1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "SparcGenInstrInfo.inc"
32 // Pin the vtable to this file.
33 void SparcInstrInfo::anchor() {}
35 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
36 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
45 int &FrameIndex) const {
46 if (MI->getOpcode() == SP::LDri ||
47 MI->getOpcode() == SP::LDXri ||
48 MI->getOpcode() == SP::LDFri ||
49 MI->getOpcode() == SP::LDDFri ||
50 MI->getOpcode() == SP::LDQFri) {
51 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
52 MI->getOperand(2).getImm() == 0) {
53 FrameIndex = MI->getOperand(1).getIndex();
54 return MI->getOperand(0).getReg();
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
65 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
66 int &FrameIndex) const {
67 if (MI->getOpcode() == SP::STri ||
68 MI->getOpcode() == SP::STXri ||
69 MI->getOpcode() == SP::STFri ||
70 MI->getOpcode() == SP::STDFri ||
71 MI->getOpcode() == SP::STQFri) {
72 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
73 MI->getOperand(1).getImm() == 0) {
74 FrameIndex = MI->getOperand(0).getIndex();
75 return MI->getOperand(2).getReg();
81 static bool IsIntegerCC(unsigned CC)
83 return (CC <= SPCC::ICC_VC);
87 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
90 case SPCC::ICC_A: return SPCC::ICC_N;
91 case SPCC::ICC_N: return SPCC::ICC_A;
92 case SPCC::ICC_NE: return SPCC::ICC_E;
93 case SPCC::ICC_E: return SPCC::ICC_NE;
94 case SPCC::ICC_G: return SPCC::ICC_LE;
95 case SPCC::ICC_LE: return SPCC::ICC_G;
96 case SPCC::ICC_GE: return SPCC::ICC_L;
97 case SPCC::ICC_L: return SPCC::ICC_GE;
98 case SPCC::ICC_GU: return SPCC::ICC_LEU;
99 case SPCC::ICC_LEU: return SPCC::ICC_GU;
100 case SPCC::ICC_CC: return SPCC::ICC_CS;
101 case SPCC::ICC_CS: return SPCC::ICC_CC;
102 case SPCC::ICC_POS: return SPCC::ICC_NEG;
103 case SPCC::ICC_NEG: return SPCC::ICC_POS;
104 case SPCC::ICC_VC: return SPCC::ICC_VS;
105 case SPCC::ICC_VS: return SPCC::ICC_VC;
107 case SPCC::FCC_A: return SPCC::FCC_N;
108 case SPCC::FCC_N: return SPCC::FCC_A;
109 case SPCC::FCC_U: return SPCC::FCC_O;
110 case SPCC::FCC_O: return SPCC::FCC_U;
111 case SPCC::FCC_G: return SPCC::FCC_ULE;
112 case SPCC::FCC_LE: return SPCC::FCC_UG;
113 case SPCC::FCC_UG: return SPCC::FCC_LE;
114 case SPCC::FCC_ULE: return SPCC::FCC_G;
115 case SPCC::FCC_L: return SPCC::FCC_UGE;
116 case SPCC::FCC_GE: return SPCC::FCC_UL;
117 case SPCC::FCC_UL: return SPCC::FCC_GE;
118 case SPCC::FCC_UGE: return SPCC::FCC_L;
119 case SPCC::FCC_LG: return SPCC::FCC_UE;
120 case SPCC::FCC_UE: return SPCC::FCC_LG;
121 case SPCC::FCC_NE: return SPCC::FCC_E;
122 case SPCC::FCC_E: return SPCC::FCC_NE;
124 llvm_unreachable("Invalid cond code");
127 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
128 MachineBasicBlock *&TBB,
129 MachineBasicBlock *&FBB,
130 SmallVectorImpl<MachineOperand> &Cond,
131 bool AllowModify) const
134 MachineBasicBlock::iterator I = MBB.end();
135 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
136 while (I != MBB.begin()) {
139 if (I->isDebugValue())
142 // When we see a non-terminator, we are done.
143 if (!isUnpredicatedTerminator(I))
146 // Terminator is not a branch.
150 // Handle Unconditional branches.
151 if (I->getOpcode() == SP::BA) {
155 TBB = I->getOperand(0).getMBB();
159 while (std::next(I) != MBB.end())
160 std::next(I)->eraseFromParent();
165 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
167 I->eraseFromParent();
169 UnCondBrIter = MBB.end();
173 TBB = I->getOperand(0).getMBB();
177 unsigned Opcode = I->getOpcode();
178 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
179 return true; // Unknown Opcode.
181 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
184 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
185 if (AllowModify && UnCondBrIter != MBB.end() &&
186 MBB.isLayoutSuccessor(TargetBB)) {
188 // Transform the code
203 BranchCode = GetOppositeBranchCondition(BranchCode);
204 MachineBasicBlock::iterator OldInst = I;
205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
206 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
207 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
210 OldInst->eraseFromParent();
211 UnCondBrIter->eraseFromParent();
213 UnCondBrIter = MBB.end();
218 TBB = I->getOperand(0).getMBB();
219 Cond.push_back(MachineOperand::CreateImm(BranchCode));
222 // FIXME: Handle subsequent conditional branches.
223 // For now, we can't handle multiple conditional branches.
230 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
231 MachineBasicBlock *FBB,
232 ArrayRef<MachineOperand> Cond,
234 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
235 assert((Cond.size() == 1 || Cond.size() == 0) &&
236 "Sparc branch conditions should have one component!");
239 assert(!FBB && "Unconditional branch with multiple successors!");
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
244 // Conditional branch
245 unsigned CC = Cond[0].getImm();
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
258 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
260 MachineBasicBlock::iterator I = MBB.end();
262 while (I != MBB.begin()) {
265 if (I->isDebugValue())
268 if (I->getOpcode() != SP::BA
269 && I->getOpcode() != SP::BCOND
270 && I->getOpcode() != SP::FBCOND)
271 break; // Not a branch
273 I->eraseFromParent();
280 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
281 MachineBasicBlock::iterator I, DebugLoc DL,
282 unsigned DestReg, unsigned SrcReg,
283 bool KillSrc) const {
284 unsigned numSubRegs = 0;
286 const unsigned *subRegIdx = nullptr;
288 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
289 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
290 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
291 SP::sub_odd64_then_sub_even,
292 SP::sub_odd64_then_sub_odd };
294 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
295 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
296 .addReg(SrcReg, getKillRegState(KillSrc));
297 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
298 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
299 .addReg(SrcReg, getKillRegState(KillSrc));
300 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
301 if (Subtarget.isV9()) {
302 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
303 .addReg(SrcReg, getKillRegState(KillSrc));
305 // Use two FMOVS instructions.
306 subRegIdx = DFP_FP_SubRegsIdx;
310 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
311 if (Subtarget.isV9()) {
312 if (Subtarget.hasHardQuad()) {
313 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
314 .addReg(SrcReg, getKillRegState(KillSrc));
316 // Use two FMOVD instructions.
317 subRegIdx = QFP_DFP_SubRegsIdx;
322 // Use four FMOVS instructions.
323 subRegIdx = QFP_FP_SubRegsIdx;
327 } else if (SP::ASRRegsRegClass.contains(DestReg) &&
328 SP::IntRegsRegClass.contains(SrcReg)) {
329 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
331 .addReg(SrcReg, getKillRegState(KillSrc));
332 } else if (SP::IntRegsRegClass.contains(DestReg) &&
333 SP::ASRRegsRegClass.contains(SrcReg)) {
334 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
335 .addReg(SrcReg, getKillRegState(KillSrc));
337 llvm_unreachable("Impossible reg-to-reg copy");
339 if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
342 const TargetRegisterInfo *TRI = &getRegisterInfo();
343 MachineInstr *MovMI = nullptr;
345 for (unsigned i = 0; i != numSubRegs; ++i) {
346 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
347 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
348 assert(Dst && Src && "Bad sub-register");
350 MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
352 // Add implicit super-register defs and kills to the last MovMI.
353 MovMI->addRegisterDefined(DestReg, TRI);
355 MovMI->addRegisterKilled(SrcReg, TRI);
358 void SparcInstrInfo::
359 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
360 unsigned SrcReg, bool isKill, int FI,
361 const TargetRegisterClass *RC,
362 const TargetRegisterInfo *TRI) const {
364 if (I != MBB.end()) DL = I->getDebugLoc();
366 MachineFunction *MF = MBB.getParent();
367 const MachineFrameInfo &MFI = *MF->getFrameInfo();
368 MachineMemOperand *MMO =
369 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
370 MachineMemOperand::MOStore,
371 MFI.getObjectSize(FI),
372 MFI.getObjectAlignment(FI));
374 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
375 if (RC == &SP::I64RegsRegClass)
376 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
377 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
378 else if (RC == &SP::IntRegsRegClass)
379 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381 else if (RC == &SP::FPRegsRegClass)
382 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
383 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
384 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
385 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
386 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
387 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
388 // Use STQFri irrespective of its legality. If STQ is not legal, it will be
389 // lowered into two STDs in eliminateFrameIndex.
390 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
391 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
393 llvm_unreachable("Can't store this register to stack slot");
396 void SparcInstrInfo::
397 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
398 unsigned DestReg, int FI,
399 const TargetRegisterClass *RC,
400 const TargetRegisterInfo *TRI) const {
402 if (I != MBB.end()) DL = I->getDebugLoc();
404 MachineFunction *MF = MBB.getParent();
405 const MachineFrameInfo &MFI = *MF->getFrameInfo();
406 MachineMemOperand *MMO =
407 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
408 MachineMemOperand::MOLoad,
409 MFI.getObjectSize(FI),
410 MFI.getObjectAlignment(FI));
412 if (RC == &SP::I64RegsRegClass)
413 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
415 else if (RC == &SP::IntRegsRegClass)
416 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
418 else if (RC == &SP::FPRegsRegClass)
419 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
422 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
425 // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
426 // lowered into two LDDs in eliminateFrameIndex.
427 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
430 llvm_unreachable("Can't load this register from stack slot");
433 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
435 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
436 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
437 if (GlobalBaseReg != 0)
438 return GlobalBaseReg;
440 // Insert the set of GlobalBaseReg into the first MBB of the function
441 MachineBasicBlock &FirstMBB = MF->front();
442 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
443 MachineRegisterInfo &RegInfo = MF->getRegInfo();
445 const TargetRegisterClass *PtrRC =
446 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
447 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
451 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
452 SparcFI->setGlobalBaseReg(GlobalBaseReg);
453 return GlobalBaseReg;