1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget->isV9()">,
33 AssemblerPredicate<"FeatureV9">;
35 // HasNoV9 - This predicate is true when the target doesn't have V9
36 // instructions. Use of this is just a hack for the isel not having proper
37 // costs for V8 instructions that are more expensive than their V9 ones.
38 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
40 // HasVIS - This is true when the target processor has VIS extensions.
41 def HasVIS : Predicate<"Subtarget->isVIS()">,
42 AssemblerPredicate<"FeatureVIS">;
43 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
44 AssemblerPredicate<"FeatureVIS2">;
45 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
46 AssemblerPredicate<"FeatureVIS3">;
48 // HasHardQuad - This is true when the target processor supports quad floating
49 // point instructions.
50 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
52 // UseDeprecatedInsts - This predicate is true when the target processor is a
53 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
54 // to use when appropriate. In either of these cases, the instruction selector
55 // will pick deprecated instructions.
56 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
58 //===----------------------------------------------------------------------===//
59 // Instruction Pattern Stuff
60 //===----------------------------------------------------------------------===//
62 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
64 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
66 def LO10 : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
71 def HI22 : SDNodeXForm<imm, [{
72 // Transformation function: shift the immediate value down into the low bits.
73 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
77 def SETHIimm : PatLeaf<(imm), [{
78 return isShiftedUInt<22, 10>(N->getZExtValue());
82 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
83 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
86 def SparcMEMrrAsmOperand : AsmOperandClass {
88 let ParserMethod = "parseMEMOperand";
91 def SparcMEMriAsmOperand : AsmOperandClass {
93 let ParserMethod = "parseMEMOperand";
96 def MEMrr : Operand<iPTR> {
97 let PrintMethod = "printMemOperand";
98 let MIOperandInfo = (ops ptr_rc, ptr_rc);
99 let ParserMatchClass = SparcMEMrrAsmOperand;
101 def MEMri : Operand<iPTR> {
102 let PrintMethod = "printMemOperand";
103 let MIOperandInfo = (ops ptr_rc, i32imm);
104 let ParserMatchClass = SparcMEMriAsmOperand;
107 def TLSSym : Operand<iPTR>;
109 // Branch targets have OtherVT type.
110 def brtarget : Operand<OtherVT> {
111 let EncoderMethod = "getBranchTargetOpValue";
114 def bprtarget : Operand<OtherVT> {
115 let EncoderMethod = "getBranchPredTargetOpValue";
118 def bprtarget16 : Operand<OtherVT> {
119 let EncoderMethod = "getBranchOnRegTargetOpValue";
122 def calltarget : Operand<i32> {
123 let EncoderMethod = "getCallTargetOpValue";
124 let DecoderMethod = "DecodeCall";
127 def simm13Op : Operand<i32> {
128 let DecoderMethod = "DecodeSIMM13";
131 // Operand for printing out a condition code.
132 let PrintMethod = "printCCOperand" in
133 def CCOp : Operand<i32>;
136 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
138 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
140 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
142 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
144 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
146 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
148 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
150 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
153 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
155 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
157 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
158 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
159 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
160 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
161 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
163 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
164 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
166 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
167 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
168 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
169 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
171 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
172 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
173 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
175 // These are target-independent nodes, but have target-specific formats.
176 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
177 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
180 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
181 [SDNPHasChain, SDNPOutGlue]>;
182 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
186 def call : SDNode<"SPISD::CALL", SDT_SPCall,
187 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
190 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
191 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
192 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
194 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
195 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
197 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
198 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
199 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
203 def getPCX : Operand<iPTR> {
204 let PrintMethod = "printGetPCX";
207 //===----------------------------------------------------------------------===//
208 // SPARC Flag Conditions
209 //===----------------------------------------------------------------------===//
211 // Note that these values must be kept in sync with the CCOp::CondCode enum
213 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
214 def ICC_NE : ICC_VAL< 9>; // Not Equal
215 def ICC_E : ICC_VAL< 1>; // Equal
216 def ICC_G : ICC_VAL<10>; // Greater
217 def ICC_LE : ICC_VAL< 2>; // Less or Equal
218 def ICC_GE : ICC_VAL<11>; // Greater or Equal
219 def ICC_L : ICC_VAL< 3>; // Less
220 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
221 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
222 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
223 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
224 def ICC_POS : ICC_VAL<14>; // Positive
225 def ICC_NEG : ICC_VAL< 6>; // Negative
226 def ICC_VC : ICC_VAL<15>; // Overflow Clear
227 def ICC_VS : ICC_VAL< 7>; // Overflow Set
229 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
230 def FCC_U : FCC_VAL<23>; // Unordered
231 def FCC_G : FCC_VAL<22>; // Greater
232 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
233 def FCC_L : FCC_VAL<20>; // Less
234 def FCC_UL : FCC_VAL<19>; // Unordered or Less
235 def FCC_LG : FCC_VAL<18>; // Less or Greater
236 def FCC_NE : FCC_VAL<17>; // Not Equal
237 def FCC_E : FCC_VAL<25>; // Equal
238 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
239 def FCC_GE : FCC_VAL<25>; // Greater or Equal
240 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
241 def FCC_LE : FCC_VAL<27>; // Less or Equal
242 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
243 def FCC_O : FCC_VAL<29>; // Ordered
245 //===----------------------------------------------------------------------===//
246 // Instruction Class Templates
247 //===----------------------------------------------------------------------===//
249 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
250 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
251 RegisterClass RC, ValueType Ty, Operand immOp> {
252 def rr : F3_1<2, Op3Val,
253 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
254 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
255 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
256 def ri : F3_2<2, Op3Val,
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
258 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
259 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
262 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
264 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
265 def rr : F3_1<2, Op3Val,
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
267 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
268 def ri : F3_2<2, Op3Val,
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
270 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
273 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
274 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
275 RegisterClass RC, ValueType Ty> {
276 def rr : F3_1<3, Op3Val,
277 (outs RC:$dst), (ins MEMrr:$addr),
278 !strconcat(OpcStr, " [$addr], $dst"),
279 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
280 def ri : F3_2<3, Op3Val,
281 (outs RC:$dst), (ins MEMri:$addr),
282 !strconcat(OpcStr, " [$addr], $dst"),
283 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
286 // LoadA multiclass - As above, but also define alternate address space variant
287 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
288 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
289 Load<OpcStr, Op3Val, OpNode, RC, Ty> {
290 // TODO: The LD*Arr instructions are currently asm only; hooking up
291 // CodeGen's address spaces to use these is a future task.
292 def Arr : F3_1_asi<3, LoadAOp3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
293 !strconcat(OpcStr, "a [$addr] $asi, $dst"),
297 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
298 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
299 RegisterClass RC, ValueType Ty> {
300 def rr : F3_1<3, Op3Val,
301 (outs), (ins MEMrr:$addr, RC:$rd),
302 !strconcat(OpcStr, " $rd, [$addr]"),
303 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
304 def ri : F3_2<3, Op3Val,
305 (outs), (ins MEMri:$addr, RC:$rd),
306 !strconcat(OpcStr, " $rd, [$addr]"),
307 [(OpNode Ty:$rd, ADDRri:$addr)]>;
310 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
311 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
312 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
313 // TODO: The ST*Arr instructions are currently asm only; hooking up
314 // CodeGen's address spaces to use these is a future task.
315 def Arr : F3_1_asi<3, StoreAOp3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
316 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
320 //===----------------------------------------------------------------------===//
322 //===----------------------------------------------------------------------===//
324 // Pseudo instructions.
325 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
326 : InstSP<outs, ins, asmstr, pattern> {
327 let isCodeGenOnly = 1;
333 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
336 let Defs = [O6], Uses = [O6] in {
337 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
338 "!ADJCALLSTACKDOWN $amt",
339 [(callseq_start timm:$amt)]>;
340 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
341 "!ADJCALLSTACKUP $amt1",
342 [(callseq_end timm:$amt1, timm:$amt2)]>;
345 let hasSideEffects = 1, mayStore = 1 in {
346 let rd = 0, rs1 = 0, rs2 = 0 in
347 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
349 [(flushw)]>, Requires<[HasV9]>;
350 let rd = 0, rs1 = 1, simm13 = 3 in
351 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
356 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
357 // instruction selection into a branch sequence. This has to handle all
358 // permutations of selection between i32/f32/f64 on ICC and FCC.
359 // Expanded after instruction selection.
360 let Uses = [ICC], usesCustomInserter = 1 in {
361 def SELECT_CC_Int_ICC
362 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
363 "; SELECT_CC_Int_ICC PSEUDO!",
364 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
366 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
367 "; SELECT_CC_FP_ICC PSEUDO!",
368 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
370 def SELECT_CC_DFP_ICC
371 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
372 "; SELECT_CC_DFP_ICC PSEUDO!",
373 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
375 def SELECT_CC_QFP_ICC
376 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
377 "; SELECT_CC_QFP_ICC PSEUDO!",
378 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
381 let usesCustomInserter = 1, Uses = [FCC0] in {
383 def SELECT_CC_Int_FCC
384 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
385 "; SELECT_CC_Int_FCC PSEUDO!",
386 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
389 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
390 "; SELECT_CC_FP_FCC PSEUDO!",
391 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
392 def SELECT_CC_DFP_FCC
393 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
394 "; SELECT_CC_DFP_FCC PSEUDO!",
395 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
396 def SELECT_CC_QFP_FCC
397 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
398 "; SELECT_CC_QFP_FCC PSEUDO!",
399 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
402 // Section B.1 - Load Integer Instructions, p. 90
403 let DecoderMethod = "DecodeLoadInt" in {
404 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
405 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
406 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
407 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
408 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
411 // Section B.2 - Load Floating-point Instructions, p. 92
412 let DecoderMethod = "DecodeLoadFP" in
413 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
414 let DecoderMethod = "DecodeLoadDFP" in
415 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
416 let DecoderMethod = "DecodeLoadQFP" in
417 defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
418 Requires<[HasV9, HasHardQuad]>;
420 // Section B.4 - Store Integer Instructions, p. 95
421 let DecoderMethod = "DecodeStoreInt" in {
422 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
423 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
424 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
427 // Section B.5 - Store Floating-point Instructions, p. 97
428 let DecoderMethod = "DecodeStoreFP" in
429 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
430 let DecoderMethod = "DecodeStoreDFP" in
431 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
432 let DecoderMethod = "DecodeStoreQFP" in
433 defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
434 Requires<[HasV9, HasHardQuad]>;
436 // Section B.8 - SWAP Register with Memory Instruction
438 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
439 def SWAPrr : F3_1<3, 0b001111,
440 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
441 "swap [$addr], $dst",
442 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
443 def SWAPri : F3_2<3, 0b001111,
444 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
445 "swap [$addr], $dst",
446 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
447 def SWAPArr : F3_1_asi<3, 0b011111,
448 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
449 "swapa [$addr] $asi, $dst",
450 [/*FIXME: pattern?*/]>;
454 // Section B.9 - SETHI Instruction, p. 104
455 def SETHIi: F2_1<0b100,
456 (outs IntRegs:$rd), (ins i32imm:$imm22),
458 [(set i32:$rd, SETHIimm:$imm22)]>;
460 // Section B.10 - NOP Instruction, p. 105
461 // (It's a special case of SETHI)
462 let rd = 0, imm22 = 0 in
463 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
465 // Section B.11 - Logical Instructions, p. 106
466 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
468 def ANDNrr : F3_1<2, 0b000101,
469 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
470 "andn $rs1, $rs2, $rd",
471 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
472 def ANDNri : F3_2<2, 0b000101,
473 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
474 "andn $rs1, $simm13, $rd", []>;
476 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
478 def ORNrr : F3_1<2, 0b000110,
479 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
480 "orn $rs1, $rs2, $rd",
481 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
482 def ORNri : F3_2<2, 0b000110,
483 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
484 "orn $rs1, $simm13, $rd", []>;
485 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
487 def XNORrr : F3_1<2, 0b000111,
488 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
489 "xnor $rs1, $rs2, $rd",
490 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
491 def XNORri : F3_2<2, 0b000111,
492 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
493 "xnor $rs1, $simm13, $rd", []>;
495 let Defs = [ICC] in {
496 defm ANDCC : F3_12np<"andcc", 0b010001>;
497 defm ANDNCC : F3_12np<"andncc", 0b010101>;
498 defm ORCC : F3_12np<"orcc", 0b010010>;
499 defm ORNCC : F3_12np<"orncc", 0b010110>;
500 defm XORCC : F3_12np<"xorcc", 0b010011>;
501 defm XNORCC : F3_12np<"xnorcc", 0b010111>;
504 // Section B.12 - Shift Instructions, p. 107
505 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
506 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
507 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
509 // Section B.13 - Add Instructions, p. 108
510 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
512 // "LEA" forms of add (patterns to make tblgen happy)
513 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
514 def LEA_ADDri : F3_2<2, 0b000000,
515 (outs IntRegs:$dst), (ins MEMri:$addr),
516 "add ${addr:arith}, $dst",
517 [(set iPTR:$dst, ADDRri:$addr)]>;
520 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
523 defm ADDC : F3_12np<"addx", 0b001000>;
525 let Uses = [ICC], Defs = [ICC] in
526 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
528 // Section B.15 - Subtract Instructions, p. 110
529 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
530 let Uses = [ICC], Defs = [ICC] in
531 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
534 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
537 defm SUBC : F3_12np <"subx", 0b001100>;
539 // cmp (from Section A.3) is a specialized alias for subcc
540 let Defs = [ICC], rd = 0 in {
541 def CMPrr : F3_1<2, 0b010100,
542 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
544 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
545 def CMPri : F3_2<2, 0b010100,
546 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
548 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
551 // Section B.18 - Multiply Instructions, p. 113
553 defm UMUL : F3_12np<"umul", 0b001010>;
554 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
557 let Defs = [Y, ICC] in {
558 defm UMULCC : F3_12np<"umulcc", 0b011010>;
559 defm SMULCC : F3_12np<"smulcc", 0b011011>;
562 // Section B.19 - Divide Instructions, p. 115
563 let Uses = [Y], Defs = [Y] in {
564 defm UDIV : F3_12np<"udiv", 0b001110>;
565 defm SDIV : F3_12np<"sdiv", 0b001111>;
568 let Uses = [Y], Defs = [Y, ICC] in {
569 defm UDIVCC : F3_12np<"udivcc", 0b011110>;
570 defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
573 // Section B.20 - SAVE and RESTORE, p. 117
574 defm SAVE : F3_12np<"save" , 0b111100>;
575 defm RESTORE : F3_12np<"restore", 0b111101>;
577 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
579 // unconditional branch class.
580 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
581 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
583 let isTerminator = 1;
584 let hasDelaySlot = 1;
589 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
592 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
594 // conditional branch class:
595 class BranchSP<dag ins, string asmstr, list<dag> pattern>
596 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
598 // conditional branch with annul class:
599 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
600 : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
602 // Conditional branch class on %icc|%xcc with predication:
603 multiclass IPredBranch<string regstr, list<dag> CCPattern> {
604 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
605 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
607 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
608 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
610 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
611 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
613 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
614 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
618 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
621 // Indirect branch instructions.
622 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
623 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
624 def BINDrr : F3_1<2, 0b111000,
625 (outs), (ins MEMrr:$ptr),
627 [(brind ADDRrr:$ptr)]>;
628 def BINDri : F3_2<2, 0b111000,
629 (outs), (ins MEMri:$ptr),
631 [(brind ADDRri:$ptr)]>;
634 let Uses = [ICC] in {
635 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
637 [(SPbricc bb:$imm22, imm:$cond)]>;
638 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
639 "b$cond,a $imm22", []>;
641 let Predicates = [HasV9], cc = 0b00 in
642 defm BPI : IPredBranch<"%icc", []>;
645 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
647 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
649 // floating-point conditional branch class:
650 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
651 : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
653 // floating-point conditional branch with annul class:
654 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
655 : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
657 // Conditional branch class on %fcc0-%fcc3 with predication:
658 multiclass FPredBranch {
659 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
661 "fb$cond $cc, $imm19", []>;
662 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
664 "fb$cond,a $cc, $imm19", []>;
665 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
667 "fb$cond,pn $cc, $imm19", []>;
668 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
670 "fb$cond,a,pn $cc, $imm19", []>;
672 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
674 let Uses = [FCC0] in {
675 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
677 [(SPbrfcc bb:$imm22, imm:$cond)]>;
678 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
679 "fb$cond,a $imm22", []>;
682 let Predicates = [HasV9] in
683 defm BPF : FPredBranch;
686 // Section B.24 - Call and Link Instruction, p. 125
687 // This is the only Format 1 instruction
689 hasDelaySlot = 1, isCall = 1 in {
690 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
694 let Inst{29-0} = disp;
697 // indirect calls: special cases of JMPL.
698 let isCodeGenOnly = 1, rd = 15 in {
699 def CALLrr : F3_1<2, 0b111000,
700 (outs), (ins MEMrr:$ptr, variable_ops),
702 [(call ADDRrr:$ptr)]>;
703 def CALLri : F3_2<2, 0b111000,
704 (outs), (ins MEMri:$ptr, variable_ops),
706 [(call ADDRri:$ptr)]>;
710 // Section B.25 - Jump and Link Instruction
713 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
714 DecoderMethod = "DecodeJMPL" in {
715 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
716 "jmpl $addr, $dst", []>;
717 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
718 "jmpl $addr, $dst", []>;
721 // Section A.3 - Synthetic Instructions, p. 85
722 // special cases of JMPL:
723 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
724 isCodeGenOnly = 1 in {
725 let rd = 0, rs1 = 15 in
726 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
727 "jmp %o7+$val", [(retflag simm13:$val)]>;
729 let rd = 0, rs1 = 31 in
730 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
734 // Section B.26 - Return from Trap Instruction
735 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
736 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
737 def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
739 def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
744 // Section B.27 - Trap on Integer Condition Codes Instruction
745 multiclass TRAP<string regStr> {
746 def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
748 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
749 def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
751 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
754 let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
755 defm TICC : TRAP<"%icc">;
757 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
758 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
760 // Section B.28 - Read State Register Instructions
762 def RDASR : F3_1<2, 0b101000,
763 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
766 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
767 let Predicates = [HasNoV9] in {
768 let rs2 = 0, rs1 = 0, Uses=[PSR] in
769 def RDPSR : F3_1<2, 0b101001,
770 (outs IntRegs:$rd), (ins),
773 let rs2 = 0, rs1 = 0, Uses=[WIM] in
774 def RDWIM : F3_1<2, 0b101010,
775 (outs IntRegs:$rd), (ins),
778 let rs2 = 0, rs1 = 0, Uses=[TBR] in
779 def RDTBR : F3_1<2, 0b101011,
780 (outs IntRegs:$rd), (ins),
784 // Section B.29 - Write State Register Instructions
785 def WRASRrr : F3_1<2, 0b110000,
786 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
787 "wr $rs1, $rs2, $rd", []>;
788 def WRASRri : F3_2<2, 0b110000,
789 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
790 "wr $rs1, $simm13, $rd", []>;
792 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
793 let Predicates = [HasNoV9] in {
794 let Defs = [PSR], rd=0 in {
795 def WRPSRrr : F3_1<2, 0b110001,
796 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
797 "wr $rs1, $rs2, %psr", []>;
798 def WRPSRri : F3_2<2, 0b110001,
799 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
800 "wr $rs1, $simm13, %psr", []>;
803 let Defs = [WIM], rd=0 in {
804 def WRWIMrr : F3_1<2, 0b110010,
805 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
806 "wr $rs1, $rs2, %wim", []>;
807 def WRWIMri : F3_2<2, 0b110010,
808 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
809 "wr $rs1, $simm13, %wim", []>;
812 let Defs = [TBR], rd=0 in {
813 def WRTBRrr : F3_1<2, 0b110011,
814 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
815 "wr $rs1, $rs2, %tbr", []>;
816 def WRTBRri : F3_2<2, 0b110011,
817 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
818 "wr $rs1, $simm13, %tbr", []>;
822 // Section B.30 - STBAR Instruction
823 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
824 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
827 // Section B.31 - Unimplmented Instruction
829 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
832 // Section B.32 - Flush Instruction Memory
834 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
836 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
839 // The no-arg FLUSH is only here for the benefit of the InstAlias
840 // "flush", which cannot seem to use FLUSHrr, due to the inability
841 // to construct a MEMrr with fixed G0 registers.
842 let rs1 = 0, rs2 = 0 in
843 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
846 // Section B.33 - Floating-point Operate (FPop) Instructions
848 // Convert Integer to Floating-point Instructions, p. 141
849 def FITOS : F3_3u<2, 0b110100, 0b011000100,
850 (outs FPRegs:$rd), (ins FPRegs:$rs2),
852 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
853 def FITOD : F3_3u<2, 0b110100, 0b011001000,
854 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
856 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
857 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
858 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
860 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
861 Requires<[HasHardQuad]>;
863 // Convert Floating-point to Integer Instructions, p. 142
864 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
865 (outs FPRegs:$rd), (ins FPRegs:$rs2),
867 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
868 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
869 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
871 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
872 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
873 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
875 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
876 Requires<[HasHardQuad]>;
878 // Convert between Floating-point Formats Instructions, p. 143
879 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
880 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
882 [(set f64:$rd, (fextend f32:$rs2))]>;
883 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
884 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
886 [(set f128:$rd, (fextend f32:$rs2))]>,
887 Requires<[HasHardQuad]>;
888 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
889 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
891 [(set f32:$rd, (fround f64:$rs2))]>;
892 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
893 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
895 [(set f128:$rd, (fextend f64:$rs2))]>,
896 Requires<[HasHardQuad]>;
897 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
898 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
900 [(set f32:$rd, (fround f128:$rs2))]>,
901 Requires<[HasHardQuad]>;
902 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
903 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
905 [(set f64:$rd, (fround f128:$rs2))]>,
906 Requires<[HasHardQuad]>;
908 // Floating-point Move Instructions, p. 144
909 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
910 (outs FPRegs:$rd), (ins FPRegs:$rs2),
911 "fmovs $rs2, $rd", []>;
912 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
913 (outs FPRegs:$rd), (ins FPRegs:$rs2),
915 [(set f32:$rd, (fneg f32:$rs2))]>;
916 def FABSS : F3_3u<2, 0b110100, 0b000001001,
917 (outs FPRegs:$rd), (ins FPRegs:$rs2),
919 [(set f32:$rd, (fabs f32:$rs2))]>;
922 // Floating-point Square Root Instructions, p.145
923 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
924 (outs FPRegs:$rd), (ins FPRegs:$rs2),
926 [(set f32:$rd, (fsqrt f32:$rs2))]>;
927 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
928 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
930 [(set f64:$rd, (fsqrt f64:$rs2))]>;
931 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
932 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
934 [(set f128:$rd, (fsqrt f128:$rs2))]>,
935 Requires<[HasHardQuad]>;
939 // Floating-point Add and Subtract Instructions, p. 146
940 def FADDS : F3_3<2, 0b110100, 0b001000001,
941 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
942 "fadds $rs1, $rs2, $rd",
943 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
944 def FADDD : F3_3<2, 0b110100, 0b001000010,
945 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
946 "faddd $rs1, $rs2, $rd",
947 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
948 def FADDQ : F3_3<2, 0b110100, 0b001000011,
949 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
950 "faddq $rs1, $rs2, $rd",
951 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
952 Requires<[HasHardQuad]>;
954 def FSUBS : F3_3<2, 0b110100, 0b001000101,
955 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
956 "fsubs $rs1, $rs2, $rd",
957 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
958 def FSUBD : F3_3<2, 0b110100, 0b001000110,
959 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
960 "fsubd $rs1, $rs2, $rd",
961 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
962 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
963 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
964 "fsubq $rs1, $rs2, $rd",
965 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
966 Requires<[HasHardQuad]>;
969 // Floating-point Multiply and Divide Instructions, p. 147
970 def FMULS : F3_3<2, 0b110100, 0b001001001,
971 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
972 "fmuls $rs1, $rs2, $rd",
973 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
974 def FMULD : F3_3<2, 0b110100, 0b001001010,
975 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
976 "fmuld $rs1, $rs2, $rd",
977 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
978 def FMULQ : F3_3<2, 0b110100, 0b001001011,
979 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
980 "fmulq $rs1, $rs2, $rd",
981 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
982 Requires<[HasHardQuad]>;
984 def FSMULD : F3_3<2, 0b110100, 0b001101001,
985 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
986 "fsmuld $rs1, $rs2, $rd",
987 [(set f64:$rd, (fmul (fextend f32:$rs1),
988 (fextend f32:$rs2)))]>;
989 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
990 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
991 "fdmulq $rs1, $rs2, $rd",
992 [(set f128:$rd, (fmul (fextend f64:$rs1),
993 (fextend f64:$rs2)))]>,
994 Requires<[HasHardQuad]>;
996 def FDIVS : F3_3<2, 0b110100, 0b001001101,
997 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
998 "fdivs $rs1, $rs2, $rd",
999 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
1000 def FDIVD : F3_3<2, 0b110100, 0b001001110,
1001 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1002 "fdivd $rs1, $rs2, $rd",
1003 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
1004 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
1005 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1006 "fdivq $rs1, $rs2, $rd",
1007 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1008 Requires<[HasHardQuad]>;
1010 // Floating-point Compare Instructions, p. 148
1011 // Note: the 2nd template arg is different for these guys.
1012 // Note 2: the result of a FCMP is not available until the 2nd cycle
1013 // after the instr is retired, but there is no interlock in Sparc V8.
1014 // This behavior is modeled with a forced noop after the instruction in
1017 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1018 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
1019 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1021 [(SPcmpfcc f32:$rs1, f32:$rs2)]>;
1022 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
1023 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1025 [(SPcmpfcc f64:$rs1, f64:$rs2)]>;
1026 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1027 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1029 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1030 Requires<[HasHardQuad]>;
1033 //===----------------------------------------------------------------------===//
1034 // Instructions for Thread Local Storage(TLS).
1035 //===----------------------------------------------------------------------===//
1036 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
1037 def TLS_ADDrr : F3_1<2, 0b000000,
1039 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1040 "add $rs1, $rs2, $rd, $sym",
1042 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1045 def TLS_LDrr : F3_1<3, 0b000000,
1046 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1047 "ld [$addr], $dst, $sym",
1049 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
1051 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
1052 def TLS_CALL : InstSP<(outs),
1053 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1055 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
1058 let Inst{29-0} = disp;
1062 //===----------------------------------------------------------------------===//
1064 //===----------------------------------------------------------------------===//
1066 // V9 Conditional Moves.
1067 let Predicates = [HasV9], Constraints = "$f = $rd" in {
1068 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
1069 let Uses = [ICC], intcc = 1, cc = 0b00 in {
1071 : F4_1<0b101100, (outs IntRegs:$rd),
1072 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1073 "mov$cond %icc, $rs2, $rd",
1074 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1077 : F4_2<0b101100, (outs IntRegs:$rd),
1078 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1079 "mov$cond %icc, $simm11, $rd",
1081 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1084 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1086 : F4_1<0b101100, (outs IntRegs:$rd),
1087 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1088 "mov$cond %fcc0, $rs2, $rd",
1089 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1091 : F4_2<0b101100, (outs IntRegs:$rd),
1092 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1093 "mov$cond %fcc0, $simm11, $rd",
1095 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1098 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
1100 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1101 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1102 "fmovs$cond %icc, $rs2, $rd",
1103 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1105 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1106 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1107 "fmovd$cond %icc, $rs2, $rd",
1108 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1110 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1111 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1112 "fmovq$cond %icc, $rs2, $rd",
1113 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1114 Requires<[HasHardQuad]>;
1117 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
1119 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1120 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1121 "fmovs$cond %fcc0, $rs2, $rd",
1122 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1124 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1125 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1126 "fmovd$cond %fcc0, $rs2, $rd",
1127 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1129 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1130 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1131 "fmovq$cond %fcc0, $rs2, $rd",
1132 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1133 Requires<[HasHardQuad]>;
1138 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1139 let Predicates = [HasV9] in {
1140 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1141 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1142 "fmovd $rs2, $rd", []>;
1143 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1144 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1145 "fmovq $rs2, $rd", []>,
1146 Requires<[HasHardQuad]>;
1147 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1148 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1150 [(set f64:$rd, (fneg f64:$rs2))]>;
1151 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1152 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1154 [(set f128:$rd, (fneg f128:$rs2))]>,
1155 Requires<[HasHardQuad]>;
1156 def FABSD : F3_3u<2, 0b110100, 0b000001010,
1157 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1159 [(set f64:$rd, (fabs f64:$rs2))]>;
1160 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1161 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1163 [(set f128:$rd, (fabs f128:$rs2))]>,
1164 Requires<[HasHardQuad]>;
1167 // Floating-point compare instruction with %fcc0-%fcc3.
1168 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
1169 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1170 "fcmps $rd, $rs1, $rs2", []>;
1171 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
1172 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1173 "fcmpd $rd, $rs1, $rs2", []>;
1174 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1175 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1176 "fcmpq $rd, $rs1, $rs2", []>,
1177 Requires<[HasHardQuad]>;
1179 let hasSideEffects = 1 in {
1180 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
1181 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1182 "fcmpes $rd, $rs1, $rs2", []>;
1183 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
1184 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1185 "fcmped $rd, $rs1, $rs2", []>;
1186 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
1187 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1188 "fcmpeq $rd, $rs1, $rs2", []>,
1189 Requires<[HasHardQuad]>;
1192 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1193 let Predicates = [HasV9] in {
1194 let Constraints = "$f = $rd", intcc = 0 in {
1196 : F4_1<0b101100, (outs IntRegs:$rd),
1197 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1198 "mov$cond $cc, $rs2, $rd", []>;
1200 : F4_2<0b101100, (outs IntRegs:$rd),
1201 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1202 "mov$cond $cc, $simm11, $rd", []>;
1204 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1205 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1206 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1208 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1209 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1210 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1212 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1213 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1214 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1215 Requires<[HasHardQuad]>;
1216 } // Constraints = "$f = $rd", ...
1217 } // let Predicates = [hasV9]
1220 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1221 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1223 def POPCrr : F3_1<2, 0b101110,
1224 (outs IntRegs:$dst), (ins IntRegs:$src),
1225 "popc $src, $dst", []>, Requires<[HasV9]>;
1226 def : Pat<(ctpop i32:$src),
1227 (POPCrr (SRLri $src, 0))>;
1229 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1230 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1231 "membar $simm13", []>;
1233 // TODO: Should add a CASArr variant. In fact, the CAS instruction,
1234 // unlike other instructions, only comes in a form which requires an
1235 // ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
1236 // default unprivileged ASI for SparcV9. (Also of note: some modern
1237 // SparcV8 implementations provide CASA as an extension, but require
1238 // the use of SparcV8's default ASI, 0xA ("User Data") instead.)
1239 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1240 def CASrr: F3_1_asi<3, 0b111100,
1241 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1243 "cas [$rs1], $rs2, $rd",
1245 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1247 let Defs = [ICC] in {
1248 defm TADDCC : F3_12np<"taddcc", 0b100000>;
1249 defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
1251 let hasSideEffects = 1 in {
1252 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1253 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1257 //===----------------------------------------------------------------------===//
1258 // Non-Instruction Patterns
1259 //===----------------------------------------------------------------------===//
1261 // Small immediates.
1262 def : Pat<(i32 simm13:$val),
1263 (ORri (i32 G0), imm:$val)>;
1264 // Arbitrary immediates.
1265 def : Pat<(i32 imm:$val),
1266 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1269 // Global addresses, constant pool entries
1270 let Predicates = [Is32Bit] in {
1272 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1273 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1274 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1275 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1277 // GlobalTLS addresses
1278 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1279 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1280 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1281 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1282 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1283 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1286 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1287 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1289 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1290 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1291 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1292 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1293 (ADDri $r, tblockaddress:$in)>;
1297 def : Pat<(call tglobaladdr:$dst),
1298 (CALL tglobaladdr:$dst)>;
1299 def : Pat<(call texternalsym:$dst),
1300 (CALL texternalsym:$dst)>;
1302 // Map integer extload's to zextloads.
1303 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1304 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1305 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1306 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1307 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1308 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1310 // zextload bool -> zextload byte
1311 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1312 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1314 // store 0, addr -> store %g0, addr
1315 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1316 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1318 // store bar for all atomic_fence in V8.
1319 let Predicates = [HasNoV9] in
1320 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1322 // atomic_load_32 addr -> load addr
1323 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1324 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1326 // atomic_store_32 val, addr -> store val, addr
1327 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1328 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1331 include "SparcInstr64Bit.td"
1332 include "SparcInstrVIS.td"
1333 include "SparcInstrAliases.td"