1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcV8InstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // HasV9 - This predicate is true when the target processor supports V9
25 // instructions. Note that the machine may be running in 32-bit mode.
26 def HasV9 : Predicate<"Subtarget.isV9()">;
28 // HasNoV9 - This predicate is true when the target doesn't have V9
29 // instructions. Use of this is just a hack for the isel not having proper
30 // costs for V8 instructions that are more expensive than their V9 ones.
31 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
33 // HasVIS - This is true when the target processor has VIS extensions.
34 def HasVIS : Predicate<"Subtarget.isVIS()">;
36 // UseDeprecatedInsts - This predicate is true when the target processor is a
37 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38 // to use when appropriate. In either of these cases, the instruction selector
39 // will pick deprecated instructions.
40 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
42 //===----------------------------------------------------------------------===//
43 // Instruction Pattern Stuff
44 //===----------------------------------------------------------------------===//
46 def simm13 : PatLeaf<(imm), [{
47 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
48 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
51 def LO10 : SDNodeXForm<imm, [{
52 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
55 def HI22 : SDNodeXForm<imm, [{
56 // Transformation function: shift the immediate value down into the low bits.
57 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
60 def SETHIimm : PatLeaf<(imm), [{
61 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
65 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
66 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
69 def MEMrr : Operand<i32> {
70 let PrintMethod = "printMemOperand";
71 let NumMIOperands = 2;
72 let MIOperandInfo = (ops IntRegs, IntRegs);
74 def MEMri : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let NumMIOperands = 2;
77 let MIOperandInfo = (ops IntRegs, i32imm);
80 // Branch targets have OtherVT type.
81 def brtarget : Operand<OtherVT>;
82 def calltarget : Operand<i32>;
85 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
87 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
88 SDTCisVT<2, FlagVT>]>;
90 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
91 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
93 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
95 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
97 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
98 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
99 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
100 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
102 def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
103 def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
105 def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
106 def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
108 def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
109 def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
111 // These are target-independent nodes, but have target-specific formats.
112 def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
113 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
114 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
116 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
117 def call : SDNode<"V8ISD::CALL", SDT_V8Call,
118 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
120 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
121 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
122 [SDNPHasChain, SDNPOptInFlag]>;
124 //===----------------------------------------------------------------------===//
125 // SPARC Flag Conditions
126 //===----------------------------------------------------------------------===//
128 // Note that these values must be kept in sync with the V8CC::CondCode enum
130 def ICC_NE : PatLeaf<(i32 9)>; // Not Equal
131 def ICC_E : PatLeaf<(i32 1)>; // Equal
132 def ICC_G : PatLeaf<(i32 10)>; // Greater
133 def ICC_LE : PatLeaf<(i32 2)>; // Less or Equal
134 def ICC_GE : PatLeaf<(i32 11)>; // Greater or Equal
135 def ICC_L : PatLeaf<(i32 3)>; // Less
136 def ICC_GU : PatLeaf<(i32 12)>; // Greater Unsigned
137 def ICC_LEU : PatLeaf<(i32 4)>; // Less or Equal Unsigned
138 def ICC_CC : PatLeaf<(i32 13)>; // Carry Clear/Great or Equal Unsigned
139 def ICC_CS : PatLeaf<(i32 5)>; // Carry Set/Less Unsigned
140 def ICC_POS : PatLeaf<(i32 14)>; // Positive
141 def ICC_NEG : PatLeaf<(i32 6)>; // Negative
142 def ICC_VC : PatLeaf<(i32 15)>; // Overflow Clear
143 def ICC_VS : PatLeaf<(i32 7)>; // Overflow Set
145 def FCC_U : PatLeaf<(i32 23)>; // Unordered
146 def FCC_G : PatLeaf<(i32 22)>; // Greater
147 def FCC_UG : PatLeaf<(i32 21)>; // Unordered or Greater
148 def FCC_L : PatLeaf<(i32 20)>; // Less
149 def FCC_UL : PatLeaf<(i32 19)>; // Unordered or Less
150 def FCC_LG : PatLeaf<(i32 18)>; // Less or Greater
151 def FCC_NE : PatLeaf<(i32 17)>; // Not Equal
152 def FCC_E : PatLeaf<(i32 25)>; // Equal
153 def FCC_UE : PatLeaf<(i32 24)>; // Unordered or Equal
154 def FCC_GE : PatLeaf<(i32 25)>; // Greater or Equal
155 def FCC_UGE : PatLeaf<(i32 26)>; // Unordered or Greater or Equal
156 def FCC_LE : PatLeaf<(i32 27)>; // Less or Equal
157 def FCC_ULE : PatLeaf<(i32 28)>; // Unordered or Less or Equal
158 def FCC_O : PatLeaf<(i32 29)>; // Ordered
161 //===----------------------------------------------------------------------===//
163 //===----------------------------------------------------------------------===//
165 // Pseudo instructions.
166 class Pseudo<dag ops, string asmstr, list<dag> pattern>
167 : InstV8<ops, asmstr, pattern>;
169 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
170 "!ADJCALLSTACKDOWN $amt",
171 [(callseq_start imm:$amt)]>;
172 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
173 "!ADJCALLSTACKUP $amt",
174 [(callseq_end imm:$amt)]>;
175 def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
176 "!IMPLICIT_DEF $dst",
177 [(set IntRegs:$dst, (undef))]>;
178 def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
179 [(set FPRegs:$dst, (undef))]>;
180 def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
181 [(set DFPRegs:$dst, (undef))]>;
183 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
185 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
186 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
187 "!FpMOVD $src, $dst", []>;
188 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
189 "!FpNEGD $src, $dst",
190 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
191 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
192 "!FpABSD $src, $dst",
193 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
196 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
197 // scheduler into a branch sequence. This has to handle all permutations of
198 // selection between i32/f32/f64 on ICC and FCC.
199 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
200 def SELECT_CC_Int_ICC
201 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
202 "; SELECT_CC_Int_ICC PSEUDO!",
203 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
205 def SELECT_CC_Int_FCC
206 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
207 "; SELECT_CC_Int_FCC PSEUDO!",
208 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
211 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
212 "; SELECT_CC_FP_ICC PSEUDO!",
213 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
216 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
217 "; SELECT_CC_FP_FCC PSEUDO!",
218 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
220 def SELECT_CC_DFP_ICC
221 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
222 "; SELECT_CC_DFP_ICC PSEUDO!",
223 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
225 def SELECT_CC_DFP_FCC
226 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
227 "; SELECT_CC_DFP_FCC PSEUDO!",
228 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
233 // Section A.3 - Synthetic Instructions, p. 85
234 // special cases of JMPL:
235 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
236 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
237 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
240 // Section B.1 - Load Integer Instructions, p. 90
241 def LDSBrr : F3_1<3, 0b001001,
242 (ops IntRegs:$dst, MEMrr:$addr),
243 "ldsb [$addr], $dst",
244 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
245 def LDSBri : F3_2<3, 0b001001,
246 (ops IntRegs:$dst, MEMri:$addr),
247 "ldsb [$addr], $dst",
248 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
249 def LDSHrr : F3_1<3, 0b001010,
250 (ops IntRegs:$dst, MEMrr:$addr),
251 "ldsh [$addr], $dst",
252 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
253 def LDSHri : F3_2<3, 0b001010,
254 (ops IntRegs:$dst, MEMri:$addr),
255 "ldsh [$addr], $dst",
256 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
257 def LDUBrr : F3_1<3, 0b000001,
258 (ops IntRegs:$dst, MEMrr:$addr),
259 "ldub [$addr], $dst",
260 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
261 def LDUBri : F3_2<3, 0b000001,
262 (ops IntRegs:$dst, MEMri:$addr),
263 "ldub [$addr], $dst",
264 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
265 def LDUHrr : F3_1<3, 0b000010,
266 (ops IntRegs:$dst, MEMrr:$addr),
267 "lduh [$addr], $dst",
268 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
269 def LDUHri : F3_2<3, 0b000010,
270 (ops IntRegs:$dst, MEMri:$addr),
271 "lduh [$addr], $dst",
272 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
273 def LDrr : F3_1<3, 0b000000,
274 (ops IntRegs:$dst, MEMrr:$addr),
276 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
277 def LDri : F3_2<3, 0b000000,
278 (ops IntRegs:$dst, MEMri:$addr),
280 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
282 // Section B.2 - Load Floating-point Instructions, p. 92
283 def LDFrr : F3_1<3, 0b100000,
284 (ops FPRegs:$dst, MEMrr:$addr),
286 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
287 def LDFri : F3_2<3, 0b100000,
288 (ops FPRegs:$dst, MEMri:$addr),
290 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
291 def LDDFrr : F3_1<3, 0b100011,
292 (ops DFPRegs:$dst, MEMrr:$addr),
294 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
295 def LDDFri : F3_2<3, 0b100011,
296 (ops DFPRegs:$dst, MEMri:$addr),
298 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
300 // Section B.4 - Store Integer Instructions, p. 95
301 def STBrr : F3_1<3, 0b000101,
302 (ops MEMrr:$addr, IntRegs:$src),
304 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
305 def STBri : F3_2<3, 0b000101,
306 (ops MEMri:$addr, IntRegs:$src),
308 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
309 def STHrr : F3_1<3, 0b000110,
310 (ops MEMrr:$addr, IntRegs:$src),
312 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
313 def STHri : F3_2<3, 0b000110,
314 (ops MEMri:$addr, IntRegs:$src),
316 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
317 def STrr : F3_1<3, 0b000100,
318 (ops MEMrr:$addr, IntRegs:$src),
320 [(store IntRegs:$src, ADDRrr:$addr)]>;
321 def STri : F3_2<3, 0b000100,
322 (ops MEMri:$addr, IntRegs:$src),
324 [(store IntRegs:$src, ADDRri:$addr)]>;
326 // Section B.5 - Store Floating-point Instructions, p. 97
327 def STFrr : F3_1<3, 0b100100,
328 (ops MEMrr:$addr, FPRegs:$src),
330 [(store FPRegs:$src, ADDRrr:$addr)]>;
331 def STFri : F3_2<3, 0b100100,
332 (ops MEMri:$addr, FPRegs:$src),
334 [(store FPRegs:$src, ADDRri:$addr)]>;
335 def STDFrr : F3_1<3, 0b100111,
336 (ops MEMrr:$addr, DFPRegs:$src),
338 [(store DFPRegs:$src, ADDRrr:$addr)]>;
339 def STDFri : F3_2<3, 0b100111,
340 (ops MEMri:$addr, DFPRegs:$src),
342 [(store DFPRegs:$src, ADDRri:$addr)]>;
344 // Section B.9 - SETHI Instruction, p. 104
345 def SETHIi: F2_1<0b100,
346 (ops IntRegs:$dst, i32imm:$src),
348 [(set IntRegs:$dst, SETHIimm:$src)]>;
350 // Section B.10 - NOP Instruction, p. 105
351 // (It's a special case of SETHI)
352 let rd = 0, imm22 = 0 in
353 def NOP : F2_1<0b100, (ops), "nop", []>;
355 // Section B.11 - Logical Instructions, p. 106
356 def ANDrr : F3_1<2, 0b000001,
357 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
359 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
360 def ANDri : F3_2<2, 0b000001,
361 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
363 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
364 def ANDNrr : F3_1<2, 0b000101,
365 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
367 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
368 def ANDNri : F3_2<2, 0b000101,
369 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
370 "andn $b, $c, $dst", []>;
371 def ORrr : F3_1<2, 0b000010,
372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
374 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
375 def ORri : F3_2<2, 0b000010,
376 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
378 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
379 def ORNrr : F3_1<2, 0b000110,
380 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
382 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
383 def ORNri : F3_2<2, 0b000110,
384 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
385 "orn $b, $c, $dst", []>;
386 def XORrr : F3_1<2, 0b000011,
387 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
389 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
390 def XORri : F3_2<2, 0b000011,
391 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
393 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
394 def XNORrr : F3_1<2, 0b000111,
395 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
397 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
398 def XNORri : F3_2<2, 0b000111,
399 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
400 "xnor $b, $c, $dst", []>;
402 // Section B.12 - Shift Instructions, p. 107
403 def SLLrr : F3_1<2, 0b100101,
404 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
406 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
407 def SLLri : F3_2<2, 0b100101,
408 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
410 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
411 def SRLrr : F3_1<2, 0b100110,
412 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
414 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
415 def SRLri : F3_2<2, 0b100110,
416 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
418 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
419 def SRArr : F3_1<2, 0b100111,
420 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
422 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
423 def SRAri : F3_2<2, 0b100111,
424 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
426 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
428 // Section B.13 - Add Instructions, p. 108
429 def ADDrr : F3_1<2, 0b000000,
430 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
432 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
433 def ADDri : F3_2<2, 0b000000,
434 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
436 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
437 def ADDCCrr : F3_1<2, 0b010000,
438 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
439 "addcc $b, $c, $dst", []>;
440 def ADDCCri : F3_2<2, 0b010000,
441 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
442 "addcc $b, $c, $dst", []>;
443 def ADDXrr : F3_1<2, 0b001000,
444 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
445 "addx $b, $c, $dst", []>;
446 def ADDXri : F3_2<2, 0b001000,
447 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
448 "addx $b, $c, $dst", []>;
450 // Section B.15 - Subtract Instructions, p. 110
451 def SUBrr : F3_1<2, 0b000100,
452 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
454 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
455 def SUBri : F3_2<2, 0b000100,
456 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
458 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
459 def SUBXrr : F3_1<2, 0b001100,
460 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
461 "subx $b, $c, $dst", []>;
462 def SUBXri : F3_2<2, 0b001100,
463 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
464 "subx $b, $c, $dst", []>;
465 def SUBCCrr : F3_1<2, 0b010100,
466 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
467 "subcc $b, $c, $dst",
468 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
469 def SUBCCri : F3_2<2, 0b010100,
470 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
471 "subcc $b, $c, $dst",
472 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
473 def SUBXCCrr: F3_1<2, 0b011100,
474 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
475 "subxcc $b, $c, $dst", []>;
477 // Section B.18 - Multiply Instructions, p. 113
478 def UMULrr : F3_1<2, 0b001010,
479 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
480 "umul $b, $c, $dst", []>;
481 def UMULri : F3_2<2, 0b001010,
482 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
483 "umul $b, $c, $dst", []>;
484 def SMULrr : F3_1<2, 0b001011,
485 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
487 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
488 def SMULri : F3_2<2, 0b001011,
489 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
491 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
493 // Section B.19 - Divide Instructions, p. 115
494 def UDIVrr : F3_1<2, 0b001110,
495 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
496 "udiv $b, $c, $dst", []>;
497 def UDIVri : F3_2<2, 0b001110,
498 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
499 "udiv $b, $c, $dst", []>;
500 def SDIVrr : F3_1<2, 0b001111,
501 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
502 "sdiv $b, $c, $dst", []>;
503 def SDIVri : F3_2<2, 0b001111,
504 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
505 "sdiv $b, $c, $dst", []>;
507 // Section B.20 - SAVE and RESTORE, p. 117
508 def SAVErr : F3_1<2, 0b111100,
509 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
510 "save $b, $c, $dst", []>;
511 def SAVEri : F3_2<2, 0b111100,
512 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
513 "save $b, $c, $dst", []>;
514 def RESTORErr : F3_1<2, 0b111101,
515 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
516 "restore $b, $c, $dst", []>;
517 def RESTOREri : F3_2<2, 0b111101,
518 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
519 "restore $b, $c, $dst", []>;
521 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
523 // conditional branch class:
524 class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
525 : F2_2<cc, 0b010, ops, asmstr, pattern> {
527 let isTerminator = 1;
528 let hasDelaySlot = 1;
533 def BA : BranchV8<0b1000, (ops brtarget:$dst),
536 def BNE : BranchV8<0b1001, (ops brtarget:$dst),
538 [(V8bricc bb:$dst, ICC_NE, ICC)]>;
539 def BE : BranchV8<0b0001, (ops brtarget:$dst),
541 [(V8bricc bb:$dst, ICC_E, ICC)]>;
542 def BG : BranchV8<0b1010, (ops brtarget:$dst),
544 [(V8bricc bb:$dst, ICC_G, ICC)]>;
545 def BLE : BranchV8<0b0010, (ops brtarget:$dst),
547 [(V8bricc bb:$dst, ICC_LE, ICC)]>;
548 def BGE : BranchV8<0b1011, (ops brtarget:$dst),
550 [(V8bricc bb:$dst, ICC_GE, ICC)]>;
551 def BL : BranchV8<0b0011, (ops brtarget:$dst),
553 [(V8bricc bb:$dst, ICC_L, ICC)]>;
554 def BGU : BranchV8<0b1100, (ops brtarget:$dst),
556 [(V8bricc bb:$dst, ICC_GU, ICC)]>;
557 def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
559 [(V8bricc bb:$dst, ICC_LEU, ICC)]>;
560 def BCC : BranchV8<0b1101, (ops brtarget:$dst),
562 [(V8bricc bb:$dst, ICC_CC, ICC)]>;
563 def BCS : BranchV8<0b0101, (ops brtarget:$dst),
565 [(V8bricc bb:$dst, ICC_CS, ICC)]>;
566 def BPOS : BranchV8<0b1110, (ops brtarget:$dst),
568 [(V8bricc bb:$dst, ICC_POS, ICC)]>;
569 def BNEG : BranchV8<0b0110, (ops brtarget:$dst),
571 [(V8bricc bb:$dst, ICC_NEG, ICC)]>;
572 def BVC : BranchV8<0b1111, (ops brtarget:$dst),
574 [(V8bricc bb:$dst, ICC_VC, ICC)]>;
575 def BVS : BranchV8<0b0111, (ops brtarget:$dst),
577 [(V8bricc bb:$dst, ICC_VS, ICC)]>;
581 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
583 // floating-point conditional branch class:
584 class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
585 : F2_2<cc, 0b110, ops, asmstr, pattern> {
587 let isTerminator = 1;
588 let hasDelaySlot = 1;
592 def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
594 [(V8brfcc bb:$dst, FCC_U, FCC)]>;
595 def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
597 [(V8brfcc bb:$dst, FCC_G, FCC)]>;
598 def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
600 [(V8brfcc bb:$dst, FCC_UG, FCC)]>;
601 def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
603 [(V8brfcc bb:$dst, FCC_L, FCC)]>;
604 def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
606 [(V8brfcc bb:$dst, FCC_UL, FCC)]>;
607 def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
609 [(V8brfcc bb:$dst, FCC_LG, FCC)]>;
610 def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
612 [(V8brfcc bb:$dst, FCC_NE, FCC)]>;
613 def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
615 [(V8brfcc bb:$dst, FCC_E, FCC)]>;
616 def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
618 [(V8brfcc bb:$dst, FCC_UE, FCC)]>;
619 def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
621 [(V8brfcc bb:$dst, FCC_GE, FCC)]>;
622 def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
624 [(V8brfcc bb:$dst, FCC_UGE, FCC)]>;
625 def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
627 [(V8brfcc bb:$dst, FCC_LE, FCC)]>;
628 def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
630 [(V8brfcc bb:$dst, FCC_ULE, FCC)]>;
631 def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
633 [(V8brfcc bb:$dst, FCC_O, FCC)]>;
637 // Section B.24 - Call and Link Instruction, p. 125
638 // This is the only Format 1 instruction
639 let Uses = [O0, O1, O2, O3, O4, O5],
640 hasDelaySlot = 1, isCall = 1, noResults = 1,
641 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
642 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
643 def CALL : InstV8<(ops calltarget:$dst),
647 let Inst{29-0} = disp;
651 def JMPLrr : F3_1<2, 0b111000,
654 [(call ADDRrr:$ptr)]>;
655 def JMPLri : F3_2<2, 0b111000,
658 [(call ADDRri:$ptr)]>;
661 // Section B.28 - Read State Register Instructions
662 def RDY : F3_1<2, 0b101000,
666 // Section B.29 - Write State Register Instructions
667 def WRYrr : F3_1<2, 0b110000,
668 (ops IntRegs:$b, IntRegs:$c),
669 "wr $b, $c, %y", []>;
670 def WRYri : F3_2<2, 0b110000,
671 (ops IntRegs:$b, i32imm:$c),
672 "wr $b, $c, %y", []>;
674 // Convert Integer to Floating-point Instructions, p. 141
675 def FITOS : F3_3<2, 0b110100, 0b011000100,
676 (ops FPRegs:$dst, FPRegs:$src),
678 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
679 def FITOD : F3_3<2, 0b110100, 0b011001000,
680 (ops DFPRegs:$dst, FPRegs:$src),
682 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
684 // Convert Floating-point to Integer Instructions, p. 142
685 def FSTOI : F3_3<2, 0b110100, 0b011010001,
686 (ops FPRegs:$dst, FPRegs:$src),
688 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
689 def FDTOI : F3_3<2, 0b110100, 0b011010010,
690 (ops FPRegs:$dst, DFPRegs:$src),
692 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
694 // Convert between Floating-point Formats Instructions, p. 143
695 def FSTOD : F3_3<2, 0b110100, 0b011001001,
696 (ops DFPRegs:$dst, FPRegs:$src),
698 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
699 def FDTOS : F3_3<2, 0b110100, 0b011000110,
700 (ops FPRegs:$dst, DFPRegs:$src),
702 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
704 // Floating-point Move Instructions, p. 144
705 def FMOVS : F3_3<2, 0b110100, 0b000000001,
706 (ops FPRegs:$dst, FPRegs:$src),
707 "fmovs $src, $dst", []>;
708 def FNEGS : F3_3<2, 0b110100, 0b000000101,
709 (ops FPRegs:$dst, FPRegs:$src),
711 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
712 def FABSS : F3_3<2, 0b110100, 0b000001001,
713 (ops FPRegs:$dst, FPRegs:$src),
715 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
718 // Floating-point Square Root Instructions, p.145
719 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
720 (ops FPRegs:$dst, FPRegs:$src),
722 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
723 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
724 (ops DFPRegs:$dst, DFPRegs:$src),
726 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
730 // Floating-point Add and Subtract Instructions, p. 146
731 def FADDS : F3_3<2, 0b110100, 0b001000001,
732 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
733 "fadds $src1, $src2, $dst",
734 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
735 def FADDD : F3_3<2, 0b110100, 0b001000010,
736 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
737 "faddd $src1, $src2, $dst",
738 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
739 def FSUBS : F3_3<2, 0b110100, 0b001000101,
740 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
741 "fsubs $src1, $src2, $dst",
742 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
743 def FSUBD : F3_3<2, 0b110100, 0b001000110,
744 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
745 "fsubd $src1, $src2, $dst",
746 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
748 // Floating-point Multiply and Divide Instructions, p. 147
749 def FMULS : F3_3<2, 0b110100, 0b001001001,
750 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
751 "fmuls $src1, $src2, $dst",
752 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
753 def FMULD : F3_3<2, 0b110100, 0b001001010,
754 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
755 "fmuld $src1, $src2, $dst",
756 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
757 def FSMULD : F3_3<2, 0b110100, 0b001101001,
758 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
759 "fsmuld $src1, $src2, $dst",
760 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
761 (fextend FPRegs:$src2)))]>;
762 def FDIVS : F3_3<2, 0b110100, 0b001001101,
763 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
764 "fdivs $src1, $src2, $dst",
765 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
766 def FDIVD : F3_3<2, 0b110100, 0b001001110,
767 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
768 "fdivd $src1, $src2, $dst",
769 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
771 // Floating-point Compare Instructions, p. 148
772 // Note: the 2nd template arg is different for these guys.
773 // Note 2: the result of a FCMP is not available until the 2nd cycle
774 // after the instr is retired, but there is no interlock. This behavior
775 // is modelled with a forced noop after the instruction.
776 def FCMPS : F3_3<2, 0b110101, 0b001010001,
777 (ops FPRegs:$src1, FPRegs:$src2),
778 "fcmps $src1, $src2\n\tnop",
779 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
780 def FCMPD : F3_3<2, 0b110101, 0b001010010,
781 (ops DFPRegs:$src1, DFPRegs:$src2),
782 "fcmpd $src1, $src2\n\tnop",
783 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
786 //===----------------------------------------------------------------------===//
788 //===----------------------------------------------------------------------===//
790 // V9 Conditional Moves.
791 let Predicates = [HasV9], isTwoAddress = 1 in {
792 // FIXME: Add instruction encodings for the JIT some day.
793 def MOVNE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
794 "movne %icc, $F, $dst",
796 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_NE, ICC))]>;
797 def MOVE : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
798 "move %icc, $F, $dst",
800 (V8selecticc IntRegs:$F, IntRegs:$T, ICC_E, ICC))]>;
803 // Floating-Point Move Instructions, p. 164 of the V9 manual.
804 let Predicates = [HasV9] in {
805 def FMOVD : F3_3<2, 0b110100, 0b000000010,
806 (ops DFPRegs:$dst, DFPRegs:$src),
807 "fmovd $src, $dst", []>;
808 def FNEGD : F3_3<2, 0b110100, 0b000000110,
809 (ops DFPRegs:$dst, DFPRegs:$src),
811 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
812 def FABSD : F3_3<2, 0b110100, 0b000001010,
813 (ops DFPRegs:$dst, DFPRegs:$src),
815 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
818 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
819 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
820 def POPCrr : F3_1<2, 0b101110,
821 (ops IntRegs:$dst, IntRegs:$src),
822 "popc $src, $dst", []>, Requires<[HasV9]>;
823 def : Pat<(ctpop IntRegs:$src),
824 (POPCrr (SLLri IntRegs:$src, 0))>;
826 //===----------------------------------------------------------------------===//
827 // Non-Instruction Patterns
828 //===----------------------------------------------------------------------===//
831 def : Pat<(i32 simm13:$val),
832 (ORri G0, imm:$val)>;
833 // Arbitrary immediates.
834 def : Pat<(i32 imm:$val),
835 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
837 // Global addresses, constant pool entries
838 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
839 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
840 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
841 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
843 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
844 def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
845 (ADDri IntRegs:$r, tglobaladdr:$in)>;
846 def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
847 (ADDri IntRegs:$r, tconstpool:$in)>;
851 def : Pat<(call tglobaladdr:$dst),
852 (CALL tglobaladdr:$dst)>;
853 def : Pat<(call externalsym:$dst),
854 (CALL externalsym:$dst)>;
856 def : Pat<(ret), (RETL)>;
858 // Map integer extload's to zextloads.
859 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
860 def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
861 def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
862 def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
863 def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
864 def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
866 // zextload bool -> zextload byte
867 def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
868 def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
870 // truncstore bool -> truncstore byte.
871 def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
872 (STBrr ADDRrr:$addr, IntRegs:$src)>;
873 def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
874 (STBri ADDRri:$addr, IntRegs:$src)>;