1 //===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // HasV9 - This predicate is true when the target processor supports V9
25 // instructions. Note that the machine may be running in 32-bit mode.
26 def HasV9 : Predicate<"Subtarget.isV9()">;
28 // HasNoV9 - This predicate is true when the target doesn't have V9
29 // instructions. Use of this is just a hack for the isel not having proper
30 // costs for V8 instructions that are more expensive than their V9 ones.
31 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
33 // HasVIS - This is true when the target processor has VIS extensions.
34 def HasVIS : Predicate<"Subtarget.isVIS()">;
36 // UseDeprecatedInsts - This predicate is true when the target processor is a
37 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38 // to use when appropriate. In either of these cases, the instruction selector
39 // will pick deprecated instructions.
40 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
42 //===----------------------------------------------------------------------===//
43 // Instruction Pattern Stuff
44 //===----------------------------------------------------------------------===//
46 def simm11 : PatLeaf<(imm), [{
47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
51 def simm13 : PatLeaf<(imm), [{
52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
56 def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
60 def HI22 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
65 def SETHIimm : PatLeaf<(imm), [{
66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
70 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
71 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
74 def MEMrr : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let MIOperandInfo = (ops IntRegs, IntRegs);
78 def MEMri : Operand<i32> {
79 let PrintMethod = "printMemOperand";
80 let MIOperandInfo = (ops IntRegs, i32imm);
83 // Branch targets have OtherVT type.
84 def brtarget : Operand<OtherVT>;
85 def calltarget : Operand<i32>;
87 // Operand for printing out a condition code.
88 let PrintMethod = "printCCOperand" in
89 def CCOp : Operand<i32>;
92 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
94 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
98 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
100 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
102 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
103 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
104 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
105 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
107 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
108 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
110 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
111 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
113 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
114 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
116 // These are target-independent nodes, but have target-specific formats.
117 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
118 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
121 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
122 [SDNPHasChain, SDNPOutFlag]>;
123 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
127 def call : SDNode<"SPISD::CALL", SDT_SPCall,
128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
130 def retflag : SDNode<"SPISD::RET_FLAG", SDTNone,
131 [SDNPHasChain, SDNPOptInFlag]>;
133 //===----------------------------------------------------------------------===//
134 // SPARC Flag Conditions
135 //===----------------------------------------------------------------------===//
137 // Note that these values must be kept in sync with the CCOp::CondCode enum
139 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
140 def ICC_NE : ICC_VAL< 9>; // Not Equal
141 def ICC_E : ICC_VAL< 1>; // Equal
142 def ICC_G : ICC_VAL<10>; // Greater
143 def ICC_LE : ICC_VAL< 2>; // Less or Equal
144 def ICC_GE : ICC_VAL<11>; // Greater or Equal
145 def ICC_L : ICC_VAL< 3>; // Less
146 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
147 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
148 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
149 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
150 def ICC_POS : ICC_VAL<14>; // Positive
151 def ICC_NEG : ICC_VAL< 6>; // Negative
152 def ICC_VC : ICC_VAL<15>; // Overflow Clear
153 def ICC_VS : ICC_VAL< 7>; // Overflow Set
155 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
156 def FCC_U : FCC_VAL<23>; // Unordered
157 def FCC_G : FCC_VAL<22>; // Greater
158 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
159 def FCC_L : FCC_VAL<20>; // Less
160 def FCC_UL : FCC_VAL<19>; // Unordered or Less
161 def FCC_LG : FCC_VAL<18>; // Less or Greater
162 def FCC_NE : FCC_VAL<17>; // Not Equal
163 def FCC_E : FCC_VAL<25>; // Equal
164 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
165 def FCC_GE : FCC_VAL<25>; // Greater or Equal
166 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
167 def FCC_LE : FCC_VAL<27>; // Less or Equal
168 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
169 def FCC_O : FCC_VAL<29>; // Ordered
171 //===----------------------------------------------------------------------===//
172 // Instruction Class Templates
173 //===----------------------------------------------------------------------===//
175 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
176 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
177 def rr : F3_1<2, Op3Val,
178 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
179 !strconcat(OpcStr, " $b, $c, $dst"),
180 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
181 def ri : F3_2<2, Op3Val,
182 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
183 !strconcat(OpcStr, " $b, $c, $dst"),
184 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
187 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
189 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
190 def rr : F3_1<2, Op3Val,
191 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
192 !strconcat(OpcStr, " $b, $c, $dst"), []>;
193 def ri : F3_2<2, Op3Val,
194 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
195 !strconcat(OpcStr, " $b, $c, $dst"), []>;
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 // Pseudo instructions.
203 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
204 : InstSP<outs, ins, asmstr, pattern>;
206 let Defs = [O6], Uses = [O6] in {
207 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
208 "!ADJCALLSTACKDOWN $amt",
209 [(callseq_start imm:$amt)]>;
210 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
211 "!ADJCALLSTACKUP $amt1",
212 [(callseq_end imm:$amt1, imm:$amt2)]>;
215 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
217 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
218 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
219 "!FpMOVD $src, $dst", []>;
220 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
221 "!FpNEGD $src, $dst",
222 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
223 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
224 "!FpABSD $src, $dst",
225 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
228 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
229 // scheduler into a branch sequence. This has to handle all permutations of
230 // selection between i32/f32/f64 on ICC and FCC.
231 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
232 def SELECT_CC_Int_ICC
233 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
234 "; SELECT_CC_Int_ICC PSEUDO!",
235 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
237 def SELECT_CC_Int_FCC
238 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
239 "; SELECT_CC_Int_FCC PSEUDO!",
240 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
243 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
244 "; SELECT_CC_FP_ICC PSEUDO!",
245 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
248 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
249 "; SELECT_CC_FP_FCC PSEUDO!",
250 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
252 def SELECT_CC_DFP_ICC
253 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
254 "; SELECT_CC_DFP_ICC PSEUDO!",
255 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
257 def SELECT_CC_DFP_FCC
258 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
259 "; SELECT_CC_DFP_FCC PSEUDO!",
260 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
265 // Section A.3 - Synthetic Instructions, p. 85
266 // special cases of JMPL:
267 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
268 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
269 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>;
272 // Section B.1 - Load Integer Instructions, p. 90
273 def LDSBrr : F3_1<3, 0b001001,
274 (outs IntRegs:$dst), (ins MEMrr:$addr),
275 "ldsb [$addr], $dst",
276 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
277 def LDSBri : F3_2<3, 0b001001,
278 (outs IntRegs:$dst), (ins MEMri:$addr),
279 "ldsb [$addr], $dst",
280 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
281 def LDSHrr : F3_1<3, 0b001010,
282 (outs IntRegs:$dst), (ins MEMrr:$addr),
283 "ldsh [$addr], $dst",
284 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
285 def LDSHri : F3_2<3, 0b001010,
286 (outs IntRegs:$dst), (ins MEMri:$addr),
287 "ldsh [$addr], $dst",
288 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
289 def LDUBrr : F3_1<3, 0b000001,
290 (outs IntRegs:$dst), (ins MEMrr:$addr),
291 "ldub [$addr], $dst",
292 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
293 def LDUBri : F3_2<3, 0b000001,
294 (outs IntRegs:$dst), (ins MEMri:$addr),
295 "ldub [$addr], $dst",
296 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
297 def LDUHrr : F3_1<3, 0b000010,
298 (outs IntRegs:$dst), (ins MEMrr:$addr),
299 "lduh [$addr], $dst",
300 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
301 def LDUHri : F3_2<3, 0b000010,
302 (outs IntRegs:$dst), (ins MEMri:$addr),
303 "lduh [$addr], $dst",
304 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
305 def LDrr : F3_1<3, 0b000000,
306 (outs IntRegs:$dst), (ins MEMrr:$addr),
308 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
309 def LDri : F3_2<3, 0b000000,
310 (outs IntRegs:$dst), (ins MEMri:$addr),
312 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
314 // Section B.2 - Load Floating-point Instructions, p. 92
315 def LDFrr : F3_1<3, 0b100000,
316 (outs FPRegs:$dst), (ins MEMrr:$addr),
318 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
319 def LDFri : F3_2<3, 0b100000,
320 (outs FPRegs:$dst), (ins MEMri:$addr),
322 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
323 def LDDFrr : F3_1<3, 0b100011,
324 (outs DFPRegs:$dst), (ins MEMrr:$addr),
326 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
327 def LDDFri : F3_2<3, 0b100011,
328 (outs DFPRegs:$dst), (ins MEMri:$addr),
330 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
332 // Section B.4 - Store Integer Instructions, p. 95
333 def STBrr : F3_1<3, 0b000101,
334 (outs), (ins MEMrr:$addr, IntRegs:$src),
336 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
337 def STBri : F3_2<3, 0b000101,
338 (outs), (ins MEMri:$addr, IntRegs:$src),
340 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
341 def STHrr : F3_1<3, 0b000110,
342 (outs), (ins MEMrr:$addr, IntRegs:$src),
344 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
345 def STHri : F3_2<3, 0b000110,
346 (outs), (ins MEMri:$addr, IntRegs:$src),
348 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
349 def STrr : F3_1<3, 0b000100,
350 (outs), (ins MEMrr:$addr, IntRegs:$src),
352 [(store IntRegs:$src, ADDRrr:$addr)]>;
353 def STri : F3_2<3, 0b000100,
354 (outs), (ins MEMri:$addr, IntRegs:$src),
356 [(store IntRegs:$src, ADDRri:$addr)]>;
358 // Section B.5 - Store Floating-point Instructions, p. 97
359 def STFrr : F3_1<3, 0b100100,
360 (outs), (ins MEMrr:$addr, FPRegs:$src),
362 [(store FPRegs:$src, ADDRrr:$addr)]>;
363 def STFri : F3_2<3, 0b100100,
364 (outs), (ins MEMri:$addr, FPRegs:$src),
366 [(store FPRegs:$src, ADDRri:$addr)]>;
367 def STDFrr : F3_1<3, 0b100111,
368 (outs), (ins MEMrr:$addr, DFPRegs:$src),
370 [(store DFPRegs:$src, ADDRrr:$addr)]>;
371 def STDFri : F3_2<3, 0b100111,
372 (outs), (ins MEMri:$addr, DFPRegs:$src),
374 [(store DFPRegs:$src, ADDRri:$addr)]>;
376 // Section B.9 - SETHI Instruction, p. 104
377 def SETHIi: F2_1<0b100,
378 (outs IntRegs:$dst), (ins i32imm:$src),
380 [(set IntRegs:$dst, SETHIimm:$src)]>;
382 // Section B.10 - NOP Instruction, p. 105
383 // (It's a special case of SETHI)
384 let rd = 0, imm22 = 0 in
385 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
387 // Section B.11 - Logical Instructions, p. 106
388 defm AND : F3_12<"and", 0b000001, and>;
390 def ANDNrr : F3_1<2, 0b000101,
391 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
393 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
394 def ANDNri : F3_2<2, 0b000101,
395 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
396 "andn $b, $c, $dst", []>;
398 defm OR : F3_12<"or", 0b000010, or>;
400 def ORNrr : F3_1<2, 0b000110,
401 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
403 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
404 def ORNri : F3_2<2, 0b000110,
405 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
406 "orn $b, $c, $dst", []>;
407 defm XOR : F3_12<"xor", 0b000011, xor>;
409 def XNORrr : F3_1<2, 0b000111,
410 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
412 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
413 def XNORri : F3_2<2, 0b000111,
414 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
415 "xnor $b, $c, $dst", []>;
417 // Section B.12 - Shift Instructions, p. 107
418 defm SLL : F3_12<"sll", 0b100101, shl>;
419 defm SRL : F3_12<"srl", 0b100110, srl>;
420 defm SRA : F3_12<"sra", 0b100111, sra>;
422 // Section B.13 - Add Instructions, p. 108
423 defm ADD : F3_12<"add", 0b000000, add>;
425 // "LEA" forms of add (patterns to make tblgen happy)
426 def LEA_ADDri : F3_2<2, 0b000000,
427 (outs IntRegs:$dst), (ins MEMri:$addr),
428 "add ${addr:arith}, $dst",
429 [(set IntRegs:$dst, ADDRri:$addr)]>;
431 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
432 defm ADDX : F3_12<"addx", 0b001000, adde>;
434 // Section B.15 - Subtract Instructions, p. 110
435 defm SUB : F3_12 <"sub" , 0b000100, sub>;
436 defm SUBX : F3_12 <"subx" , 0b001100, sube>;
437 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
439 def SUBXCCrr: F3_1<2, 0b011100,
440 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
441 "subxcc $b, $c, $dst", []>;
443 // Section B.18 - Multiply Instructions, p. 113
444 defm UMUL : F3_12np<"umul", 0b001010>;
445 defm SMUL : F3_12 <"smul", 0b001011, mul>;
448 // Section B.19 - Divide Instructions, p. 115
449 defm UDIV : F3_12np<"udiv", 0b001110>;
450 defm SDIV : F3_12np<"sdiv", 0b001111>;
452 // Section B.20 - SAVE and RESTORE, p. 117
453 defm SAVE : F3_12np<"save" , 0b111100>;
454 defm RESTORE : F3_12np<"restore", 0b111101>;
456 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
458 // conditional branch class:
459 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
460 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
462 let isTerminator = 1;
463 let hasDelaySlot = 1;
467 def BA : BranchSP<0b1000, (ins brtarget:$dst),
471 // FIXME: the encoding for the JIT should look at the condition field.
472 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
474 [(SPbricc bb:$dst, imm:$cc)]>;
477 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
479 // floating-point conditional branch class:
480 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
481 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
483 let isTerminator = 1;
484 let hasDelaySlot = 1;
487 // FIXME: the encoding for the JIT should look at the condition field.
488 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
490 [(SPbrfcc bb:$dst, imm:$cc)]>;
493 // Section B.24 - Call and Link Instruction, p. 125
494 // This is the only Format 1 instruction
495 let Uses = [O0, O1, O2, O3, O4, O5],
496 hasDelaySlot = 1, isCall = 1,
497 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
498 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
499 def CALL : InstSP<(outs), (ins calltarget:$dst),
503 let Inst{29-0} = disp;
507 def JMPLrr : F3_1<2, 0b111000,
508 (outs), (ins MEMrr:$ptr),
510 [(call ADDRrr:$ptr)]>;
511 def JMPLri : F3_2<2, 0b111000,
512 (outs), (ins MEMri:$ptr),
514 [(call ADDRri:$ptr)]>;
517 // Section B.28 - Read State Register Instructions
518 def RDY : F3_1<2, 0b101000,
519 (outs IntRegs:$dst), (ins),
522 // Section B.29 - Write State Register Instructions
523 def WRYrr : F3_1<2, 0b110000,
524 (outs), (ins IntRegs:$b, IntRegs:$c),
525 "wr $b, $c, %y", []>;
526 def WRYri : F3_2<2, 0b110000,
527 (outs), (ins IntRegs:$b, i32imm:$c),
528 "wr $b, $c, %y", []>;
530 // Convert Integer to Floating-point Instructions, p. 141
531 def FITOS : F3_3<2, 0b110100, 0b011000100,
532 (outs FPRegs:$dst), (ins FPRegs:$src),
534 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
535 def FITOD : F3_3<2, 0b110100, 0b011001000,
536 (outs DFPRegs:$dst), (ins FPRegs:$src),
538 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
540 // Convert Floating-point to Integer Instructions, p. 142
541 def FSTOI : F3_3<2, 0b110100, 0b011010001,
542 (outs FPRegs:$dst), (ins FPRegs:$src),
544 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
545 def FDTOI : F3_3<2, 0b110100, 0b011010010,
546 (outs FPRegs:$dst), (ins DFPRegs:$src),
548 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
550 // Convert between Floating-point Formats Instructions, p. 143
551 def FSTOD : F3_3<2, 0b110100, 0b011001001,
552 (outs DFPRegs:$dst), (ins FPRegs:$src),
554 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
555 def FDTOS : F3_3<2, 0b110100, 0b011000110,
556 (outs FPRegs:$dst), (ins DFPRegs:$src),
558 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
560 // Floating-point Move Instructions, p. 144
561 def FMOVS : F3_3<2, 0b110100, 0b000000001,
562 (outs FPRegs:$dst), (ins FPRegs:$src),
563 "fmovs $src, $dst", []>;
564 def FNEGS : F3_3<2, 0b110100, 0b000000101,
565 (outs FPRegs:$dst), (ins FPRegs:$src),
567 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
568 def FABSS : F3_3<2, 0b110100, 0b000001001,
569 (outs FPRegs:$dst), (ins FPRegs:$src),
571 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
574 // Floating-point Square Root Instructions, p.145
575 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
576 (outs FPRegs:$dst), (ins FPRegs:$src),
578 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
579 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
580 (outs DFPRegs:$dst), (ins DFPRegs:$src),
582 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
586 // Floating-point Add and Subtract Instructions, p. 146
587 def FADDS : F3_3<2, 0b110100, 0b001000001,
588 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
589 "fadds $src1, $src2, $dst",
590 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
591 def FADDD : F3_3<2, 0b110100, 0b001000010,
592 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
593 "faddd $src1, $src2, $dst",
594 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
595 def FSUBS : F3_3<2, 0b110100, 0b001000101,
596 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
597 "fsubs $src1, $src2, $dst",
598 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
599 def FSUBD : F3_3<2, 0b110100, 0b001000110,
600 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
601 "fsubd $src1, $src2, $dst",
602 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
604 // Floating-point Multiply and Divide Instructions, p. 147
605 def FMULS : F3_3<2, 0b110100, 0b001001001,
606 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
607 "fmuls $src1, $src2, $dst",
608 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
609 def FMULD : F3_3<2, 0b110100, 0b001001010,
610 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
611 "fmuld $src1, $src2, $dst",
612 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
613 def FSMULD : F3_3<2, 0b110100, 0b001101001,
614 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
615 "fsmuld $src1, $src2, $dst",
616 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
617 (fextend FPRegs:$src2)))]>;
618 def FDIVS : F3_3<2, 0b110100, 0b001001101,
619 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
620 "fdivs $src1, $src2, $dst",
621 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
622 def FDIVD : F3_3<2, 0b110100, 0b001001110,
623 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
624 "fdivd $src1, $src2, $dst",
625 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
627 // Floating-point Compare Instructions, p. 148
628 // Note: the 2nd template arg is different for these guys.
629 // Note 2: the result of a FCMP is not available until the 2nd cycle
630 // after the instr is retired, but there is no interlock. This behavior
631 // is modelled with a forced noop after the instruction.
632 def FCMPS : F3_3<2, 0b110101, 0b001010001,
633 (outs), (ins FPRegs:$src1, FPRegs:$src2),
634 "fcmps $src1, $src2\n\tnop",
635 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
636 def FCMPD : F3_3<2, 0b110101, 0b001010010,
637 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
638 "fcmpd $src1, $src2\n\tnop",
639 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
646 // V9 Conditional Moves.
647 let Predicates = [HasV9], isTwoAddress = 1 in {
648 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
649 // FIXME: Add instruction encodings for the JIT some day.
651 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
652 "mov$cc %icc, $F, $dst",
654 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
656 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
657 "mov$cc %icc, $F, $dst",
659 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
662 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
663 "mov$cc %fcc0, $F, $dst",
665 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
667 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
668 "mov$cc %fcc0, $F, $dst",
670 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
673 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
674 "fmovs$cc %icc, $F, $dst",
676 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
678 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
679 "fmovd$cc %icc, $F, $dst",
681 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
683 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
684 "fmovs$cc %fcc0, $F, $dst",
686 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
688 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
689 "fmovd$cc %fcc0, $F, $dst",
691 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
695 // Floating-Point Move Instructions, p. 164 of the V9 manual.
696 let Predicates = [HasV9] in {
697 def FMOVD : F3_3<2, 0b110100, 0b000000010,
698 (outs DFPRegs:$dst), (ins DFPRegs:$src),
699 "fmovd $src, $dst", []>;
700 def FNEGD : F3_3<2, 0b110100, 0b000000110,
701 (outs DFPRegs:$dst), (ins DFPRegs:$src),
703 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
704 def FABSD : F3_3<2, 0b110100, 0b000001010,
705 (outs DFPRegs:$dst), (ins DFPRegs:$src),
707 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
710 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
711 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
712 def POPCrr : F3_1<2, 0b101110,
713 (outs IntRegs:$dst), (ins IntRegs:$src),
714 "popc $src, $dst", []>, Requires<[HasV9]>;
715 def : Pat<(ctpop IntRegs:$src),
716 (POPCrr (SLLri IntRegs:$src, 0))>;
718 //===----------------------------------------------------------------------===//
719 // Non-Instruction Patterns
720 //===----------------------------------------------------------------------===//
723 def : Pat<(i32 simm13:$val),
724 (ORri G0, imm:$val)>;
725 // Arbitrary immediates.
726 def : Pat<(i32 imm:$val),
727 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
730 def : Pat<(subc IntRegs:$b, IntRegs:$c),
731 (SUBCCrr IntRegs:$b, IntRegs:$c)>;
732 def : Pat<(subc IntRegs:$b, simm13:$val),
733 (SUBCCri IntRegs:$b, imm:$val)>;
735 // Global addresses, constant pool entries
736 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
737 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
738 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
739 def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
741 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
742 def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
743 (ADDri IntRegs:$r, tglobaladdr:$in)>;
744 def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
745 (ADDri IntRegs:$r, tconstpool:$in)>;
748 def : Pat<(call tglobaladdr:$dst),
749 (CALL tglobaladdr:$dst)>;
750 def : Pat<(call texternalsym:$dst),
751 (CALL texternalsym:$dst)>;
753 def : Pat<(ret), (RETL)>;
755 // Map integer extload's to zextloads.
756 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
757 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
758 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
759 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
760 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
761 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
763 // zextload bool -> zextload byte
764 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
765 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;