1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // UseDeprecatedInsts - This predicate is true when the target processor is a
43 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
44 // to use when appropriate. In either of these cases, the instruction selector
45 // will pick deprecated instructions.
46 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
48 //===----------------------------------------------------------------------===//
49 // Instruction Pattern Stuff
50 //===----------------------------------------------------------------------===//
52 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
54 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
56 def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
61 def HI22 : SDNodeXForm<imm, [{
62 // Transformation function: shift the immediate value down into the low bits.
63 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
66 def SETHIimm : PatLeaf<(imm), [{
67 return isShiftedUInt<22, 10>(N->getZExtValue());
71 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
72 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
75 def MEMrr : Operand<iPTR> {
76 let PrintMethod = "printMemOperand";
77 let MIOperandInfo = (ops ptr_rc, ptr_rc);
79 def MEMri : Operand<iPTR> {
80 let PrintMethod = "printMemOperand";
81 let MIOperandInfo = (ops ptr_rc, i32imm);
84 // Branch targets have OtherVT type.
85 def brtarget : Operand<OtherVT>;
86 def calltarget : Operand<i32>;
88 // Operand for printing out a condition code.
89 let PrintMethod = "printCCOperand" in
90 def CCOp : Operand<i32>;
93 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
95 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
97 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
99 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
101 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
103 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
105 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
106 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
107 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
108 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
109 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
111 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
112 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
114 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
115 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
117 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
118 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
119 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
121 // These are target-independent nodes, but have target-specific formats.
122 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
123 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
126 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
127 [SDNPHasChain, SDNPOutGlue]>;
128 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
129 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
131 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
132 def call : SDNode<"SPISD::CALL", SDT_SPCall,
133 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
136 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
137 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
138 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
140 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
141 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
143 def getPCX : Operand<i32> {
144 let PrintMethod = "printGetPCX";
147 //===----------------------------------------------------------------------===//
148 // SPARC Flag Conditions
149 //===----------------------------------------------------------------------===//
151 // Note that these values must be kept in sync with the CCOp::CondCode enum
153 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
154 def ICC_NE : ICC_VAL< 9>; // Not Equal
155 def ICC_E : ICC_VAL< 1>; // Equal
156 def ICC_G : ICC_VAL<10>; // Greater
157 def ICC_LE : ICC_VAL< 2>; // Less or Equal
158 def ICC_GE : ICC_VAL<11>; // Greater or Equal
159 def ICC_L : ICC_VAL< 3>; // Less
160 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
161 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
162 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
163 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
164 def ICC_POS : ICC_VAL<14>; // Positive
165 def ICC_NEG : ICC_VAL< 6>; // Negative
166 def ICC_VC : ICC_VAL<15>; // Overflow Clear
167 def ICC_VS : ICC_VAL< 7>; // Overflow Set
169 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
170 def FCC_U : FCC_VAL<23>; // Unordered
171 def FCC_G : FCC_VAL<22>; // Greater
172 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
173 def FCC_L : FCC_VAL<20>; // Less
174 def FCC_UL : FCC_VAL<19>; // Unordered or Less
175 def FCC_LG : FCC_VAL<18>; // Less or Greater
176 def FCC_NE : FCC_VAL<17>; // Not Equal
177 def FCC_E : FCC_VAL<25>; // Equal
178 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
179 def FCC_GE : FCC_VAL<25>; // Greater or Equal
180 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
181 def FCC_LE : FCC_VAL<27>; // Less or Equal
182 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
183 def FCC_O : FCC_VAL<29>; // Ordered
185 //===----------------------------------------------------------------------===//
186 // Instruction Class Templates
187 //===----------------------------------------------------------------------===//
189 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
190 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
191 def rr : F3_1<2, Op3Val,
192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
193 !strconcat(OpcStr, " $b, $c, $dst"),
194 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
195 def ri : F3_2<2, Op3Val,
196 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
197 !strconcat(OpcStr, " $b, $c, $dst"),
198 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
201 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
203 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
204 def rr : F3_1<2, Op3Val,
205 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
206 !strconcat(OpcStr, " $b, $c, $dst"), []>;
207 def ri : F3_2<2, Op3Val,
208 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
209 !strconcat(OpcStr, " $b, $c, $dst"), []>;
212 //===----------------------------------------------------------------------===//
214 //===----------------------------------------------------------------------===//
216 // Pseudo instructions.
217 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
218 : InstSP<outs, ins, asmstr, pattern>;
222 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
225 let Defs = [O6], Uses = [O6] in {
226 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
227 "!ADJCALLSTACKDOWN $amt",
228 [(callseq_start timm:$amt)]>;
229 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
230 "!ADJCALLSTACKUP $amt1",
231 [(callseq_end timm:$amt1, timm:$amt2)]>;
234 let hasSideEffects = 1, mayStore = 1 in {
235 let rd = 0, rs1 = 0, rs2 = 0 in
236 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
238 [(flushw)]>, Requires<[HasV9]>;
239 let rd = 0, rs1 = 1, simm13 = 3 in
240 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
245 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
248 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
250 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
251 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
252 "!FpMOVD $src, $dst", []>;
253 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
254 "!FpNEGD $src, $dst",
255 [(set f64:$dst, (fneg f64:$src))]>;
256 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
257 "!FpABSD $src, $dst",
258 [(set f64:$dst, (fabs f64:$src))]>;
261 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
262 // instruction selection into a branch sequence. This has to handle all
263 // permutations of selection between i32/f32/f64 on ICC and FCC.
264 // Expanded after instruction selection.
265 let Uses = [ICC], usesCustomInserter = 1 in {
266 def SELECT_CC_Int_ICC
267 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
268 "; SELECT_CC_Int_ICC PSEUDO!",
269 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
271 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
272 "; SELECT_CC_FP_ICC PSEUDO!",
273 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
275 def SELECT_CC_DFP_ICC
276 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
277 "; SELECT_CC_DFP_ICC PSEUDO!",
278 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
281 let usesCustomInserter = 1, Uses = [FCC] in {
283 def SELECT_CC_Int_FCC
284 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
285 "; SELECT_CC_Int_FCC PSEUDO!",
286 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
289 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
290 "; SELECT_CC_FP_FCC PSEUDO!",
291 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
292 def SELECT_CC_DFP_FCC
293 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
294 "; SELECT_CC_DFP_FCC PSEUDO!",
295 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
299 // Section A.3 - Synthetic Instructions, p. 85
300 // special cases of JMPL:
301 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
302 let rd = O7.Num, rs1 = G0.Num in
303 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
304 "jmp %o7+$val", [(retflag simm13:$val)]>;
306 let rd = I7.Num, rs1 = G0.Num in
307 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
311 // Section B.1 - Load Integer Instructions, p. 90
312 def LDSBrr : F3_1<3, 0b001001,
313 (outs IntRegs:$dst), (ins MEMrr:$addr),
314 "ldsb [$addr], $dst",
315 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
316 def LDSBri : F3_2<3, 0b001001,
317 (outs IntRegs:$dst), (ins MEMri:$addr),
318 "ldsb [$addr], $dst",
319 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
320 def LDSHrr : F3_1<3, 0b001010,
321 (outs IntRegs:$dst), (ins MEMrr:$addr),
322 "ldsh [$addr], $dst",
323 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
324 def LDSHri : F3_2<3, 0b001010,
325 (outs IntRegs:$dst), (ins MEMri:$addr),
326 "ldsh [$addr], $dst",
327 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
328 def LDUBrr : F3_1<3, 0b000001,
329 (outs IntRegs:$dst), (ins MEMrr:$addr),
330 "ldub [$addr], $dst",
331 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
332 def LDUBri : F3_2<3, 0b000001,
333 (outs IntRegs:$dst), (ins MEMri:$addr),
334 "ldub [$addr], $dst",
335 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
336 def LDUHrr : F3_1<3, 0b000010,
337 (outs IntRegs:$dst), (ins MEMrr:$addr),
338 "lduh [$addr], $dst",
339 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
340 def LDUHri : F3_2<3, 0b000010,
341 (outs IntRegs:$dst), (ins MEMri:$addr),
342 "lduh [$addr], $dst",
343 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
344 def LDrr : F3_1<3, 0b000000,
345 (outs IntRegs:$dst), (ins MEMrr:$addr),
347 [(set i32:$dst, (load ADDRrr:$addr))]>;
348 def LDri : F3_2<3, 0b000000,
349 (outs IntRegs:$dst), (ins MEMri:$addr),
351 [(set i32:$dst, (load ADDRri:$addr))]>;
353 // Section B.2 - Load Floating-point Instructions, p. 92
354 def LDFrr : F3_1<3, 0b100000,
355 (outs FPRegs:$dst), (ins MEMrr:$addr),
357 [(set f32:$dst, (load ADDRrr:$addr))]>;
358 def LDFri : F3_2<3, 0b100000,
359 (outs FPRegs:$dst), (ins MEMri:$addr),
361 [(set f32:$dst, (load ADDRri:$addr))]>;
362 def LDDFrr : F3_1<3, 0b100011,
363 (outs DFPRegs:$dst), (ins MEMrr:$addr),
365 [(set f64:$dst, (load ADDRrr:$addr))]>;
366 def LDDFri : F3_2<3, 0b100011,
367 (outs DFPRegs:$dst), (ins MEMri:$addr),
369 [(set f64:$dst, (load ADDRri:$addr))]>;
371 // Section B.4 - Store Integer Instructions, p. 95
372 def STBrr : F3_1<3, 0b000101,
373 (outs), (ins MEMrr:$addr, IntRegs:$src),
375 [(truncstorei8 i32:$src, ADDRrr:$addr)]>;
376 def STBri : F3_2<3, 0b000101,
377 (outs), (ins MEMri:$addr, IntRegs:$src),
379 [(truncstorei8 i32:$src, ADDRri:$addr)]>;
380 def STHrr : F3_1<3, 0b000110,
381 (outs), (ins MEMrr:$addr, IntRegs:$src),
383 [(truncstorei16 i32:$src, ADDRrr:$addr)]>;
384 def STHri : F3_2<3, 0b000110,
385 (outs), (ins MEMri:$addr, IntRegs:$src),
387 [(truncstorei16 i32:$src, ADDRri:$addr)]>;
388 def STrr : F3_1<3, 0b000100,
389 (outs), (ins MEMrr:$addr, IntRegs:$src),
391 [(store i32:$src, ADDRrr:$addr)]>;
392 def STri : F3_2<3, 0b000100,
393 (outs), (ins MEMri:$addr, IntRegs:$src),
395 [(store i32:$src, ADDRri:$addr)]>;
397 // Section B.5 - Store Floating-point Instructions, p. 97
398 def STFrr : F3_1<3, 0b100100,
399 (outs), (ins MEMrr:$addr, FPRegs:$src),
401 [(store f32:$src, ADDRrr:$addr)]>;
402 def STFri : F3_2<3, 0b100100,
403 (outs), (ins MEMri:$addr, FPRegs:$src),
405 [(store f32:$src, ADDRri:$addr)]>;
406 def STDFrr : F3_1<3, 0b100111,
407 (outs), (ins MEMrr:$addr, DFPRegs:$src),
409 [(store f64:$src, ADDRrr:$addr)]>;
410 def STDFri : F3_2<3, 0b100111,
411 (outs), (ins MEMri:$addr, DFPRegs:$src),
413 [(store f64:$src, ADDRri:$addr)]>;
415 // Section B.9 - SETHI Instruction, p. 104
416 def SETHIi: F2_1<0b100,
417 (outs IntRegs:$dst), (ins i32imm:$src),
419 [(set i32:$dst, SETHIimm:$src)]>;
421 // Section B.10 - NOP Instruction, p. 105
422 // (It's a special case of SETHI)
423 let rd = 0, imm22 = 0 in
424 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
426 // Section B.11 - Logical Instructions, p. 106
427 defm AND : F3_12<"and", 0b000001, and>;
429 def ANDNrr : F3_1<2, 0b000101,
430 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
432 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
433 def ANDNri : F3_2<2, 0b000101,
434 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
435 "andn $b, $c, $dst", []>;
437 defm OR : F3_12<"or", 0b000010, or>;
439 def ORNrr : F3_1<2, 0b000110,
440 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
442 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
443 def ORNri : F3_2<2, 0b000110,
444 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
445 "orn $b, $c, $dst", []>;
446 defm XOR : F3_12<"xor", 0b000011, xor>;
448 def XNORrr : F3_1<2, 0b000111,
449 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
451 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
452 def XNORri : F3_2<2, 0b000111,
453 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
454 "xnor $b, $c, $dst", []>;
456 // Section B.12 - Shift Instructions, p. 107
457 defm SLL : F3_12<"sll", 0b100101, shl>;
458 defm SRL : F3_12<"srl", 0b100110, srl>;
459 defm SRA : F3_12<"sra", 0b100111, sra>;
461 // Section B.13 - Add Instructions, p. 108
462 defm ADD : F3_12<"add", 0b000000, add>;
464 // "LEA" forms of add (patterns to make tblgen happy)
465 def LEA_ADDri : F3_2<2, 0b000000,
466 (outs IntRegs:$dst), (ins MEMri:$addr),
467 "add ${addr:arith}, $dst",
468 [(set iPTR:$dst, ADDRri:$addr)]>;
471 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
474 defm ADDX : F3_12<"addx", 0b001000, adde>;
476 // Section B.15 - Subtract Instructions, p. 110
477 defm SUB : F3_12 <"sub" , 0b000100, sub>;
479 defm SUBX : F3_12 <"subx" , 0b001100, sube>;
481 let Defs = [ICC] in {
482 defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
484 def CMPrr : F3_1<2, 0b010100,
485 (outs), (ins IntRegs:$b, IntRegs:$c),
487 [(SPcmpicc i32:$b, i32:$c)]>;
488 def CMPri : F3_1<2, 0b010100,
489 (outs), (ins IntRegs:$b, i32imm:$c),
491 [(SPcmpicc i32:$b, (i32 simm13:$c))]>;
494 let Uses = [ICC], Defs = [ICC] in
495 def SUBXCCrr: F3_1<2, 0b011100,
496 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
497 "subxcc $b, $c, $dst", []>;
500 // Section B.18 - Multiply Instructions, p. 113
502 defm UMUL : F3_12np<"umul", 0b001010>;
503 defm SMUL : F3_12 <"smul", 0b001011, mul>;
506 // Section B.19 - Divide Instructions, p. 115
508 defm UDIV : F3_12np<"udiv", 0b001110>;
509 defm SDIV : F3_12np<"sdiv", 0b001111>;
512 // Section B.20 - SAVE and RESTORE, p. 117
513 defm SAVE : F3_12np<"save" , 0b111100>;
514 defm RESTORE : F3_12np<"restore", 0b111101>;
516 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
518 // conditional branch class:
519 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
520 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
522 let isTerminator = 1;
523 let hasDelaySlot = 1;
527 def BA : BranchSP<0b1000, (ins brtarget:$dst),
531 // Indirect branch instructions.
532 let isTerminator = 1, isBarrier = 1,
533 hasDelaySlot = 1, isBranch =1,
534 isIndirectBranch = 1 in {
535 def BINDrr : F3_1<2, 0b111000,
536 (outs), (ins MEMrr:$ptr),
538 [(brind ADDRrr:$ptr)]>;
539 def BINDri : F3_2<2, 0b111000,
540 (outs), (ins MEMri:$ptr),
542 [(brind ADDRri:$ptr)]>;
545 // FIXME: the encoding for the JIT should look at the condition field.
547 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
549 [(SPbricc bb:$dst, imm:$cc)]>;
552 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
554 // floating-point conditional branch class:
555 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
556 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
558 let isTerminator = 1;
559 let hasDelaySlot = 1;
562 // FIXME: the encoding for the JIT should look at the condition field.
564 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
566 [(SPbrfcc bb:$dst, imm:$cc)]>;
569 // Section B.24 - Call and Link Instruction, p. 125
570 // This is the only Format 1 instruction
572 hasDelaySlot = 1, isCall = 1,
573 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
574 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
576 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
580 let Inst{29-0} = disp;
584 def JMPLrr : F3_1<2, 0b111000,
585 (outs), (ins MEMrr:$ptr, variable_ops),
587 [(call ADDRrr:$ptr)]>;
588 def JMPLri : F3_2<2, 0b111000,
589 (outs), (ins MEMri:$ptr, variable_ops),
591 [(call ADDRri:$ptr)]>;
594 // Section B.28 - Read State Register Instructions
596 def RDY : F3_1<2, 0b101000,
597 (outs IntRegs:$dst), (ins),
600 // Section B.29 - Write State Register Instructions
602 def WRYrr : F3_1<2, 0b110000,
603 (outs), (ins IntRegs:$b, IntRegs:$c),
604 "wr $b, $c, %y", []>;
605 def WRYri : F3_2<2, 0b110000,
606 (outs), (ins IntRegs:$b, i32imm:$c),
607 "wr $b, $c, %y", []>;
609 // Convert Integer to Floating-point Instructions, p. 141
610 def FITOS : F3_3<2, 0b110100, 0b011000100,
611 (outs FPRegs:$dst), (ins FPRegs:$src),
613 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
614 def FITOD : F3_3<2, 0b110100, 0b011001000,
615 (outs DFPRegs:$dst), (ins FPRegs:$src),
617 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
619 // Convert Floating-point to Integer Instructions, p. 142
620 def FSTOI : F3_3<2, 0b110100, 0b011010001,
621 (outs FPRegs:$dst), (ins FPRegs:$src),
623 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
624 def FDTOI : F3_3<2, 0b110100, 0b011010010,
625 (outs FPRegs:$dst), (ins DFPRegs:$src),
627 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
629 // Convert between Floating-point Formats Instructions, p. 143
630 def FSTOD : F3_3<2, 0b110100, 0b011001001,
631 (outs DFPRegs:$dst), (ins FPRegs:$src),
633 [(set f64:$dst, (fextend f32:$src))]>;
634 def FDTOS : F3_3<2, 0b110100, 0b011000110,
635 (outs FPRegs:$dst), (ins DFPRegs:$src),
637 [(set f32:$dst, (fround f64:$src))]>;
639 // Floating-point Move Instructions, p. 144
640 def FMOVS : F3_3<2, 0b110100, 0b000000001,
641 (outs FPRegs:$dst), (ins FPRegs:$src),
642 "fmovs $src, $dst", []>;
643 def FNEGS : F3_3<2, 0b110100, 0b000000101,
644 (outs FPRegs:$dst), (ins FPRegs:$src),
646 [(set f32:$dst, (fneg f32:$src))]>;
647 def FABSS : F3_3<2, 0b110100, 0b000001001,
648 (outs FPRegs:$dst), (ins FPRegs:$src),
650 [(set f32:$dst, (fabs f32:$src))]>;
653 // Floating-point Square Root Instructions, p.145
654 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
655 (outs FPRegs:$dst), (ins FPRegs:$src),
657 [(set f32:$dst, (fsqrt f32:$src))]>;
658 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
659 (outs DFPRegs:$dst), (ins DFPRegs:$src),
661 [(set f64:$dst, (fsqrt f64:$src))]>;
665 // Floating-point Add and Subtract Instructions, p. 146
666 def FADDS : F3_3<2, 0b110100, 0b001000001,
667 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
668 "fadds $src1, $src2, $dst",
669 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
670 def FADDD : F3_3<2, 0b110100, 0b001000010,
671 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
672 "faddd $src1, $src2, $dst",
673 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
674 def FSUBS : F3_3<2, 0b110100, 0b001000101,
675 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
676 "fsubs $src1, $src2, $dst",
677 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
678 def FSUBD : F3_3<2, 0b110100, 0b001000110,
679 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
680 "fsubd $src1, $src2, $dst",
681 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
683 // Floating-point Multiply and Divide Instructions, p. 147
684 def FMULS : F3_3<2, 0b110100, 0b001001001,
685 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
686 "fmuls $src1, $src2, $dst",
687 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
688 def FMULD : F3_3<2, 0b110100, 0b001001010,
689 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
690 "fmuld $src1, $src2, $dst",
691 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
692 def FSMULD : F3_3<2, 0b110100, 0b001101001,
693 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
694 "fsmuld $src1, $src2, $dst",
695 [(set f64:$dst, (fmul (fextend f32:$src1),
696 (fextend f32:$src2)))]>;
697 def FDIVS : F3_3<2, 0b110100, 0b001001101,
698 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
699 "fdivs $src1, $src2, $dst",
700 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
701 def FDIVD : F3_3<2, 0b110100, 0b001001110,
702 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
703 "fdivd $src1, $src2, $dst",
704 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
706 // Floating-point Compare Instructions, p. 148
707 // Note: the 2nd template arg is different for these guys.
708 // Note 2: the result of a FCMP is not available until the 2nd cycle
709 // after the instr is retired, but there is no interlock. This behavior
710 // is modelled with a forced noop after the instruction.
711 let Defs = [FCC] in {
712 def FCMPS : F3_3<2, 0b110101, 0b001010001,
713 (outs), (ins FPRegs:$src1, FPRegs:$src2),
714 "fcmps $src1, $src2\n\tnop",
715 [(SPcmpfcc f32:$src1, f32:$src2)]>;
716 def FCMPD : F3_3<2, 0b110101, 0b001010010,
717 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
718 "fcmpd $src1, $src2\n\tnop",
719 [(SPcmpfcc f64:$src1, f64:$src2)]>;
722 //===----------------------------------------------------------------------===//
724 //===----------------------------------------------------------------------===//
726 // V9 Conditional Moves.
727 let Predicates = [HasV9], Constraints = "$f = $rd" in {
728 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
729 // FIXME: Add instruction encodings for the JIT some day.
730 let Uses = [ICC] in {
732 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
733 "mov$cc %icc, $rs2, $rd",
734 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>;
736 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
737 "mov$cc %icc, $i, $rd",
738 [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>;
741 let Uses = [FCC] in {
743 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
744 "mov$cc %fcc0, $rs2, $rd",
745 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>;
747 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
748 "mov$cc %fcc0, $i, $rd",
749 [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>;
752 let Uses = [ICC] in {
754 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
755 "fmovs$cc %icc, $rs2, $rd",
756 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>;
758 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
759 "fmovd$cc %icc, $rs2, $rd",
760 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>;
763 let Uses = [FCC] in {
765 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
766 "fmovs$cc %fcc0, $rs2, $rd",
767 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>;
769 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
770 "fmovd$cc %fcc0, $rs2, $rd",
771 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>;
776 // Floating-Point Move Instructions, p. 164 of the V9 manual.
777 let Predicates = [HasV9] in {
778 def FMOVD : F3_3<2, 0b110100, 0b000000010,
779 (outs DFPRegs:$dst), (ins DFPRegs:$src),
780 "fmovd $src, $dst", []>;
781 def FNEGD : F3_3<2, 0b110100, 0b000000110,
782 (outs DFPRegs:$dst), (ins DFPRegs:$src),
784 [(set f64:$dst, (fneg f64:$src))]>;
785 def FABSD : F3_3<2, 0b110100, 0b000001010,
786 (outs DFPRegs:$dst), (ins DFPRegs:$src),
788 [(set f64:$dst, (fabs f64:$src))]>;
791 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
792 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
793 def POPCrr : F3_1<2, 0b101110,
794 (outs IntRegs:$dst), (ins IntRegs:$src),
795 "popc $src, $dst", []>, Requires<[HasV9]>;
796 def : Pat<(ctpop i32:$src),
797 (POPCrr (SLLri $src, 0))>;
799 //===----------------------------------------------------------------------===//
800 // Non-Instruction Patterns
801 //===----------------------------------------------------------------------===//
804 def : Pat<(i32 simm13:$val),
805 (ORri (i32 G0), imm:$val)>;
806 // Arbitrary immediates.
807 def : Pat<(i32 imm:$val),
808 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
811 // Global addresses, constant pool entries
812 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
813 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
814 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
815 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
818 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
819 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
821 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
822 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
823 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
824 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
825 (ADDri $r, tblockaddress:$in)>;
828 def : Pat<(call tglobaladdr:$dst),
829 (CALL tglobaladdr:$dst)>;
830 def : Pat<(call texternalsym:$dst),
831 (CALL texternalsym:$dst)>;
833 // Map integer extload's to zextloads.
834 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
835 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
836 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
837 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
838 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
839 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
841 // zextload bool -> zextload byte
842 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
843 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
845 // store 0, addr -> store %g0, addr
846 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
847 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
849 include "SparcInstr64Bit.td"