1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcV8InstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Instruction Pattern Stuff
22 //===----------------------------------------------------------------------===//
24 def simm13 : PatLeaf<(imm), [{
25 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
26 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
29 def LO10 : SDNodeXForm<imm, [{
30 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
33 def HI22 : SDNodeXForm<imm, [{
34 // Transformation function: shift the immediate value down into the low bits.
35 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
38 def SETHIimm : PatLeaf<(imm), [{
39 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
43 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
44 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
47 def MEMrr : Operand<i32> {
48 let PrintMethod = "printMemOperand";
49 let NumMIOperands = 2;
50 let MIOperandInfo = (ops IntRegs, IntRegs);
52 def MEMri : Operand<i32> {
53 let PrintMethod = "printMemOperand";
54 let NumMIOperands = 2;
55 let MIOperandInfo = (ops IntRegs, i32imm);
58 // Branch targets have OtherVT type.
59 def brtarget : Operand<OtherVT>;
60 def calltarget : Operand<i32>;
63 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
65 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
66 SDTCisVT<2, FlagVT>]>;
68 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
69 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
71 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
73 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
75 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
76 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
77 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
78 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
80 def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
81 def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
83 def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
84 def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
86 def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
87 def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
89 // These are target-independent nodes, but have target-specific formats.
90 def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
91 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
92 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
94 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
95 def call : SDNode<"V8ISD::CALL", SDT_V8Call,
96 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
98 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
99 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
100 [SDNPHasChain, SDNPOptInFlag]>;
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
106 // Pseudo instructions.
107 class Pseudo<dag ops, string asmstr, list<dag> pattern>
108 : InstV8<ops, asmstr, pattern>;
110 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
111 "!ADJCALLSTACKDOWN $amt",
112 [(callseq_start imm:$amt)]>;
113 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
114 "!ADJCALLSTACKUP $amt",
115 [(callseq_end imm:$amt)]>;
116 def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
117 "!IMPLICIT_DEF $dst",
118 [(set IntRegs:$dst, (undef))]>;
119 def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
120 [(set FPRegs:$dst, (undef))]>;
121 def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
122 [(set DFPRegs:$dst, (undef))]>;
124 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
126 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
127 "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move
128 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
129 "!FpNEGD $src, $dst",
130 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
131 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
132 "!FpABSD $src, $dst",
133 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
135 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
136 // scheduler into a branch sequence. This has to handle all permutations of
137 // selection between i32/f32/f64 on ICC and FCC.
138 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
139 def SELECT_CC_Int_ICC
140 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
141 "; SELECT_CC_Int_ICC PSEUDO!",
142 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
144 def SELECT_CC_Int_FCC
145 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
146 "; SELECT_CC_Int_FCC PSEUDO!",
147 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
150 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
151 "; SELECT_CC_FP_ICC PSEUDO!",
152 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
155 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
156 "; SELECT_CC_FP_FCC PSEUDO!",
157 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
159 def SELECT_CC_DFP_ICC
160 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
161 "; SELECT_CC_DFP_ICC PSEUDO!",
162 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
164 def SELECT_CC_DFP_FCC
165 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
166 "; SELECT_CC_DFP_FCC PSEUDO!",
167 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
171 // Section A.3 - Synthetic Instructions, p. 85
172 // special cases of JMPL:
173 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
174 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
175 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
178 // Section B.1 - Load Integer Instructions, p. 90
179 def LDSBrr : F3_1<3, 0b001001,
180 (ops IntRegs:$dst, MEMrr:$addr),
181 "ldsb [$addr], $dst",
182 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
183 def LDSBri : F3_2<3, 0b001001,
184 (ops IntRegs:$dst, MEMri:$addr),
185 "ldsb [$addr], $dst",
186 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
187 def LDSHrr : F3_1<3, 0b001010,
188 (ops IntRegs:$dst, MEMrr:$addr),
189 "ldsh [$addr], $dst",
190 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
191 def LDSHri : F3_2<3, 0b001010,
192 (ops IntRegs:$dst, MEMri:$addr),
193 "ldsh [$addr], $dst",
194 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
195 def LDUBrr : F3_1<3, 0b000001,
196 (ops IntRegs:$dst, MEMrr:$addr),
197 "ldub [$addr], $dst",
198 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
199 def LDUBri : F3_2<3, 0b000001,
200 (ops IntRegs:$dst, MEMri:$addr),
201 "ldub [$addr], $dst",
202 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
203 def LDUHrr : F3_1<3, 0b000010,
204 (ops IntRegs:$dst, MEMrr:$addr),
205 "lduh [$addr], $dst",
206 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
207 def LDUHri : F3_2<3, 0b000010,
208 (ops IntRegs:$dst, MEMri:$addr),
209 "lduh [$addr], $dst",
210 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
211 def LDrr : F3_1<3, 0b000000,
212 (ops IntRegs:$dst, MEMrr:$addr),
214 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
215 def LDri : F3_2<3, 0b000000,
216 (ops IntRegs:$dst, MEMri:$addr),
218 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
220 // Section B.2 - Load Floating-point Instructions, p. 92
221 def LDFrr : F3_1<3, 0b100000,
222 (ops FPRegs:$dst, MEMrr:$addr),
224 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
225 def LDFri : F3_2<3, 0b100000,
226 (ops FPRegs:$dst, MEMri:$addr),
228 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
229 def LDDFrr : F3_1<3, 0b100011,
230 (ops DFPRegs:$dst, MEMrr:$addr),
232 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
233 def LDDFri : F3_2<3, 0b100011,
234 (ops DFPRegs:$dst, MEMri:$addr),
236 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
238 // Section B.4 - Store Integer Instructions, p. 95
239 def STBrr : F3_1<3, 0b000101,
240 (ops MEMrr:$addr, IntRegs:$src),
242 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
243 def STBri : F3_2<3, 0b000101,
244 (ops MEMri:$addr, IntRegs:$src),
246 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
247 def STHrr : F3_1<3, 0b000110,
248 (ops MEMrr:$addr, IntRegs:$src),
250 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
251 def STHri : F3_2<3, 0b000110,
252 (ops MEMri:$addr, IntRegs:$src),
254 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
255 def STrr : F3_1<3, 0b000100,
256 (ops MEMrr:$addr, IntRegs:$src),
258 [(store IntRegs:$src, ADDRrr:$addr)]>;
259 def STri : F3_2<3, 0b000100,
260 (ops MEMri:$addr, IntRegs:$src),
262 [(store IntRegs:$src, ADDRri:$addr)]>;
264 // Section B.5 - Store Floating-point Instructions, p. 97
265 def STFrr : F3_1<3, 0b100100,
266 (ops MEMrr:$addr, FPRegs:$src),
268 [(store FPRegs:$src, ADDRrr:$addr)]>;
269 def STFri : F3_2<3, 0b100100,
270 (ops MEMri:$addr, FPRegs:$src),
272 [(store FPRegs:$src, ADDRri:$addr)]>;
273 def STDFrr : F3_1<3, 0b100111,
274 (ops MEMrr:$addr, DFPRegs:$src),
276 [(store DFPRegs:$src, ADDRrr:$addr)]>;
277 def STDFri : F3_2<3, 0b100111,
278 (ops MEMri:$addr, DFPRegs:$src),
280 [(store DFPRegs:$src, ADDRri:$addr)]>;
282 // Section B.9 - SETHI Instruction, p. 104
283 def SETHIi: F2_1<0b100,
284 (ops IntRegs:$dst, i32imm:$src),
286 [(set IntRegs:$dst, SETHIimm:$src)]>;
288 // Section B.10 - NOP Instruction, p. 105
289 // (It's a special case of SETHI)
290 let rd = 0, imm22 = 0 in
291 def NOP : F2_1<0b100, (ops), "nop", []>;
293 // Section B.11 - Logical Instructions, p. 106
294 def ANDrr : F3_1<2, 0b000001,
295 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
297 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
298 def ANDri : F3_2<2, 0b000001,
299 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
301 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
302 def ANDNrr : F3_1<2, 0b000101,
303 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
305 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
306 def ANDNri : F3_2<2, 0b000101,
307 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
308 "andn $b, $c, $dst", []>;
309 def ORrr : F3_1<2, 0b000010,
310 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
312 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
313 def ORri : F3_2<2, 0b000010,
314 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
316 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
317 def ORNrr : F3_1<2, 0b000110,
318 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
320 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
321 def ORNri : F3_2<2, 0b000110,
322 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
323 "orn $b, $c, $dst", []>;
324 def XORrr : F3_1<2, 0b000011,
325 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
327 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
328 def XORri : F3_2<2, 0b000011,
329 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
331 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
332 def XNORrr : F3_1<2, 0b000111,
333 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
335 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
336 def XNORri : F3_2<2, 0b000111,
337 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
338 "xnor $b, $c, $dst", []>;
340 // Section B.12 - Shift Instructions, p. 107
341 def SLLrr : F3_1<2, 0b100101,
342 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
344 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
345 def SLLri : F3_2<2, 0b100101,
346 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
348 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
349 def SRLrr : F3_1<2, 0b100110,
350 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
352 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
353 def SRLri : F3_2<2, 0b100110,
354 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
356 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
357 def SRArr : F3_1<2, 0b100111,
358 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
360 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
361 def SRAri : F3_2<2, 0b100111,
362 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
364 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
366 // Section B.13 - Add Instructions, p. 108
367 def ADDrr : F3_1<2, 0b000000,
368 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
370 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
371 def ADDri : F3_2<2, 0b000000,
372 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
374 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
375 def ADDCCrr : F3_1<2, 0b010000,
376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
377 "addcc $b, $c, $dst", []>;
378 def ADDCCri : F3_2<2, 0b010000,
379 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
380 "addcc $b, $c, $dst", []>;
381 def ADDXrr : F3_1<2, 0b001000,
382 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
383 "addx $b, $c, $dst", []>;
384 def ADDXri : F3_2<2, 0b001000,
385 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
386 "addx $b, $c, $dst", []>;
388 // Section B.15 - Subtract Instructions, p. 110
389 def SUBrr : F3_1<2, 0b000100,
390 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
392 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
393 def SUBri : F3_2<2, 0b000100,
394 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
396 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
397 def SUBXrr : F3_1<2, 0b001100,
398 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
399 "subx $b, $c, $dst", []>;
400 def SUBXri : F3_2<2, 0b001100,
401 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
402 "subx $b, $c, $dst", []>;
403 def SUBCCrr : F3_1<2, 0b010100,
404 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
405 "subcc $b, $c, $dst",
406 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
407 def SUBCCri : F3_2<2, 0b010100,
408 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
409 "subcc $b, $c, $dst",
410 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
411 def SUBXCCrr: F3_1<2, 0b011100,
412 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
413 "subxcc $b, $c, $dst", []>;
415 // Section B.18 - Multiply Instructions, p. 113
416 def UMULrr : F3_1<2, 0b001010,
417 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
418 "umul $b, $c, $dst", []>;
419 def UMULri : F3_2<2, 0b001010,
420 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
421 "umul $b, $c, $dst", []>;
422 def SMULrr : F3_1<2, 0b001011,
423 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
425 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
426 def SMULri : F3_2<2, 0b001011,
427 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
429 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
431 // Section B.19 - Divide Instructions, p. 115
432 def UDIVrr : F3_1<2, 0b001110,
433 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
434 "udiv $b, $c, $dst", []>;
435 def UDIVri : F3_2<2, 0b001110,
436 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
437 "udiv $b, $c, $dst", []>;
438 def SDIVrr : F3_1<2, 0b001111,
439 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
440 "sdiv $b, $c, $dst", []>;
441 def SDIVri : F3_2<2, 0b001111,
442 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
443 "sdiv $b, $c, $dst", []>;
445 // Section B.20 - SAVE and RESTORE, p. 117
446 def SAVErr : F3_1<2, 0b111100,
447 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
448 "save $b, $c, $dst", []>;
449 def SAVEri : F3_2<2, 0b111100,
450 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
451 "save $b, $c, $dst", []>;
452 def RESTORErr : F3_1<2, 0b111101,
453 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
454 "restore $b, $c, $dst", []>;
455 def RESTOREri : F3_2<2, 0b111101,
456 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
457 "restore $b, $c, $dst", []>;
459 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
461 // conditional branch class:
462 class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
463 : F2_2<cc, 0b010, ops, asmstr, pattern> {
465 let isTerminator = 1;
466 let hasDelaySlot = 1;
471 def BA : BranchV8<0b1000, (ops brtarget:$dst),
474 def BNE : BranchV8<0b1001, (ops brtarget:$dst),
476 [(V8bricc bb:$dst, SETNE, ICC)]>;
477 def BE : BranchV8<0b0001, (ops brtarget:$dst),
479 [(V8bricc bb:$dst, SETEQ, ICC)]>;
480 def BG : BranchV8<0b1010, (ops brtarget:$dst),
482 [(V8bricc bb:$dst, SETGT, ICC)]>;
483 def BLE : BranchV8<0b0010, (ops brtarget:$dst),
485 [(V8bricc bb:$dst, SETLE, ICC)]>;
486 def BGE : BranchV8<0b1011, (ops brtarget:$dst),
488 [(V8bricc bb:$dst, SETGE, ICC)]>;
489 def BL : BranchV8<0b0011, (ops brtarget:$dst),
491 [(V8bricc bb:$dst, SETLT, ICC)]>;
492 def BGU : BranchV8<0b1100, (ops brtarget:$dst),
494 [(V8bricc bb:$dst, SETUGT, ICC)]>;
495 def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
497 [(V8bricc bb:$dst, SETULE, ICC)]>;
498 def BCC : BranchV8<0b1101, (ops brtarget:$dst),
500 [(V8bricc bb:$dst, SETUGE, ICC)]>;
501 def BCS : BranchV8<0b0101, (ops brtarget:$dst),
503 [(V8bricc bb:$dst, SETULT, ICC)]>;
505 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
507 // floating-point conditional branch class:
508 class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
509 : F2_2<cc, 0b110, ops, asmstr, pattern> {
511 let isTerminator = 1;
512 let hasDelaySlot = 1;
516 def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
518 [(V8brfcc bb:$dst, SETUO, FCC)]>;
519 def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
521 [(V8brfcc bb:$dst, SETGT, FCC)]>;
522 def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
524 [(V8brfcc bb:$dst, SETUGT, FCC)]>;
525 def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
527 [(V8brfcc bb:$dst, SETLT, FCC)]>;
528 def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
530 [(V8brfcc bb:$dst, SETULT, FCC)]>;
531 def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
533 [(V8brfcc bb:$dst, SETONE, FCC)]>;
534 def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
536 [(V8brfcc bb:$dst, SETNE, FCC)]>;
537 def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
539 [(V8brfcc bb:$dst, SETEQ, FCC)]>;
540 def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
542 [(V8brfcc bb:$dst, SETUEQ, FCC)]>;
543 def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
545 [(V8brfcc bb:$dst, SETGE, FCC)]>;
546 def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
548 [(V8brfcc bb:$dst, SETUGE, FCC)]>;
549 def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
551 [(V8brfcc bb:$dst, SETLE, FCC)]>;
552 def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
554 [(V8brfcc bb:$dst, SETULE, FCC)]>;
555 def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
557 [(V8brfcc bb:$dst, SETO, FCC)]>;
561 // Section B.24 - Call and Link Instruction, p. 125
562 // This is the only Format 1 instruction
563 let Uses = [O0, O1, O2, O3, O4, O5],
564 hasDelaySlot = 1, isCall = 1, noResults = 1,
565 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
566 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
567 def CALL : InstV8<(ops calltarget:$dst),
571 let Inst{29-0} = disp;
575 def JMPLrr : F3_1<2, 0b111000,
578 [(call ADDRrr:$ptr)]>;
579 def JMPLri : F3_2<2, 0b111000,
582 [(call ADDRri:$ptr)]>;
585 // Section B.28 - Read State Register Instructions
586 def RDY : F3_1<2, 0b101000,
590 // Section B.29 - Write State Register Instructions
591 def WRYrr : F3_1<2, 0b110000,
592 (ops IntRegs:$b, IntRegs:$c),
593 "wr $b, $c, %y", []>;
594 def WRYri : F3_2<2, 0b110000,
595 (ops IntRegs:$b, i32imm:$c),
596 "wr $b, $c, %y", []>;
598 // Convert Integer to Floating-point Instructions, p. 141
599 def FITOS : F3_3<2, 0b110100, 0b011000100,
600 (ops FPRegs:$dst, FPRegs:$src),
602 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
603 def FITOD : F3_3<2, 0b110100, 0b011001000,
604 (ops DFPRegs:$dst, FPRegs:$src),
606 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
608 // Convert Floating-point to Integer Instructions, p. 142
609 def FSTOI : F3_3<2, 0b110100, 0b011010001,
610 (ops FPRegs:$dst, FPRegs:$src),
612 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
613 def FDTOI : F3_3<2, 0b110100, 0b011010010,
614 (ops FPRegs:$dst, DFPRegs:$src),
616 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
618 // Convert between Floating-point Formats Instructions, p. 143
619 def FSTOD : F3_3<2, 0b110100, 0b011001001,
620 (ops DFPRegs:$dst, FPRegs:$src),
622 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
623 def FDTOS : F3_3<2, 0b110100, 0b011000110,
624 (ops FPRegs:$dst, DFPRegs:$src),
626 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
628 // Floating-point Move Instructions, p. 144
629 def FMOVS : F3_3<2, 0b110100, 0b000000001,
630 (ops FPRegs:$dst, FPRegs:$src),
631 "fmovs $src, $dst", []>;
632 def FNEGS : F3_3<2, 0b110100, 0b000000101,
633 (ops FPRegs:$dst, FPRegs:$src),
635 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
636 def FABSS : F3_3<2, 0b110100, 0b000001001,
637 (ops FPRegs:$dst, FPRegs:$src),
639 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
642 // Floating-point Square Root Instructions, p.145
643 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
644 (ops FPRegs:$dst, FPRegs:$src),
646 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
647 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
648 (ops DFPRegs:$dst, DFPRegs:$src),
650 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
654 // Floating-point Add and Subtract Instructions, p. 146
655 def FADDS : F3_3<2, 0b110100, 0b001000001,
656 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
657 "fadds $src1, $src2, $dst",
658 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
659 def FADDD : F3_3<2, 0b110100, 0b001000010,
660 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
661 "faddd $src1, $src2, $dst",
662 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
663 def FSUBS : F3_3<2, 0b110100, 0b001000101,
664 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
665 "fsubs $src1, $src2, $dst",
666 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
667 def FSUBD : F3_3<2, 0b110100, 0b001000110,
668 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
669 "fsubd $src1, $src2, $dst",
670 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
672 // Floating-point Multiply and Divide Instructions, p. 147
673 def FMULS : F3_3<2, 0b110100, 0b001001001,
674 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
675 "fmuls $src1, $src2, $dst",
676 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
677 def FMULD : F3_3<2, 0b110100, 0b001001010,
678 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
679 "fmuld $src1, $src2, $dst",
680 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
681 def FSMULD : F3_3<2, 0b110100, 0b001101001,
682 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
683 "fsmuld $src1, $src2, $dst",
684 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
685 (fextend FPRegs:$src2)))]>;
686 def FDIVS : F3_3<2, 0b110100, 0b001001101,
687 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
688 "fdivs $src1, $src2, $dst",
689 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
690 def FDIVD : F3_3<2, 0b110100, 0b001001110,
691 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
692 "fdivd $src1, $src2, $dst",
693 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
695 // Floating-point Compare Instructions, p. 148
696 // Note: the 2nd template arg is different for these guys.
697 // Note 2: the result of a FCMP is not available until the 2nd cycle
698 // after the instr is retired, but there is no interlock. This behavior
699 // is modelled with a forced noop after the instruction.
700 def FCMPS : F3_3<2, 0b110101, 0b001010001,
701 (ops FPRegs:$src1, FPRegs:$src2),
702 "fcmps $src1, $src2\n\tnop",
703 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
704 def FCMPD : F3_3<2, 0b110101, 0b001010010,
705 (ops DFPRegs:$src1, DFPRegs:$src2),
706 "fcmpd $src1, $src2\n\tnop",
707 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
709 //===----------------------------------------------------------------------===//
710 // Non-Instruction Patterns
711 //===----------------------------------------------------------------------===//
714 def : Pat<(i32 simm13:$val),
715 (ORri G0, imm:$val)>;
716 // Arbitrary immediates.
717 def : Pat<(i32 imm:$val),
718 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
720 // Global addresses, constant pool entries
721 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
722 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
723 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
724 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
726 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
727 def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
728 (ADDri IntRegs:$r, tglobaladdr:$in)>;
729 def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
730 (ADDri IntRegs:$r, tconstpool:$in)>;
734 def : Pat<(call tglobaladdr:$dst),
735 (CALL tglobaladdr:$dst)>;
736 def : Pat<(call externalsym:$dst),
737 (CALL externalsym:$dst)>;
739 def : Pat<(ret), (RETL)>;
741 // Map integer extload's to zextloads.
742 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
743 def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
744 def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
745 def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
746 def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
747 def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
749 // zextload bool -> zextload byte
750 def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
751 def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
753 // truncstore bool -> truncstore byte.
754 def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
755 (STBrr ADDRrr:$addr, IntRegs:$src)>;
756 def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
757 (STBri ADDRri:$addr, IntRegs:$src)>;