1 //===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // HasV9 - This predicate is true when the target processor supports V9
25 // instructions. Note that the machine may be running in 32-bit mode.
26 def HasV9 : Predicate<"Subtarget.isV9()">;
28 // HasNoV9 - This predicate is true when the target doesn't have V9
29 // instructions. Use of this is just a hack for the isel not having proper
30 // costs for V8 instructions that are more expensive than their V9 ones.
31 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
33 // HasVIS - This is true when the target processor has VIS extensions.
34 def HasVIS : Predicate<"Subtarget.isVIS()">;
36 // UseDeprecatedInsts - This predicate is true when the target processor is a
37 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38 // to use when appropriate. In either of these cases, the instruction selector
39 // will pick deprecated instructions.
40 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
42 //===----------------------------------------------------------------------===//
43 // Instruction Pattern Stuff
44 //===----------------------------------------------------------------------===//
46 def simm11 : PatLeaf<(imm), [{
47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
51 def simm13 : PatLeaf<(imm), [{
52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
56 def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
60 def HI22 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
65 def SETHIimm : PatLeaf<(imm), [{
66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
70 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
71 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
74 def MEMrr : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let MIOperandInfo = (ops IntRegs, IntRegs);
78 def MEMri : Operand<i32> {
79 let PrintMethod = "printMemOperand";
80 let MIOperandInfo = (ops IntRegs, i32imm);
83 // Branch targets have OtherVT type.
84 def brtarget : Operand<OtherVT>;
85 def calltarget : Operand<i32>;
87 // Operand for printing out a condition code.
88 let PrintMethod = "printCCOperand" in
89 def CCOp : Operand<i32>;
92 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
94 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
98 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
100 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
102 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
103 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
104 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
105 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
107 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
108 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
110 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
111 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
113 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
114 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
116 // These are target-independent nodes, but have target-specific formats.
117 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
118 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
121 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
122 [SDNPHasChain, SDNPOutFlag]>;
123 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
124 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
127 def call : SDNode<"SPISD::CALL", SDT_SPCall,
128 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
130 def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
131 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
132 [SDNPHasChain, SDNPOptInFlag]>;
134 //===----------------------------------------------------------------------===//
135 // SPARC Flag Conditions
136 //===----------------------------------------------------------------------===//
138 // Note that these values must be kept in sync with the CCOp::CondCode enum
140 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
141 def ICC_NE : ICC_VAL< 9>; // Not Equal
142 def ICC_E : ICC_VAL< 1>; // Equal
143 def ICC_G : ICC_VAL<10>; // Greater
144 def ICC_LE : ICC_VAL< 2>; // Less or Equal
145 def ICC_GE : ICC_VAL<11>; // Greater or Equal
146 def ICC_L : ICC_VAL< 3>; // Less
147 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
148 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
149 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
150 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
151 def ICC_POS : ICC_VAL<14>; // Positive
152 def ICC_NEG : ICC_VAL< 6>; // Negative
153 def ICC_VC : ICC_VAL<15>; // Overflow Clear
154 def ICC_VS : ICC_VAL< 7>; // Overflow Set
156 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
157 def FCC_U : FCC_VAL<23>; // Unordered
158 def FCC_G : FCC_VAL<22>; // Greater
159 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
160 def FCC_L : FCC_VAL<20>; // Less
161 def FCC_UL : FCC_VAL<19>; // Unordered or Less
162 def FCC_LG : FCC_VAL<18>; // Less or Greater
163 def FCC_NE : FCC_VAL<17>; // Not Equal
164 def FCC_E : FCC_VAL<25>; // Equal
165 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
166 def FCC_GE : FCC_VAL<25>; // Greater or Equal
167 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
168 def FCC_LE : FCC_VAL<27>; // Less or Equal
169 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
170 def FCC_O : FCC_VAL<29>; // Ordered
172 //===----------------------------------------------------------------------===//
173 // Instruction Class Templates
174 //===----------------------------------------------------------------------===//
176 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
177 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
178 def rr : F3_1<2, Op3Val,
179 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
180 !strconcat(OpcStr, " $b, $c, $dst"),
181 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
182 def ri : F3_2<2, Op3Val,
183 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
184 !strconcat(OpcStr, " $b, $c, $dst"),
185 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
188 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
190 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
191 def rr : F3_1<2, Op3Val,
192 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
193 !strconcat(OpcStr, " $b, $c, $dst"), []>;
194 def ri : F3_2<2, Op3Val,
195 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
196 !strconcat(OpcStr, " $b, $c, $dst"), []>;
199 //===----------------------------------------------------------------------===//
201 //===----------------------------------------------------------------------===//
203 // Pseudo instructions.
204 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
205 : InstSP<outs, ins, asmstr, pattern>;
207 let Defs = [O6], Uses = [O6] in {
208 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
209 "!ADJCALLSTACKDOWN $amt",
210 [(callseq_start imm:$amt)]>;
211 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
212 "!ADJCALLSTACKUP $amt1",
213 [(callseq_end imm:$amt1, imm:$amt2)]>;
216 let isImplicitDef = 1 in {
217 def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
218 "!IMPLICIT_DEF $dst",
219 [(set IntRegs:$dst, (undef))]>;
220 def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
221 [(set FPRegs:$dst, (undef))]>;
222 def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
223 [(set DFPRegs:$dst, (undef))]>;
226 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
228 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
229 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
230 "!FpMOVD $src, $dst", []>;
231 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
232 "!FpNEGD $src, $dst",
233 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
234 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
235 "!FpABSD $src, $dst",
236 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
239 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
240 // scheduler into a branch sequence. This has to handle all permutations of
241 // selection between i32/f32/f64 on ICC and FCC.
242 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
243 def SELECT_CC_Int_ICC
244 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
245 "; SELECT_CC_Int_ICC PSEUDO!",
246 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
248 def SELECT_CC_Int_FCC
249 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
250 "; SELECT_CC_Int_FCC PSEUDO!",
251 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
254 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
255 "; SELECT_CC_FP_ICC PSEUDO!",
256 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
259 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
260 "; SELECT_CC_FP_FCC PSEUDO!",
261 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
263 def SELECT_CC_DFP_ICC
264 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
265 "; SELECT_CC_DFP_ICC PSEUDO!",
266 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
268 def SELECT_CC_DFP_FCC
269 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
270 "; SELECT_CC_DFP_FCC PSEUDO!",
271 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
276 // Section A.3 - Synthetic Instructions, p. 85
277 // special cases of JMPL:
278 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
279 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
280 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>;
283 // Section B.1 - Load Integer Instructions, p. 90
284 def LDSBrr : F3_1<3, 0b001001,
285 (outs IntRegs:$dst), (ins MEMrr:$addr),
286 "ldsb [$addr], $dst",
287 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
288 def LDSBri : F3_2<3, 0b001001,
289 (outs IntRegs:$dst), (ins MEMri:$addr),
290 "ldsb [$addr], $dst",
291 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
292 def LDSHrr : F3_1<3, 0b001010,
293 (outs IntRegs:$dst), (ins MEMrr:$addr),
294 "ldsh [$addr], $dst",
295 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
296 def LDSHri : F3_2<3, 0b001010,
297 (outs IntRegs:$dst), (ins MEMri:$addr),
298 "ldsh [$addr], $dst",
299 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
300 def LDUBrr : F3_1<3, 0b000001,
301 (outs IntRegs:$dst), (ins MEMrr:$addr),
302 "ldub [$addr], $dst",
303 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
304 def LDUBri : F3_2<3, 0b000001,
305 (outs IntRegs:$dst), (ins MEMri:$addr),
306 "ldub [$addr], $dst",
307 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
308 def LDUHrr : F3_1<3, 0b000010,
309 (outs IntRegs:$dst), (ins MEMrr:$addr),
310 "lduh [$addr], $dst",
311 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
312 def LDUHri : F3_2<3, 0b000010,
313 (outs IntRegs:$dst), (ins MEMri:$addr),
314 "lduh [$addr], $dst",
315 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
316 def LDrr : F3_1<3, 0b000000,
317 (outs IntRegs:$dst), (ins MEMrr:$addr),
319 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
320 def LDri : F3_2<3, 0b000000,
321 (outs IntRegs:$dst), (ins MEMri:$addr),
323 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
325 // Section B.2 - Load Floating-point Instructions, p. 92
326 def LDFrr : F3_1<3, 0b100000,
327 (outs FPRegs:$dst), (ins MEMrr:$addr),
329 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
330 def LDFri : F3_2<3, 0b100000,
331 (outs FPRegs:$dst), (ins MEMri:$addr),
333 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
334 def LDDFrr : F3_1<3, 0b100011,
335 (outs DFPRegs:$dst), (ins MEMrr:$addr),
337 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
338 def LDDFri : F3_2<3, 0b100011,
339 (outs DFPRegs:$dst), (ins MEMri:$addr),
341 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
343 // Section B.4 - Store Integer Instructions, p. 95
344 def STBrr : F3_1<3, 0b000101,
345 (outs), (ins MEMrr:$addr, IntRegs:$src),
347 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
348 def STBri : F3_2<3, 0b000101,
349 (outs), (ins MEMri:$addr, IntRegs:$src),
351 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
352 def STHrr : F3_1<3, 0b000110,
353 (outs), (ins MEMrr:$addr, IntRegs:$src),
355 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
356 def STHri : F3_2<3, 0b000110,
357 (outs), (ins MEMri:$addr, IntRegs:$src),
359 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
360 def STrr : F3_1<3, 0b000100,
361 (outs), (ins MEMrr:$addr, IntRegs:$src),
363 [(store IntRegs:$src, ADDRrr:$addr)]>;
364 def STri : F3_2<3, 0b000100,
365 (outs), (ins MEMri:$addr, IntRegs:$src),
367 [(store IntRegs:$src, ADDRri:$addr)]>;
369 // Section B.5 - Store Floating-point Instructions, p. 97
370 def STFrr : F3_1<3, 0b100100,
371 (outs), (ins MEMrr:$addr, FPRegs:$src),
373 [(store FPRegs:$src, ADDRrr:$addr)]>;
374 def STFri : F3_2<3, 0b100100,
375 (outs), (ins MEMri:$addr, FPRegs:$src),
377 [(store FPRegs:$src, ADDRri:$addr)]>;
378 def STDFrr : F3_1<3, 0b100111,
379 (outs), (ins MEMrr:$addr, DFPRegs:$src),
381 [(store DFPRegs:$src, ADDRrr:$addr)]>;
382 def STDFri : F3_2<3, 0b100111,
383 (outs), (ins MEMri:$addr, DFPRegs:$src),
385 [(store DFPRegs:$src, ADDRri:$addr)]>;
387 // Section B.9 - SETHI Instruction, p. 104
388 def SETHIi: F2_1<0b100,
389 (outs IntRegs:$dst), (ins i32imm:$src),
391 [(set IntRegs:$dst, SETHIimm:$src)]>;
393 // Section B.10 - NOP Instruction, p. 105
394 // (It's a special case of SETHI)
395 let rd = 0, imm22 = 0 in
396 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
398 // Section B.11 - Logical Instructions, p. 106
399 defm AND : F3_12<"and", 0b000001, and>;
401 def ANDNrr : F3_1<2, 0b000101,
402 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
404 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
405 def ANDNri : F3_2<2, 0b000101,
406 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
407 "andn $b, $c, $dst", []>;
409 defm OR : F3_12<"or", 0b000010, or>;
411 def ORNrr : F3_1<2, 0b000110,
412 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
414 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
415 def ORNri : F3_2<2, 0b000110,
416 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
417 "orn $b, $c, $dst", []>;
418 defm XOR : F3_12<"xor", 0b000011, xor>;
420 def XNORrr : F3_1<2, 0b000111,
421 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
423 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
424 def XNORri : F3_2<2, 0b000111,
425 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
426 "xnor $b, $c, $dst", []>;
428 // Section B.12 - Shift Instructions, p. 107
429 defm SLL : F3_12<"sll", 0b100101, shl>;
430 defm SRL : F3_12<"srl", 0b100110, srl>;
431 defm SRA : F3_12<"sra", 0b100111, sra>;
433 // Section B.13 - Add Instructions, p. 108
434 defm ADD : F3_12<"add", 0b000000, add>;
436 // "LEA" forms of add (patterns to make tblgen happy)
437 def LEA_ADDri : F3_2<2, 0b000000,
438 (outs IntRegs:$dst), (ins MEMri:$addr),
439 "add ${addr:arith}, $dst",
440 [(set IntRegs:$dst, ADDRri:$addr)]>;
442 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
443 defm ADDX : F3_12<"addx", 0b001000, adde>;
445 // Section B.15 - Subtract Instructions, p. 110
446 defm SUB : F3_12 <"sub" , 0b000100, sub>;
447 defm SUBX : F3_12 <"subx" , 0b001100, sube>;
448 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
450 def SUBXCCrr: F3_1<2, 0b011100,
451 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
452 "subxcc $b, $c, $dst", []>;
454 // Section B.18 - Multiply Instructions, p. 113
455 defm UMUL : F3_12np<"umul", 0b001010>;
456 defm SMUL : F3_12 <"smul", 0b001011, mul>;
459 // Section B.19 - Divide Instructions, p. 115
460 defm UDIV : F3_12np<"udiv", 0b001110>;
461 defm SDIV : F3_12np<"sdiv", 0b001111>;
463 // Section B.20 - SAVE and RESTORE, p. 117
464 defm SAVE : F3_12np<"save" , 0b111100>;
465 defm RESTORE : F3_12np<"restore", 0b111101>;
467 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
469 // conditional branch class:
470 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
471 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
473 let isTerminator = 1;
474 let hasDelaySlot = 1;
478 def BA : BranchSP<0b1000, (ins brtarget:$dst),
482 // FIXME: the encoding for the JIT should look at the condition field.
483 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
485 [(SPbricc bb:$dst, imm:$cc)]>;
488 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
490 // floating-point conditional branch class:
491 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
492 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
494 let isTerminator = 1;
495 let hasDelaySlot = 1;
498 // FIXME: the encoding for the JIT should look at the condition field.
499 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
501 [(SPbrfcc bb:$dst, imm:$cc)]>;
504 // Section B.24 - Call and Link Instruction, p. 125
505 // This is the only Format 1 instruction
506 let Uses = [O0, O1, O2, O3, O4, O5],
507 hasDelaySlot = 1, isCall = 1,
508 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
509 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
510 def CALL : InstSP<(outs), (ins calltarget:$dst),
514 let Inst{29-0} = disp;
518 def JMPLrr : F3_1<2, 0b111000,
519 (outs), (ins MEMrr:$ptr),
521 [(call ADDRrr:$ptr)]>;
522 def JMPLri : F3_2<2, 0b111000,
523 (outs), (ins MEMri:$ptr),
525 [(call ADDRri:$ptr)]>;
528 // Section B.28 - Read State Register Instructions
529 def RDY : F3_1<2, 0b101000,
530 (outs IntRegs:$dst), (ins),
533 // Section B.29 - Write State Register Instructions
534 def WRYrr : F3_1<2, 0b110000,
535 (outs), (ins IntRegs:$b, IntRegs:$c),
536 "wr $b, $c, %y", []>;
537 def WRYri : F3_2<2, 0b110000,
538 (outs), (ins IntRegs:$b, i32imm:$c),
539 "wr $b, $c, %y", []>;
541 // Convert Integer to Floating-point Instructions, p. 141
542 def FITOS : F3_3<2, 0b110100, 0b011000100,
543 (outs FPRegs:$dst), (ins FPRegs:$src),
545 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
546 def FITOD : F3_3<2, 0b110100, 0b011001000,
547 (outs DFPRegs:$dst), (ins FPRegs:$src),
549 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
551 // Convert Floating-point to Integer Instructions, p. 142
552 def FSTOI : F3_3<2, 0b110100, 0b011010001,
553 (outs FPRegs:$dst), (ins FPRegs:$src),
555 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
556 def FDTOI : F3_3<2, 0b110100, 0b011010010,
557 (outs FPRegs:$dst), (ins DFPRegs:$src),
559 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
561 // Convert between Floating-point Formats Instructions, p. 143
562 def FSTOD : F3_3<2, 0b110100, 0b011001001,
563 (outs DFPRegs:$dst), (ins FPRegs:$src),
565 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
566 def FDTOS : F3_3<2, 0b110100, 0b011000110,
567 (outs FPRegs:$dst), (ins DFPRegs:$src),
569 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
571 // Floating-point Move Instructions, p. 144
572 def FMOVS : F3_3<2, 0b110100, 0b000000001,
573 (outs FPRegs:$dst), (ins FPRegs:$src),
574 "fmovs $src, $dst", []>;
575 def FNEGS : F3_3<2, 0b110100, 0b000000101,
576 (outs FPRegs:$dst), (ins FPRegs:$src),
578 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
579 def FABSS : F3_3<2, 0b110100, 0b000001001,
580 (outs FPRegs:$dst), (ins FPRegs:$src),
582 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
585 // Floating-point Square Root Instructions, p.145
586 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
587 (outs FPRegs:$dst), (ins FPRegs:$src),
589 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
590 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
591 (outs DFPRegs:$dst), (ins DFPRegs:$src),
593 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
597 // Floating-point Add and Subtract Instructions, p. 146
598 def FADDS : F3_3<2, 0b110100, 0b001000001,
599 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
600 "fadds $src1, $src2, $dst",
601 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
602 def FADDD : F3_3<2, 0b110100, 0b001000010,
603 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
604 "faddd $src1, $src2, $dst",
605 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
606 def FSUBS : F3_3<2, 0b110100, 0b001000101,
607 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
608 "fsubs $src1, $src2, $dst",
609 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
610 def FSUBD : F3_3<2, 0b110100, 0b001000110,
611 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
612 "fsubd $src1, $src2, $dst",
613 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
615 // Floating-point Multiply and Divide Instructions, p. 147
616 def FMULS : F3_3<2, 0b110100, 0b001001001,
617 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
618 "fmuls $src1, $src2, $dst",
619 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
620 def FMULD : F3_3<2, 0b110100, 0b001001010,
621 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
622 "fmuld $src1, $src2, $dst",
623 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
624 def FSMULD : F3_3<2, 0b110100, 0b001101001,
625 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
626 "fsmuld $src1, $src2, $dst",
627 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
628 (fextend FPRegs:$src2)))]>;
629 def FDIVS : F3_3<2, 0b110100, 0b001001101,
630 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
631 "fdivs $src1, $src2, $dst",
632 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
633 def FDIVD : F3_3<2, 0b110100, 0b001001110,
634 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
635 "fdivd $src1, $src2, $dst",
636 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
638 // Floating-point Compare Instructions, p. 148
639 // Note: the 2nd template arg is different for these guys.
640 // Note 2: the result of a FCMP is not available until the 2nd cycle
641 // after the instr is retired, but there is no interlock. This behavior
642 // is modelled with a forced noop after the instruction.
643 def FCMPS : F3_3<2, 0b110101, 0b001010001,
644 (outs), (ins FPRegs:$src1, FPRegs:$src2),
645 "fcmps $src1, $src2\n\tnop",
646 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
647 def FCMPD : F3_3<2, 0b110101, 0b001010010,
648 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
649 "fcmpd $src1, $src2\n\tnop",
650 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
653 //===----------------------------------------------------------------------===//
655 //===----------------------------------------------------------------------===//
657 // V9 Conditional Moves.
658 let Predicates = [HasV9], isTwoAddress = 1 in {
659 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
660 // FIXME: Add instruction encodings for the JIT some day.
662 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
663 "mov$cc %icc, $F, $dst",
665 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
667 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
668 "mov$cc %icc, $F, $dst",
670 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
673 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
674 "mov$cc %fcc0, $F, $dst",
676 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
678 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
679 "mov$cc %fcc0, $F, $dst",
681 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
684 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
685 "fmovs$cc %icc, $F, $dst",
687 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
689 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
690 "fmovd$cc %icc, $F, $dst",
692 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
694 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
695 "fmovs$cc %fcc0, $F, $dst",
697 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
699 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
700 "fmovd$cc %fcc0, $F, $dst",
702 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
706 // Floating-Point Move Instructions, p. 164 of the V9 manual.
707 let Predicates = [HasV9] in {
708 def FMOVD : F3_3<2, 0b110100, 0b000000010,
709 (outs DFPRegs:$dst), (ins DFPRegs:$src),
710 "fmovd $src, $dst", []>;
711 def FNEGD : F3_3<2, 0b110100, 0b000000110,
712 (outs DFPRegs:$dst), (ins DFPRegs:$src),
714 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
715 def FABSD : F3_3<2, 0b110100, 0b000001010,
716 (outs DFPRegs:$dst), (ins DFPRegs:$src),
718 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
721 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
722 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
723 def POPCrr : F3_1<2, 0b101110,
724 (outs IntRegs:$dst), (ins IntRegs:$src),
725 "popc $src, $dst", []>, Requires<[HasV9]>;
726 def : Pat<(ctpop IntRegs:$src),
727 (POPCrr (SLLri IntRegs:$src, 0))>;
729 //===----------------------------------------------------------------------===//
730 // Non-Instruction Patterns
731 //===----------------------------------------------------------------------===//
734 def : Pat<(i32 simm13:$val),
735 (ORri G0, imm:$val)>;
736 // Arbitrary immediates.
737 def : Pat<(i32 imm:$val),
738 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
741 def : Pat<(subc IntRegs:$b, IntRegs:$c),
742 (SUBCCrr IntRegs:$b, IntRegs:$c)>;
743 def : Pat<(subc IntRegs:$b, simm13:$val),
744 (SUBCCri IntRegs:$b, imm:$val)>;
746 // Global addresses, constant pool entries
747 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
748 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
749 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
750 def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
752 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
753 def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
754 (ADDri IntRegs:$r, tglobaladdr:$in)>;
755 def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
756 (ADDri IntRegs:$r, tconstpool:$in)>;
759 def : Pat<(call tglobaladdr:$dst),
760 (CALL tglobaladdr:$dst)>;
761 def : Pat<(call texternalsym:$dst),
762 (CALL texternalsym:$dst)>;
764 def : Pat<(ret), (RETL)>;
766 // Map integer extload's to zextloads.
767 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
768 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
769 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
770 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
771 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
772 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
774 // zextload bool -> zextload byte
775 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
776 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;