1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget->isV9()">,
33 AssemblerPredicate<"FeatureV9">;
35 // HasNoV9 - This predicate is true when the target doesn't have V9
36 // instructions. Use of this is just a hack for the isel not having proper
37 // costs for V8 instructions that are more expensive than their V9 ones.
38 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
40 // HasVIS - This is true when the target processor has VIS extensions.
41 def HasVIS : Predicate<"Subtarget->isVIS()">,
42 AssemblerPredicate<"FeatureVIS">;
43 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
44 AssemblerPredicate<"FeatureVIS2">;
45 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
46 AssemblerPredicate<"FeatureVIS3">;
48 // HasHardQuad - This is true when the target processor supports quad floating
49 // point instructions.
50 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
52 // UseDeprecatedInsts - This predicate is true when the target processor is a
53 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
54 // to use when appropriate. In either of these cases, the instruction selector
55 // will pick deprecated instructions.
56 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
58 //===----------------------------------------------------------------------===//
59 // Instruction Pattern Stuff
60 //===----------------------------------------------------------------------===//
62 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
64 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
66 def LO10 : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
71 def HI22 : SDNodeXForm<imm, [{
72 // Transformation function: shift the immediate value down into the low bits.
73 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
77 def SETHIimm : PatLeaf<(imm), [{
78 return isShiftedUInt<22, 10>(N->getZExtValue());
82 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
83 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
86 def SparcMEMrrAsmOperand : AsmOperandClass {
88 let ParserMethod = "parseMEMOperand";
91 def SparcMEMriAsmOperand : AsmOperandClass {
93 let ParserMethod = "parseMEMOperand";
96 def MEMrr : Operand<iPTR> {
97 let PrintMethod = "printMemOperand";
98 let MIOperandInfo = (ops ptr_rc, ptr_rc);
99 let ParserMatchClass = SparcMEMrrAsmOperand;
101 def MEMri : Operand<iPTR> {
102 let PrintMethod = "printMemOperand";
103 let MIOperandInfo = (ops ptr_rc, i32imm);
104 let ParserMatchClass = SparcMEMriAsmOperand;
107 def TLSSym : Operand<iPTR>;
109 // Branch targets have OtherVT type.
110 def brtarget : Operand<OtherVT> {
111 let EncoderMethod = "getBranchTargetOpValue";
114 def bprtarget : Operand<OtherVT> {
115 let EncoderMethod = "getBranchPredTargetOpValue";
118 def bprtarget16 : Operand<OtherVT> {
119 let EncoderMethod = "getBranchOnRegTargetOpValue";
122 def calltarget : Operand<i32> {
123 let EncoderMethod = "getCallTargetOpValue";
124 let DecoderMethod = "DecodeCall";
127 def simm13Op : Operand<i32> {
128 let DecoderMethod = "DecodeSIMM13";
131 // Operand for printing out a condition code.
132 let PrintMethod = "printCCOperand" in
133 def CCOp : Operand<i32>;
136 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
138 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
140 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
142 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
144 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
146 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
148 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
150 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
153 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
155 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
157 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
158 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
159 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
160 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
161 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
163 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
164 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
166 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
167 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
168 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
169 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
171 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
172 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
173 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
175 // These are target-independent nodes, but have target-specific formats.
176 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
177 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
180 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
181 [SDNPHasChain, SDNPOutGlue]>;
182 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
186 def call : SDNode<"SPISD::CALL", SDT_SPCall,
187 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
190 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
191 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
192 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
194 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
195 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
197 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
198 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
199 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
203 def getPCX : Operand<iPTR> {
204 let PrintMethod = "printGetPCX";
207 //===----------------------------------------------------------------------===//
208 // SPARC Flag Conditions
209 //===----------------------------------------------------------------------===//
211 // Note that these values must be kept in sync with the CCOp::CondCode enum
213 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
214 def ICC_NE : ICC_VAL< 9>; // Not Equal
215 def ICC_E : ICC_VAL< 1>; // Equal
216 def ICC_G : ICC_VAL<10>; // Greater
217 def ICC_LE : ICC_VAL< 2>; // Less or Equal
218 def ICC_GE : ICC_VAL<11>; // Greater or Equal
219 def ICC_L : ICC_VAL< 3>; // Less
220 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
221 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
222 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
223 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
224 def ICC_POS : ICC_VAL<14>; // Positive
225 def ICC_NEG : ICC_VAL< 6>; // Negative
226 def ICC_VC : ICC_VAL<15>; // Overflow Clear
227 def ICC_VS : ICC_VAL< 7>; // Overflow Set
229 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
230 def FCC_U : FCC_VAL<23>; // Unordered
231 def FCC_G : FCC_VAL<22>; // Greater
232 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
233 def FCC_L : FCC_VAL<20>; // Less
234 def FCC_UL : FCC_VAL<19>; // Unordered or Less
235 def FCC_LG : FCC_VAL<18>; // Less or Greater
236 def FCC_NE : FCC_VAL<17>; // Not Equal
237 def FCC_E : FCC_VAL<25>; // Equal
238 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
239 def FCC_GE : FCC_VAL<25>; // Greater or Equal
240 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
241 def FCC_LE : FCC_VAL<27>; // Less or Equal
242 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
243 def FCC_O : FCC_VAL<29>; // Ordered
245 //===----------------------------------------------------------------------===//
246 // Instruction Class Templates
247 //===----------------------------------------------------------------------===//
249 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
250 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
251 RegisterClass RC, ValueType Ty, Operand immOp> {
252 def rr : F3_1<2, Op3Val,
253 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
254 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
255 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
256 def ri : F3_2<2, Op3Val,
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
258 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
259 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
262 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
264 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
265 def rr : F3_1<2, Op3Val,
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
267 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
268 def ri : F3_2<2, Op3Val,
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
270 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
273 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
274 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
275 RegisterClass RC, ValueType Ty> {
276 def rr : F3_1<3, Op3Val,
277 (outs RC:$dst), (ins MEMrr:$addr),
278 !strconcat(OpcStr, " [$addr], $dst"),
279 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
280 def ri : F3_2<3, Op3Val,
281 (outs RC:$dst), (ins MEMri:$addr),
282 !strconcat(OpcStr, " [$addr], $dst"),
283 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
286 // TODO: Instructions of the LoadASI class are currently asm only; hooking up
287 // CodeGen's address spaces to use these is a future task.
288 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
289 RegisterClass RC, ValueType Ty> :
290 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
291 !strconcat(OpcStr, "a [$addr] $asi, $dst"),
294 // LoadA multiclass - As above, but also define alternate address space variant
295 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
296 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
297 Load<OpcStr, Op3Val, OpNode, RC, Ty> {
298 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
301 // The LDSTUB instruction is supported for asm only.
302 // It is unlikely that general-purpose code could make use of it.
303 // CAS is preferred for sparc v9.
304 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
305 "ldstub [$addr], $dst", []>;
306 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
307 "ldstub [$addr], $dst", []>;
308 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
309 (ins MEMrr:$addr, i8imm:$asi),
310 "ldstuba [$addr] $asi, $dst", []>;
312 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
313 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
314 RegisterClass RC, ValueType Ty> {
315 def rr : F3_1<3, Op3Val,
316 (outs), (ins MEMrr:$addr, RC:$rd),
317 !strconcat(OpcStr, " $rd, [$addr]"),
318 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
319 def ri : F3_2<3, Op3Val,
320 (outs), (ins MEMri:$addr, RC:$rd),
321 !strconcat(OpcStr, " $rd, [$addr]"),
322 [(OpNode Ty:$rd, ADDRri:$addr)]>;
325 // TODO: Instructions of the StoreASI class are currently asm only; hooking up
326 // CodeGen's address spaces to use these is a future task.
327 class StoreASI<string OpcStr, bits<6> Op3Val,
328 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
329 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
330 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
333 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
334 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
335 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
336 def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty>;
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 // Pseudo instructions.
344 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
345 : InstSP<outs, ins, asmstr, pattern> {
346 let isCodeGenOnly = 1;
352 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
355 let Defs = [O6], Uses = [O6] in {
356 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
357 "!ADJCALLSTACKDOWN $amt",
358 [(callseq_start timm:$amt)]>;
359 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
360 "!ADJCALLSTACKUP $amt1",
361 [(callseq_end timm:$amt1, timm:$amt2)]>;
364 let hasSideEffects = 1, mayStore = 1 in {
365 let rd = 0, rs1 = 0, rs2 = 0 in
366 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
368 [(flushw)]>, Requires<[HasV9]>;
369 let rd = 0, rs1 = 1, simm13 = 3 in
370 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
375 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
376 // instruction selection into a branch sequence. This has to handle all
377 // permutations of selection between i32/f32/f64 on ICC and FCC.
378 // Expanded after instruction selection.
379 let Uses = [ICC], usesCustomInserter = 1 in {
380 def SELECT_CC_Int_ICC
381 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
382 "; SELECT_CC_Int_ICC PSEUDO!",
383 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
385 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
386 "; SELECT_CC_FP_ICC PSEUDO!",
387 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
389 def SELECT_CC_DFP_ICC
390 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
391 "; SELECT_CC_DFP_ICC PSEUDO!",
392 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
394 def SELECT_CC_QFP_ICC
395 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
396 "; SELECT_CC_QFP_ICC PSEUDO!",
397 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
400 let usesCustomInserter = 1, Uses = [FCC0] in {
402 def SELECT_CC_Int_FCC
403 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
404 "; SELECT_CC_Int_FCC PSEUDO!",
405 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
408 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
409 "; SELECT_CC_FP_FCC PSEUDO!",
410 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
411 def SELECT_CC_DFP_FCC
412 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
413 "; SELECT_CC_DFP_FCC PSEUDO!",
414 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
415 def SELECT_CC_QFP_FCC
416 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
417 "; SELECT_CC_QFP_FCC PSEUDO!",
418 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
421 // Section B.1 - Load Integer Instructions, p. 90
422 let DecoderMethod = "DecodeLoadInt" in {
423 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
424 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
425 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
426 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
427 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
430 let DecoderMethod = "DecodeLoadIntPair" in
431 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32>;
433 // Section B.2 - Load Floating-point Instructions, p. 92
434 let DecoderMethod = "DecodeLoadFP" in {
435 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
436 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32>,
439 let DecoderMethod = "DecodeLoadDFP" in {
440 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
441 def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>,
444 let DecoderMethod = "DecodeLoadQFP" in
445 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
446 Requires<[HasV9, HasHardQuad]>;
448 let DecoderMethod = "DecodeLoadFP" in
449 let Defs = [FSR] in {
451 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
452 "ld [$addr], %fsr", []>;
453 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
454 "ld [$addr], %fsr", []>;
457 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
458 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
459 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
460 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
464 // Section B.4 - Store Integer Instructions, p. 95
465 let DecoderMethod = "DecodeStoreInt" in {
466 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
467 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
468 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
471 let DecoderMethod = "DecodeStoreIntPair" in
472 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>;
474 // Section B.5 - Store Floating-point Instructions, p. 97
475 let DecoderMethod = "DecodeStoreFP" in {
476 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
477 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>,
480 let DecoderMethod = "DecodeStoreDFP" in {
481 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
482 def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>,
485 let DecoderMethod = "DecodeStoreQFP" in
486 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
487 Requires<[HasV9, HasHardQuad]>;
489 let DecoderMethod = "DecodeStoreFP" in
490 let Defs = [FSR] in {
492 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
493 "st %fsr, [$addr]", []>;
494 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
495 "st %fsr, [$addr]", []>;
498 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
499 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
500 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
501 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
505 // Section B.8 - SWAP Register with Memory Instruction
507 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
508 def SWAPrr : F3_1<3, 0b001111,
509 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
510 "swap [$addr], $dst",
511 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
512 def SWAPri : F3_2<3, 0b001111,
513 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
514 "swap [$addr], $dst",
515 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
516 def SWAPArr : F3_1_asi<3, 0b011111,
517 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
518 "swapa [$addr] $asi, $dst",
519 [/*FIXME: pattern?*/]>;
523 // Section B.9 - SETHI Instruction, p. 104
524 def SETHIi: F2_1<0b100,
525 (outs IntRegs:$rd), (ins i32imm:$imm22),
527 [(set i32:$rd, SETHIimm:$imm22)]>;
529 // Section B.10 - NOP Instruction, p. 105
530 // (It's a special case of SETHI)
531 let rd = 0, imm22 = 0 in
532 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
534 // Section B.11 - Logical Instructions, p. 106
535 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
537 def ANDNrr : F3_1<2, 0b000101,
538 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
539 "andn $rs1, $rs2, $rd",
540 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
541 def ANDNri : F3_2<2, 0b000101,
542 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
543 "andn $rs1, $simm13, $rd", []>;
545 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
547 def ORNrr : F3_1<2, 0b000110,
548 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
549 "orn $rs1, $rs2, $rd",
550 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
551 def ORNri : F3_2<2, 0b000110,
552 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
553 "orn $rs1, $simm13, $rd", []>;
554 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
556 def XNORrr : F3_1<2, 0b000111,
557 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
558 "xnor $rs1, $rs2, $rd",
559 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
560 def XNORri : F3_2<2, 0b000111,
561 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
562 "xnor $rs1, $simm13, $rd", []>;
564 let Defs = [ICC] in {
565 defm ANDCC : F3_12np<"andcc", 0b010001>;
566 defm ANDNCC : F3_12np<"andncc", 0b010101>;
567 defm ORCC : F3_12np<"orcc", 0b010010>;
568 defm ORNCC : F3_12np<"orncc", 0b010110>;
569 defm XORCC : F3_12np<"xorcc", 0b010011>;
570 defm XNORCC : F3_12np<"xnorcc", 0b010111>;
573 // Section B.12 - Shift Instructions, p. 107
574 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
575 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
576 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
578 // Section B.13 - Add Instructions, p. 108
579 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
581 // "LEA" forms of add (patterns to make tblgen happy)
582 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
583 def LEA_ADDri : F3_2<2, 0b000000,
584 (outs IntRegs:$dst), (ins MEMri:$addr),
585 "add ${addr:arith}, $dst",
586 [(set iPTR:$dst, ADDRri:$addr)]>;
589 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
592 defm ADDC : F3_12np<"addx", 0b001000>;
594 let Uses = [ICC], Defs = [ICC] in
595 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
597 // Section B.15 - Subtract Instructions, p. 110
598 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
599 let Uses = [ICC], Defs = [ICC] in
600 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
603 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
606 defm SUBC : F3_12np <"subx", 0b001100>;
608 // cmp (from Section A.3) is a specialized alias for subcc
609 let Defs = [ICC], rd = 0 in {
610 def CMPrr : F3_1<2, 0b010100,
611 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
613 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
614 def CMPri : F3_2<2, 0b010100,
615 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
617 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
620 // Section B.18 - Multiply Instructions, p. 113
622 defm UMUL : F3_12np<"umul", 0b001010>;
623 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
626 let Defs = [Y, ICC] in {
627 defm UMULCC : F3_12np<"umulcc", 0b011010>;
628 defm SMULCC : F3_12np<"smulcc", 0b011011>;
631 let Defs = [Y, ICC], Uses = [Y, ICC] in {
632 defm MULSCC : F3_12np<"mulscc", 0b100100>;
635 // Section B.19 - Divide Instructions, p. 115
636 let Uses = [Y], Defs = [Y] in {
637 defm UDIV : F3_12np<"udiv", 0b001110>;
638 defm SDIV : F3_12np<"sdiv", 0b001111>;
641 let Uses = [Y], Defs = [Y, ICC] in {
642 defm UDIVCC : F3_12np<"udivcc", 0b011110>;
643 defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
646 // Section B.20 - SAVE and RESTORE, p. 117
647 defm SAVE : F3_12np<"save" , 0b111100>;
648 defm RESTORE : F3_12np<"restore", 0b111101>;
650 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
652 // unconditional branch class.
653 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
654 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
656 let isTerminator = 1;
657 let hasDelaySlot = 1;
662 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
665 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
667 // conditional branch class:
668 class BranchSP<dag ins, string asmstr, list<dag> pattern>
669 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
671 // conditional branch with annul class:
672 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
673 : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
675 // Conditional branch class on %icc|%xcc with predication:
676 multiclass IPredBranch<string regstr, list<dag> CCPattern> {
677 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
678 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
680 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
681 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
683 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
684 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
686 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
687 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
691 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
694 // Indirect branch instructions.
695 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
696 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
697 def BINDrr : F3_1<2, 0b111000,
698 (outs), (ins MEMrr:$ptr),
700 [(brind ADDRrr:$ptr)]>;
701 def BINDri : F3_2<2, 0b111000,
702 (outs), (ins MEMri:$ptr),
704 [(brind ADDRri:$ptr)]>;
707 let Uses = [ICC] in {
708 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
710 [(SPbricc bb:$imm22, imm:$cond)]>;
711 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
712 "b$cond,a $imm22", []>;
714 let Predicates = [HasV9], cc = 0b00 in
715 defm BPI : IPredBranch<"%icc", []>;
718 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
720 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
722 // floating-point conditional branch class:
723 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
724 : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
726 // floating-point conditional branch with annul class:
727 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
728 : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
730 // Conditional branch class on %fcc0-%fcc3 with predication:
731 multiclass FPredBranch {
732 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
734 "fb$cond $cc, $imm19", []>;
735 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
737 "fb$cond,a $cc, $imm19", []>;
738 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
740 "fb$cond,pn $cc, $imm19", []>;
741 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
743 "fb$cond,a,pn $cc, $imm19", []>;
745 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
747 let Uses = [FCC0] in {
748 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
750 [(SPbrfcc bb:$imm22, imm:$cond)]>;
751 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
752 "fb$cond,a $imm22", []>;
755 let Predicates = [HasV9] in
756 defm BPF : FPredBranch;
759 // Section B.24 - Call and Link Instruction, p. 125
760 // This is the only Format 1 instruction
762 hasDelaySlot = 1, isCall = 1 in {
763 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
767 let Inst{29-0} = disp;
770 // indirect calls: special cases of JMPL.
771 let isCodeGenOnly = 1, rd = 15 in {
772 def CALLrr : F3_1<2, 0b111000,
773 (outs), (ins MEMrr:$ptr, variable_ops),
775 [(call ADDRrr:$ptr)]>;
776 def CALLri : F3_2<2, 0b111000,
777 (outs), (ins MEMri:$ptr, variable_ops),
779 [(call ADDRri:$ptr)]>;
783 // Section B.25 - Jump and Link Instruction
786 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
787 DecoderMethod = "DecodeJMPL" in {
788 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
789 "jmpl $addr, $dst", []>;
790 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
791 "jmpl $addr, $dst", []>;
794 // Section A.3 - Synthetic Instructions, p. 85
795 // special cases of JMPL:
796 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
797 isCodeGenOnly = 1 in {
798 let rd = 0, rs1 = 15 in
799 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
800 "jmp %o7+$val", [(retflag simm13:$val)]>;
802 let rd = 0, rs1 = 31 in
803 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
807 // Section B.26 - Return from Trap Instruction
808 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
809 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
810 def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
812 def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
817 // Section B.27 - Trap on Integer Condition Codes Instruction
818 multiclass TRAP<string regStr> {
819 def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
821 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
822 def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
824 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
827 let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
828 defm TICC : TRAP<"%icc">;
830 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
831 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
833 // Section B.28 - Read State Register Instructions
835 def RDASR : F3_1<2, 0b101000,
836 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
839 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
840 let Predicates = [HasNoV9] in {
841 let rs2 = 0, rs1 = 0, Uses=[PSR] in
842 def RDPSR : F3_1<2, 0b101001,
843 (outs IntRegs:$rd), (ins),
846 let rs2 = 0, rs1 = 0, Uses=[WIM] in
847 def RDWIM : F3_1<2, 0b101010,
848 (outs IntRegs:$rd), (ins),
851 let rs2 = 0, rs1 = 0, Uses=[TBR] in
852 def RDTBR : F3_1<2, 0b101011,
853 (outs IntRegs:$rd), (ins),
857 // Section B.29 - Write State Register Instructions
858 def WRASRrr : F3_1<2, 0b110000,
859 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
860 "wr $rs1, $rs2, $rd", []>;
861 def WRASRri : F3_2<2, 0b110000,
862 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
863 "wr $rs1, $simm13, $rd", []>;
865 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
866 let Predicates = [HasNoV9] in {
867 let Defs = [PSR], rd=0 in {
868 def WRPSRrr : F3_1<2, 0b110001,
869 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
870 "wr $rs1, $rs2, %psr", []>;
871 def WRPSRri : F3_2<2, 0b110001,
872 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
873 "wr $rs1, $simm13, %psr", []>;
876 let Defs = [WIM], rd=0 in {
877 def WRWIMrr : F3_1<2, 0b110010,
878 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
879 "wr $rs1, $rs2, %wim", []>;
880 def WRWIMri : F3_2<2, 0b110010,
881 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
882 "wr $rs1, $simm13, %wim", []>;
885 let Defs = [TBR], rd=0 in {
886 def WRTBRrr : F3_1<2, 0b110011,
887 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
888 "wr $rs1, $rs2, %tbr", []>;
889 def WRTBRri : F3_2<2, 0b110011,
890 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
891 "wr $rs1, $simm13, %tbr", []>;
895 // Section B.30 - STBAR Instruction
896 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
897 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
900 // Section B.31 - Unimplmented Instruction
902 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
905 // Section B.32 - Flush Instruction Memory
907 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
909 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
912 // The no-arg FLUSH is only here for the benefit of the InstAlias
913 // "flush", which cannot seem to use FLUSHrr, due to the inability
914 // to construct a MEMrr with fixed G0 registers.
915 let rs1 = 0, rs2 = 0 in
916 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
919 // Section B.33 - Floating-point Operate (FPop) Instructions
921 // Convert Integer to Floating-point Instructions, p. 141
922 def FITOS : F3_3u<2, 0b110100, 0b011000100,
923 (outs FPRegs:$rd), (ins FPRegs:$rs2),
925 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
926 def FITOD : F3_3u<2, 0b110100, 0b011001000,
927 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
929 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
930 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
931 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
933 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
934 Requires<[HasHardQuad]>;
936 // Convert Floating-point to Integer Instructions, p. 142
937 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
938 (outs FPRegs:$rd), (ins FPRegs:$rs2),
940 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
941 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
942 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
944 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
945 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
946 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
948 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
949 Requires<[HasHardQuad]>;
951 // Convert between Floating-point Formats Instructions, p. 143
952 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
953 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
955 [(set f64:$rd, (fextend f32:$rs2))]>;
956 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
957 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
959 [(set f128:$rd, (fextend f32:$rs2))]>,
960 Requires<[HasHardQuad]>;
961 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
962 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
964 [(set f32:$rd, (fround f64:$rs2))]>;
965 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
966 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
968 [(set f128:$rd, (fextend f64:$rs2))]>,
969 Requires<[HasHardQuad]>;
970 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
971 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
973 [(set f32:$rd, (fround f128:$rs2))]>,
974 Requires<[HasHardQuad]>;
975 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
976 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
978 [(set f64:$rd, (fround f128:$rs2))]>,
979 Requires<[HasHardQuad]>;
981 // Floating-point Move Instructions, p. 144
982 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
983 (outs FPRegs:$rd), (ins FPRegs:$rs2),
984 "fmovs $rs2, $rd", []>;
985 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
986 (outs FPRegs:$rd), (ins FPRegs:$rs2),
988 [(set f32:$rd, (fneg f32:$rs2))]>;
989 def FABSS : F3_3u<2, 0b110100, 0b000001001,
990 (outs FPRegs:$rd), (ins FPRegs:$rs2),
992 [(set f32:$rd, (fabs f32:$rs2))]>;
995 // Floating-point Square Root Instructions, p.145
996 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
997 (outs FPRegs:$rd), (ins FPRegs:$rs2),
999 [(set f32:$rd, (fsqrt f32:$rs2))]>;
1000 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
1001 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1003 [(set f64:$rd, (fsqrt f64:$rs2))]>;
1004 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
1005 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1007 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1008 Requires<[HasHardQuad]>;
1012 // Floating-point Add and Subtract Instructions, p. 146
1013 def FADDS : F3_3<2, 0b110100, 0b001000001,
1014 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1015 "fadds $rs1, $rs2, $rd",
1016 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
1017 def FADDD : F3_3<2, 0b110100, 0b001000010,
1018 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1019 "faddd $rs1, $rs2, $rd",
1020 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
1021 def FADDQ : F3_3<2, 0b110100, 0b001000011,
1022 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1023 "faddq $rs1, $rs2, $rd",
1024 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
1025 Requires<[HasHardQuad]>;
1027 def FSUBS : F3_3<2, 0b110100, 0b001000101,
1028 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1029 "fsubs $rs1, $rs2, $rd",
1030 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
1031 def FSUBD : F3_3<2, 0b110100, 0b001000110,
1032 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1033 "fsubd $rs1, $rs2, $rd",
1034 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
1035 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
1036 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1037 "fsubq $rs1, $rs2, $rd",
1038 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
1039 Requires<[HasHardQuad]>;
1042 // Floating-point Multiply and Divide Instructions, p. 147
1043 def FMULS : F3_3<2, 0b110100, 0b001001001,
1044 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1045 "fmuls $rs1, $rs2, $rd",
1046 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
1047 def FMULD : F3_3<2, 0b110100, 0b001001010,
1048 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1049 "fmuld $rs1, $rs2, $rd",
1050 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
1051 def FMULQ : F3_3<2, 0b110100, 0b001001011,
1052 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1053 "fmulq $rs1, $rs2, $rd",
1054 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1055 Requires<[HasHardQuad]>;
1057 def FSMULD : F3_3<2, 0b110100, 0b001101001,
1058 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1059 "fsmuld $rs1, $rs2, $rd",
1060 [(set f64:$rd, (fmul (fextend f32:$rs1),
1061 (fextend f32:$rs2)))]>;
1062 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
1063 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1064 "fdmulq $rs1, $rs2, $rd",
1065 [(set f128:$rd, (fmul (fextend f64:$rs1),
1066 (fextend f64:$rs2)))]>,
1067 Requires<[HasHardQuad]>;
1069 def FDIVS : F3_3<2, 0b110100, 0b001001101,
1070 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1071 "fdivs $rs1, $rs2, $rd",
1072 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
1073 def FDIVD : F3_3<2, 0b110100, 0b001001110,
1074 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1075 "fdivd $rs1, $rs2, $rd",
1076 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
1077 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
1078 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1079 "fdivq $rs1, $rs2, $rd",
1080 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1081 Requires<[HasHardQuad]>;
1083 // Floating-point Compare Instructions, p. 148
1084 // Note: the 2nd template arg is different for these guys.
1085 // Note 2: the result of a FCMP is not available until the 2nd cycle
1086 // after the instr is retired, but there is no interlock in Sparc V8.
1087 // This behavior is modeled with a forced noop after the instruction in
1090 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1091 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
1092 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1094 [(SPcmpfcc f32:$rs1, f32:$rs2)]>;
1095 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
1096 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1098 [(SPcmpfcc f64:$rs1, f64:$rs2)]>;
1099 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1100 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1102 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1103 Requires<[HasHardQuad]>;
1106 //===----------------------------------------------------------------------===//
1107 // Instructions for Thread Local Storage(TLS).
1108 //===----------------------------------------------------------------------===//
1109 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
1110 def TLS_ADDrr : F3_1<2, 0b000000,
1112 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1113 "add $rs1, $rs2, $rd, $sym",
1115 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1118 def TLS_LDrr : F3_1<3, 0b000000,
1119 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1120 "ld [$addr], $dst, $sym",
1122 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
1124 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
1125 def TLS_CALL : InstSP<(outs),
1126 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1128 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
1131 let Inst{29-0} = disp;
1135 //===----------------------------------------------------------------------===//
1137 //===----------------------------------------------------------------------===//
1139 // V9 Conditional Moves.
1140 let Predicates = [HasV9], Constraints = "$f = $rd" in {
1141 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
1142 let Uses = [ICC], intcc = 1, cc = 0b00 in {
1144 : F4_1<0b101100, (outs IntRegs:$rd),
1145 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1146 "mov$cond %icc, $rs2, $rd",
1147 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1150 : F4_2<0b101100, (outs IntRegs:$rd),
1151 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1152 "mov$cond %icc, $simm11, $rd",
1154 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1157 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1159 : F4_1<0b101100, (outs IntRegs:$rd),
1160 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1161 "mov$cond %fcc0, $rs2, $rd",
1162 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1164 : F4_2<0b101100, (outs IntRegs:$rd),
1165 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1166 "mov$cond %fcc0, $simm11, $rd",
1168 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1171 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
1173 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1174 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1175 "fmovs$cond %icc, $rs2, $rd",
1176 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1178 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1179 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1180 "fmovd$cond %icc, $rs2, $rd",
1181 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1183 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1184 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1185 "fmovq$cond %icc, $rs2, $rd",
1186 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1187 Requires<[HasHardQuad]>;
1190 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
1192 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1193 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1194 "fmovs$cond %fcc0, $rs2, $rd",
1195 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1197 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1198 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1199 "fmovd$cond %fcc0, $rs2, $rd",
1200 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1202 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1203 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1204 "fmovq$cond %fcc0, $rs2, $rd",
1205 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1206 Requires<[HasHardQuad]>;
1211 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1212 let Predicates = [HasV9] in {
1213 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1214 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1215 "fmovd $rs2, $rd", []>;
1216 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1217 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1218 "fmovq $rs2, $rd", []>,
1219 Requires<[HasHardQuad]>;
1220 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1221 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1223 [(set f64:$rd, (fneg f64:$rs2))]>;
1224 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1225 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1227 [(set f128:$rd, (fneg f128:$rs2))]>,
1228 Requires<[HasHardQuad]>;
1229 def FABSD : F3_3u<2, 0b110100, 0b000001010,
1230 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1232 [(set f64:$rd, (fabs f64:$rs2))]>;
1233 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1234 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1236 [(set f128:$rd, (fabs f128:$rs2))]>,
1237 Requires<[HasHardQuad]>;
1240 // Floating-point compare instruction with %fcc0-%fcc3.
1241 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
1242 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1243 "fcmps $rd, $rs1, $rs2", []>;
1244 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
1245 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1246 "fcmpd $rd, $rs1, $rs2", []>;
1247 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1248 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1249 "fcmpq $rd, $rs1, $rs2", []>,
1250 Requires<[HasHardQuad]>;
1252 let hasSideEffects = 1 in {
1253 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
1254 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1255 "fcmpes $rd, $rs1, $rs2", []>;
1256 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
1257 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1258 "fcmped $rd, $rs1, $rs2", []>;
1259 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
1260 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1261 "fcmpeq $rd, $rs1, $rs2", []>,
1262 Requires<[HasHardQuad]>;
1265 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1266 let Predicates = [HasV9] in {
1267 let Constraints = "$f = $rd", intcc = 0 in {
1269 : F4_1<0b101100, (outs IntRegs:$rd),
1270 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1271 "mov$cond $cc, $rs2, $rd", []>;
1273 : F4_2<0b101100, (outs IntRegs:$rd),
1274 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1275 "mov$cond $cc, $simm11, $rd", []>;
1277 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1278 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1279 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1281 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1282 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1283 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1285 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1286 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1287 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1288 Requires<[HasHardQuad]>;
1289 } // Constraints = "$f = $rd", ...
1290 } // let Predicates = [hasV9]
1293 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1294 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1296 def POPCrr : F3_1<2, 0b101110,
1297 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1298 "popc $rs2, $rd", []>, Requires<[HasV9]>;
1299 def : Pat<(ctpop i32:$src),
1300 (POPCrr (SRLri $src, 0))>;
1302 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1303 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1304 "membar $simm13", []>;
1306 // TODO: Should add a CASArr variant. In fact, the CAS instruction,
1307 // unlike other instructions, only comes in a form which requires an
1308 // ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
1309 // default unprivileged ASI for SparcV9. (Also of note: some modern
1310 // SparcV8 implementations provide CASA as an extension, but require
1311 // the use of SparcV8's default ASI, 0xA ("User Data") instead.)
1312 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1313 def CASrr: F3_1_asi<3, 0b111100,
1314 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1316 "cas [$rs1], $rs2, $rd",
1318 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1320 let Defs = [ICC] in {
1321 defm TADDCC : F3_12np<"taddcc", 0b100000>;
1322 defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
1324 let hasSideEffects = 1 in {
1325 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1326 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1330 //===----------------------------------------------------------------------===//
1331 // Non-Instruction Patterns
1332 //===----------------------------------------------------------------------===//
1334 // Small immediates.
1335 def : Pat<(i32 simm13:$val),
1336 (ORri (i32 G0), imm:$val)>;
1337 // Arbitrary immediates.
1338 def : Pat<(i32 imm:$val),
1339 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1342 // Global addresses, constant pool entries
1343 let Predicates = [Is32Bit] in {
1345 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1346 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1347 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1348 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1350 // GlobalTLS addresses
1351 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1352 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1353 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1354 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1355 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1356 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1359 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1360 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1362 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1363 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1364 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1365 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1366 (ADDri $r, tblockaddress:$in)>;
1370 def : Pat<(call tglobaladdr:$dst),
1371 (CALL tglobaladdr:$dst)>;
1372 def : Pat<(call texternalsym:$dst),
1373 (CALL texternalsym:$dst)>;
1375 // Map integer extload's to zextloads.
1376 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1377 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1378 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1379 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1380 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1381 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1383 // zextload bool -> zextload byte
1384 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1385 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1387 // store 0, addr -> store %g0, addr
1388 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1389 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1391 // store bar for all atomic_fence in V8.
1392 let Predicates = [HasNoV9] in
1393 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1395 // atomic_load_32 addr -> load addr
1396 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1397 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1399 // atomic_store_32 val, addr -> store val, addr
1400 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1401 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1404 def : Pat<(vector_extract (v2i32 IntPair:$Rn), 0),
1405 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
1406 def : Pat<(vector_extract (v2i32 IntPair:$Rn), 1),
1407 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
1410 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1412 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1413 (i32 IntRegs:$a2), sub_odd)>;
1416 include "SparcInstr64Bit.td"
1417 include "SparcInstrVIS.td"
1418 include "SparcInstrAliases.td"