1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 def LO10 : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
46 def HI22 : SDNodeXForm<imm, [{
47 // Transformation function: shift the immediate value down into the low bits.
48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
51 def SETHIimm : PatLeaf<(imm), [{
52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
56 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
57 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
60 def MEMrr : Operand<i32> {
61 let PrintMethod = "printMemOperand";
62 let NumMIOperands = 2;
63 let MIOperandInfo = (ops IntRegs, IntRegs);
65 def MEMri : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let NumMIOperands = 2;
68 let MIOperandInfo = (ops IntRegs, i32imm);
71 //===----------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
75 // Pseudo instructions.
76 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
77 let AsmString = asmstr;
78 dag OperandList = ops;
80 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
81 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
83 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
85 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
86 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
88 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
90 // Section A.3 - Synthetic Instructions, p. 85
91 // special cases of JMPL:
92 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
93 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
94 def RET : F3_2<2, 0b111000,
95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
96 "ret $b, $c, $dst", []>;
97 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
98 def RETL: F3_2<2, 0b111000, (ops),
101 // CMP is a special case of SUBCC where destination is ignored, by setting it to
102 // %g0 (hardwired zero).
103 // FIXME: should keep track of the fact that it defs the integer condition codes
105 def CMPri: F3_2<2, 0b010100,
106 (ops IntRegs:$b, i32imm:$c),
109 // Section B.1 - Load Integer Instructions, p. 90
110 def LDSBrr : F3_1<3, 0b001001,
111 (ops IntRegs:$dst, MEMrr:$addr),
112 "ldsb [$addr], $dst",
113 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
114 def LDSBri : F3_2<3, 0b001001,
115 (ops IntRegs:$dst, MEMri:$addr),
116 "ldsb [$addr], $dst",
117 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
118 def LDSHrr : F3_1<3, 0b001010,
119 (ops IntRegs:$dst, MEMrr:$addr),
120 "ldsh [$addr], $dst",
121 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
122 def LDSHri : F3_2<3, 0b001010,
123 (ops IntRegs:$dst, MEMri:$addr),
124 "ldsh [$addr], $dst",
125 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
126 def LDUBrr : F3_1<3, 0b000001,
127 (ops IntRegs:$dst, MEMrr:$addr),
128 "ldub [$addr], $dst",
129 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
130 def LDUBri : F3_2<3, 0b000001,
131 (ops IntRegs:$dst, MEMri:$addr),
132 "ldub [$addr], $dst",
133 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
134 def LDUHrr : F3_1<3, 0b000010,
135 (ops IntRegs:$dst, MEMrr:$addr),
136 "lduh [$addr], $dst",
137 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
138 def LDUHri : F3_2<3, 0b000010,
139 (ops IntRegs:$dst, MEMri:$addr),
140 "lduh [$addr], $dst",
141 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
142 def LDrr : F3_1<3, 0b000000,
143 (ops IntRegs:$dst, MEMrr:$addr),
145 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
146 def LDri : F3_2<3, 0b000000,
147 (ops IntRegs:$dst, MEMri:$addr),
149 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
150 def LDDrr : F3_1<3, 0b000011,
151 (ops IntRegs:$dst, MEMrr:$addr),
152 "ldd [$addr], $dst", []>;
153 def LDDri : F3_2<3, 0b000011,
154 (ops IntRegs:$dst, MEMri:$addr),
155 "ldd [$addr], $dst", []>;
157 // Section B.2 - Load Floating-point Instructions, p. 92
158 def LDFrr : F3_1<3, 0b100000,
159 (ops FPRegs:$dst, MEMrr:$addr),
161 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
162 def LDFri : F3_2<3, 0b100000,
163 (ops FPRegs:$dst, MEMri:$addr),
165 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
166 def LDDFrr : F3_1<3, 0b100011,
167 (ops DFPRegs:$dst, MEMrr:$addr),
169 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
170 def LDDFri : F3_2<3, 0b100011,
171 (ops DFPRegs:$dst, MEMri:$addr),
173 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
175 // Section B.4 - Store Integer Instructions, p. 95
176 def STBrr : F3_1<3, 0b000101,
177 (ops MEMrr:$addr, IntRegs:$src),
179 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
180 def STBri : F3_2<3, 0b000101,
181 (ops MEMri:$addr, IntRegs:$src),
183 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
184 def STHrr : F3_1<3, 0b000110,
185 (ops MEMrr:$addr, IntRegs:$src),
187 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
188 def STHri : F3_2<3, 0b000110,
189 (ops MEMri:$addr, IntRegs:$src),
191 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
192 def STrr : F3_1<3, 0b000100,
193 (ops MEMrr:$addr, IntRegs:$src),
195 [(store IntRegs:$src, ADDRrr:$addr)]>;
196 def STri : F3_2<3, 0b000100,
197 (ops MEMri:$addr, IntRegs:$src),
199 [(store IntRegs:$src, ADDRri:$addr)]>;
200 def STDrr : F3_1<3, 0b000111,
201 (ops MEMrr:$addr, IntRegs:$src),
202 "std $src, [$addr]", []>;
203 def STDri : F3_2<3, 0b000111,
204 (ops MEMri:$addr, IntRegs:$src),
205 "std $src, [$addr]", []>;
207 // Section B.5 - Store Floating-point Instructions, p. 97
208 def STFrr : F3_1<3, 0b100100,
209 (ops MEMrr:$addr, FPRegs:$src),
211 [(store FPRegs:$src, ADDRrr:$addr)]>;
212 def STFri : F3_2<3, 0b100100,
213 (ops MEMri:$addr, FPRegs:$src),
215 [(store FPRegs:$src, ADDRri:$addr)]>;
216 def STDFrr : F3_1<3, 0b100111,
217 (ops MEMrr:$addr, DFPRegs:$src),
219 [(store DFPRegs:$src, ADDRrr:$addr)]>;
220 def STDFri : F3_2<3, 0b100111,
221 (ops MEMri:$addr, DFPRegs:$src),
223 [(store DFPRegs:$src, ADDRri:$addr)]>;
225 // Section B.9 - SETHI Instruction, p. 104
226 def SETHIi: F2_1<0b100,
227 (ops IntRegs:$dst, i32imm:$src),
229 [(set IntRegs:$dst, SETHIimm:$src)]>;
231 // Section B.10 - NOP Instruction, p. 105
232 // (It's a special case of SETHI)
233 let rd = 0, imm22 = 0 in
234 def NOP : F2_1<0b100, (ops), "nop", []>;
236 // Section B.11 - Logical Instructions, p. 106
237 def ANDrr : F3_1<2, 0b000001,
238 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
240 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
241 def ANDri : F3_2<2, 0b000001,
242 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
244 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
245 def ANDCCrr : F3_1<2, 0b010001,
246 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
247 "andcc $b, $c, $dst", []>;
248 def ANDCCri : F3_2<2, 0b010001,
249 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
250 "andcc $b, $c, $dst", []>;
251 def ANDNrr : F3_1<2, 0b000101,
252 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
254 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
255 def ANDNri : F3_2<2, 0b000101,
256 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
257 "andn $b, $c, $dst", []>;
258 def ANDNCCrr: F3_1<2, 0b010101,
259 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
260 "andncc $b, $c, $dst", []>;
261 def ANDNCCri: F3_2<2, 0b010101,
262 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
263 "andncc $b, $c, $dst", []>;
264 def ORrr : F3_1<2, 0b000010,
265 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
267 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
268 def ORri : F3_2<2, 0b000010,
269 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
271 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
272 def ORCCrr : F3_1<2, 0b010010,
273 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
274 "orcc $b, $c, $dst", []>;
275 def ORCCri : F3_2<2, 0b010010,
276 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
277 "orcc $b, $c, $dst", []>;
278 def ORNrr : F3_1<2, 0b000110,
279 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
281 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
282 def ORNri : F3_2<2, 0b000110,
283 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
284 "orn $b, $c, $dst", []>;
285 def ORNCCrr : F3_1<2, 0b010110,
286 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
287 "orncc $b, $c, $dst", []>;
288 def ORNCCri : F3_2<2, 0b010110,
289 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
290 "orncc $b, $c, $dst", []>;
291 def XORrr : F3_1<2, 0b000011,
292 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
294 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
295 def XORri : F3_2<2, 0b000011,
296 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
298 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
299 def XORCCrr : F3_1<2, 0b010011,
300 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
301 "xorcc $b, $c, $dst", []>;
302 def XORCCri : F3_2<2, 0b010011,
303 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
304 "xorcc $b, $c, $dst", []>;
305 def XNORrr : F3_1<2, 0b000111,
306 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
308 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
309 def XNORri : F3_2<2, 0b000111,
310 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
311 "xnor $b, $c, $dst", []>;
312 def XNORCCrr: F3_1<2, 0b010111,
313 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
314 "xnorcc $b, $c, $dst", []>;
315 def XNORCCri: F3_2<2, 0b010111,
316 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
317 "xnorcc $b, $c, $dst", []>;
319 // Section B.12 - Shift Instructions, p. 107
320 def SLLrr : F3_1<2, 0b100101,
321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
323 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
324 def SLLri : F3_2<2, 0b100101,
325 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
327 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
328 def SRLrr : F3_1<2, 0b100110,
329 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
331 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
332 def SRLri : F3_2<2, 0b100110,
333 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
335 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
336 def SRArr : F3_1<2, 0b100111,
337 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
339 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
340 def SRAri : F3_2<2, 0b100111,
341 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
343 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
345 // Section B.13 - Add Instructions, p. 108
346 def ADDrr : F3_1<2, 0b000000,
347 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
349 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
350 def ADDri : F3_2<2, 0b000000,
351 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
353 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
354 def ADDCCrr : F3_1<2, 0b010000,
355 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
356 "addcc $b, $c, $dst", []>;
357 def ADDCCri : F3_2<2, 0b010000,
358 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
359 "addcc $b, $c, $dst", []>;
360 def ADDXrr : F3_1<2, 0b001000,
361 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
362 "addx $b, $c, $dst", []>;
363 def ADDXri : F3_2<2, 0b001000,
364 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
365 "addx $b, $c, $dst", []>;
366 def ADDXCCrr: F3_1<2, 0b011000,
367 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
368 "addxcc $b, $c, $dst", []>;
369 def ADDXCCri: F3_2<2, 0b011000,
370 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
371 "addxcc $b, $c, $dst", []>;
373 // Section B.15 - Subtract Instructions, p. 110
374 def SUBrr : F3_1<2, 0b000100,
375 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
377 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
378 def SUBri : F3_2<2, 0b000100,
379 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
381 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
382 def SUBCCrr : F3_1<2, 0b010100,
383 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
384 "subcc $b, $c, $dst", []>;
385 def SUBCCri : F3_2<2, 0b010100,
386 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
387 "subcc $b, $c, $dst", []>;
388 def SUBXrr : F3_1<2, 0b001100,
389 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
390 "subx $b, $c, $dst", []>;
391 def SUBXri : F3_2<2, 0b001100,
392 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
393 "subx $b, $c, $dst", []>;
394 def SUBXCCrr: F3_1<2, 0b011100,
395 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
396 "subxcc $b, $c, $dst", []>;
397 def SUBXCCri: F3_2<2, 0b011100,
398 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
399 "subxcc $b, $c, $dst", []>;
401 // Section B.18 - Multiply Instructions, p. 113
402 def UMULrr : F3_1<2, 0b001010,
403 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
404 "umul $b, $c, $dst", []>;
405 def UMULri : F3_2<2, 0b001010,
406 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
407 "umul $b, $c, $dst", []>;
408 def SMULrr : F3_1<2, 0b001011,
409 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
410 "smul $b, $c, $dst", []>;
411 def SMULri : F3_2<2, 0b001011,
412 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
413 "smul $b, $c, $dst", []>;
414 def UMULCCrr: F3_1<2, 0b011010,
415 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
416 "umulcc $b, $c, $dst", []>;
417 def UMULCCri: F3_2<2, 0b011010,
418 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
419 "umulcc $b, $c, $dst", []>;
420 def SMULCCrr: F3_1<2, 0b011011,
421 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
422 "smulcc $b, $c, $dst", []>;
423 def SMULCCri: F3_2<2, 0b011011,
424 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
425 "smulcc $b, $c, $dst", []>;
427 // Section B.19 - Divide Instructions, p. 115
428 def UDIVrr : F3_1<2, 0b001110,
429 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
430 "udiv $b, $c, $dst", []>;
431 def UDIVri : F3_2<2, 0b001110,
432 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
433 "udiv $b, $c, $dst", []>;
434 def SDIVrr : F3_1<2, 0b001111,
435 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
436 "sdiv $b, $c, $dst", []>;
437 def SDIVri : F3_2<2, 0b001111,
438 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
439 "sdiv $b, $c, $dst", []>;
440 def UDIVCCrr : F3_1<2, 0b011110,
441 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
442 "udivcc $b, $c, $dst", []>;
443 def UDIVCCri : F3_2<2, 0b011110,
444 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
445 "udivcc $b, $c, $dst", []>;
446 def SDIVCCrr : F3_1<2, 0b011111,
447 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
448 "sdivcc $b, $c, $dst", []>;
449 def SDIVCCri : F3_2<2, 0b011111,
450 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
451 "sdivcc $b, $c, $dst", []>;
453 // Section B.20 - SAVE and RESTORE, p. 117
454 def SAVErr : F3_1<2, 0b111100,
455 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
456 "save $b, $c, $dst", []>;
457 def SAVEri : F3_2<2, 0b111100,
458 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
459 "save $b, $c, $dst", []>;
460 def RESTORErr : F3_1<2, 0b111101,
461 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
462 "restore $b, $c, $dst", []>;
463 def RESTOREri : F3_2<2, 0b111101,
464 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
465 "restore $b, $c, $dst", []>;
467 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
469 // conditional branch class:
470 class BranchV8<bits<4> cc, dag ops, string asmstr>
471 : F2_2<cc, 0b010, ops, asmstr> {
473 let isTerminator = 1;
474 let hasDelaySlot = 1;
478 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
479 def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
480 def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
481 def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
482 def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
483 def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
484 def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
485 def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
486 def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
487 def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
488 def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
489 def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
491 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
493 // floating-point conditional branch class:
494 class FPBranchV8<bits<4> cc, dag ops, string asmstr>
495 : F2_2<cc, 0b110, ops, asmstr> {
497 let isTerminator = 1;
498 let hasDelaySlot = 1;
501 def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
502 def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
503 def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
504 def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
505 def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
506 def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
507 def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
508 def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
509 def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
510 def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
511 def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
512 def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
513 def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
514 def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
515 def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
516 def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
520 // Section B.24 - Call and Link Instruction, p. 125
521 // This is the only Format 1 instruction
522 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
524 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
525 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
527 let OperandList = (ops IntRegs:$dst);
530 let Inst{29-0} = disp;
531 let AsmString = "call $dst";
534 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
535 // be an implicit def):
536 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
537 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
538 def JMPLrr : F3_1<2, 0b111000,
539 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
540 "jmpl $b+$c, $dst", []>;
543 // Section B.29 - Write State Register Instructions
544 def WRrr : F3_1<2, 0b110000,
545 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
546 "wr $b, $c, $dst", []>;
547 def WRri : F3_2<2, 0b110000,
548 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
549 "wr $b, $c, $dst", []>;
551 // Convert Integer to Floating-point Instructions, p. 141
552 def FITOS : F3_3<2, 0b110100, 0b011000100,
553 (ops FPRegs:$dst, FPRegs:$src),
555 def FITOD : F3_3<2, 0b110100, 0b011001000,
556 (ops DFPRegs:$dst, DFPRegs:$src),
559 // Convert Floating-point to Integer Instructions, p. 142
560 def FSTOI : F3_3<2, 0b110100, 0b011010001,
561 (ops FPRegs:$dst, FPRegs:$src),
563 def FDTOI : F3_3<2, 0b110100, 0b011010010,
564 (ops DFPRegs:$dst, DFPRegs:$src),
567 // Convert between Floating-point Formats Instructions, p. 143
568 def FSTOD : F3_3<2, 0b110100, 0b011001001,
569 (ops DFPRegs:$dst, FPRegs:$src),
571 def FDTOS : F3_3<2, 0b110100, 0b011000110,
572 (ops FPRegs:$dst, DFPRegs:$src),
575 // Floating-point Move Instructions, p. 144
576 def FMOVS : F3_3<2, 0b110100, 0b000000001,
577 (ops FPRegs:$dst, FPRegs:$src),
579 def FNEGS : F3_3<2, 0b110100, 0b000000101,
580 (ops FPRegs:$dst, FPRegs:$src),
582 def FABSS : F3_3<2, 0b110100, 0b000001001,
583 (ops FPRegs:$dst, FPRegs:$src),
586 // Floating-point Add and Subtract Instructions, p. 146
587 def FADDS : F3_3<2, 0b110100, 0b001000001,
588 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
589 "fadds $src1, $src2, $dst">;
590 def FADDD : F3_3<2, 0b110100, 0b001000010,
591 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
592 "faddd $src1, $src2, $dst">;
593 def FSUBS : F3_3<2, 0b110100, 0b001000101,
594 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
595 "fsubs $src1, $src2, $dst">;
596 def FSUBD : F3_3<2, 0b110100, 0b001000110,
597 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
598 "fsubd $src1, $src2, $dst">;
600 // Floating-point Multiply and Divide Instructions, p. 147
601 def FMULS : F3_3<2, 0b110100, 0b001001001,
602 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
603 "fmuls $src1, $src2, $dst">;
604 def FMULD : F3_3<2, 0b110100, 0b001001010,
605 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
606 "fmuld $src1, $src2, $dst">;
607 def FSMULD : F3_3<2, 0b110100, 0b001101001,
608 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
609 "fsmuld $src1, $src2, $dst">;
610 def FDIVS : F3_3<2, 0b110100, 0b001001101,
611 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
612 "fdivs $src1, $src2, $dst">;
613 def FDIVD : F3_3<2, 0b110100, 0b001001110,
614 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
615 "fdivd $src1, $src2, $dst">;
617 // Floating-point Compare Instructions, p. 148
618 // Note: the 2nd template arg is different for these guys.
619 // Note 2: the result of a FCMP is not available until the 2nd cycle
620 // after the instr is retired, but there is no interlock. This behavior
621 // is modelled with a forced noop after the instruction.
622 def FCMPS : F3_3<2, 0b110101, 0b001010001,
623 (ops FPRegs:$src1, FPRegs:$src2),
624 "fcmps $src1, $src2\n\tnop">;
625 def FCMPD : F3_3<2, 0b110101, 0b001010010,
626 (ops DFPRegs:$src1, DFPRegs:$src2),
627 "fcmpd $src1, $src2\n\tnop">;
628 def FCMPES : F3_3<2, 0b110101, 0b001010101,
629 (ops FPRegs:$src1, FPRegs:$src2),
630 "fcmpes $src1, $src2\n\tnop">;
631 def FCMPED : F3_3<2, 0b110101, 0b001010110,
632 (ops DFPRegs:$src1, DFPRegs:$src2),
633 "fcmped $src1, $src2\n\tnop">;
635 //===----------------------------------------------------------------------===//
636 // Non-Instruction Patterns
637 //===----------------------------------------------------------------------===//
640 def : Pat<(i32 simm13:$val),
641 (ORri G0, imm:$val)>;
642 // Arbitrary immediates.
643 def : Pat<(i32 imm:$val),
644 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;