1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 def LO10 : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
46 def HI22 : SDNodeXForm<imm, [{
47 // Transformation function: shift the immediate value down into the low bits.
48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
51 def SETHIimm : PatLeaf<(imm), [{
52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
56 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
57 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
60 def MEMrr : Operand<i32> {
61 let PrintMethod = "printMemOperand";
62 let NumMIOperands = 2;
63 let MIOperandInfo = (ops IntRegs, IntRegs);
65 def MEMri : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let NumMIOperands = 2;
68 let MIOperandInfo = (ops IntRegs, i32imm);
71 //===----------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
75 // Pseudo instructions.
76 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
77 let AsmString = asmstr;
78 dag OperandList = ops;
80 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
81 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
83 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
85 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
86 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
88 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
90 // Section A.3 - Synthetic Instructions, p. 85
91 // special cases of JMPL:
92 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
93 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
94 def RET : F3_2<2, 0b111000,
95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
96 "ret $b, $c, $dst", []>;
97 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
98 def RETL: F3_2<2, 0b111000, (ops),
101 // CMP is a special case of SUBCC where destination is ignored, by setting it to
102 // %g0 (hardwired zero).
103 // FIXME: should keep track of the fact that it defs the integer condition codes
105 def CMPri: F3_2<2, 0b010100,
106 (ops IntRegs:$b, i32imm:$c),
109 // Section B.1 - Load Integer Instructions, p. 90
110 def LDSBrr : F3_1<3, 0b001001,
111 (ops IntRegs:$dst, MEMrr:$addr),
112 "ldsb [$addr], $dst",
113 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
114 def LDSBri : F3_2<3, 0b001001,
115 (ops IntRegs:$dst, MEMri:$addr),
116 "ldsb [$addr], $dst",
117 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
118 def LDSHrr : F3_1<3, 0b001010,
119 (ops IntRegs:$dst, MEMrr:$addr),
120 "ldsh [$addr], $dst",
121 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
122 def LDSHri : F3_2<3, 0b001010,
123 (ops IntRegs:$dst, MEMri:$addr),
124 "ldsh [$addr], $dst",
125 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
126 def LDUBrr : F3_1<3, 0b000001,
127 (ops IntRegs:$dst, MEMrr:$addr),
128 "ldub [$addr], $dst",
129 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
130 def LDUBri : F3_2<3, 0b000001,
131 (ops IntRegs:$dst, MEMri:$addr),
132 "ldub [$addr], $dst",
133 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
134 def LDUHrr : F3_1<3, 0b000010,
135 (ops IntRegs:$dst, MEMrr:$addr),
136 "lduh [$addr], $dst",
137 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
138 def LDUHri : F3_2<3, 0b000010,
139 (ops IntRegs:$dst, MEMri:$addr),
140 "lduh [$addr], $dst",
141 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
142 def LDrr : F3_1<3, 0b000000,
143 (ops IntRegs:$dst, MEMrr:$addr),
145 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
146 def LDri : F3_2<3, 0b000000,
147 (ops IntRegs:$dst, MEMri:$addr),
149 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
150 def LDDrr : F3_1<3, 0b000011,
151 (ops IntRegs:$dst, MEMrr:$addr),
152 "ldd [$addr], $dst", []>;
153 def LDDri : F3_2<3, 0b000011,
154 (ops IntRegs:$dst, MEMri:$addr),
155 "ldd [$addr], $dst", []>;
157 // Section B.2 - Load Floating-point Instructions, p. 92
158 def LDFrr : F3_1<3, 0b100000,
159 (ops FPRegs:$dst, MEMrr:$addr),
161 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
162 def LDFri : F3_2<3, 0b100000,
163 (ops FPRegs:$dst, MEMri:$addr),
165 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
166 def LDDFrr : F3_1<3, 0b100011,
167 (ops DFPRegs:$dst, MEMrr:$addr),
169 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
170 def LDDFri : F3_2<3, 0b100011,
171 (ops DFPRegs:$dst, MEMri:$addr),
173 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
175 // Section B.4 - Store Integer Instructions, p. 95
176 def STBrr : F3_1<3, 0b000101,
177 (ops MEMrr:$addr, IntRegs:$src),
179 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
180 def STBri : F3_2<3, 0b000101,
181 (ops MEMri:$addr, IntRegs:$src),
183 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
184 def STHrr : F3_1<3, 0b000110,
185 (ops MEMrr:$addr, IntRegs:$src),
187 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
188 def STHri : F3_2<3, 0b000110,
189 (ops MEMri:$addr, IntRegs:$src),
191 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
192 def STrr : F3_1<3, 0b000100,
193 (ops MEMrr:$addr, IntRegs:$src),
195 [(store IntRegs:$src, ADDRrr:$addr)]>;
196 def STri : F3_2<3, 0b000100,
197 (ops MEMri:$addr, IntRegs:$src),
199 [(store IntRegs:$src, ADDRri:$addr)]>;
200 def STDrr : F3_1<3, 0b000111,
201 (ops MEMrr:$addr, IntRegs:$src),
202 "std $src, [$addr]", []>;
203 def STDri : F3_2<3, 0b000111,
204 (ops MEMri:$addr, IntRegs:$src),
205 "std $src, [$addr]", []>;
207 // Section B.5 - Store Floating-point Instructions, p. 97
208 def STFrr : F3_1<3, 0b100100,
209 (ops MEMrr:$addr, FPRegs:$src),
211 [(store FPRegs:$src, ADDRrr:$addr)]>;
212 def STFri : F3_2<3, 0b100100,
213 (ops MEMri:$addr, FPRegs:$src),
215 [(store FPRegs:$src, ADDRri:$addr)]>;
216 def STDFrr : F3_1<3, 0b100111,
217 (ops MEMrr:$addr, DFPRegs:$src),
219 [(store DFPRegs:$src, ADDRrr:$addr)]>;
220 def STDFri : F3_2<3, 0b100111,
221 (ops MEMri:$addr, DFPRegs:$src),
223 [(store DFPRegs:$src, ADDRri:$addr)]>;
225 // Section B.9 - SETHI Instruction, p. 104
226 def SETHIi: F2_1<0b100,
227 (ops IntRegs:$dst, i32imm:$src),
229 [(set IntRegs:$dst, SETHIimm:$src)]>;
231 // Section B.10 - NOP Instruction, p. 105
232 // (It's a special case of SETHI)
233 let rd = 0, imm22 = 0 in
234 def NOP : F2_1<0b100, (ops), "nop", []>;
236 // Section B.11 - Logical Instructions, p. 106
237 def ANDrr : F3_1<2, 0b000001,
238 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
240 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
241 def ANDri : F3_2<2, 0b000001,
242 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
244 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
245 def ANDCCrr : F3_1<2, 0b010001,
246 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
247 "andcc $b, $c, $dst", []>;
248 def ANDCCri : F3_2<2, 0b010001,
249 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
250 "andcc $b, $c, $dst", []>;
251 def ANDNrr : F3_1<2, 0b000101,
252 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
253 "andn $b, $c, $dst", []>;
254 def ANDNri : F3_2<2, 0b000101,
255 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
256 "andn $b, $c, $dst", []>;
257 def ANDNCCrr: F3_1<2, 0b010101,
258 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
259 "andncc $b, $c, $dst", []>;
260 def ANDNCCri: F3_2<2, 0b010101,
261 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
262 "andncc $b, $c, $dst", []>;
263 def ORrr : F3_1<2, 0b000010,
264 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
266 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
267 def ORri : F3_2<2, 0b000010,
268 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
270 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
271 def ORCCrr : F3_1<2, 0b010010,
272 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
273 "orcc $b, $c, $dst", []>;
274 def ORCCri : F3_2<2, 0b010010,
275 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
276 "orcc $b, $c, $dst", []>;
277 def ORNrr : F3_1<2, 0b000110,
278 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
279 "orn $b, $c, $dst", []>;
280 def ORNri : F3_2<2, 0b000110,
281 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
282 "orn $b, $c, $dst", []>;
283 def ORNCCrr : F3_1<2, 0b010110,
284 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
285 "orncc $b, $c, $dst", []>;
286 def ORNCCri : F3_2<2, 0b010110,
287 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
288 "orncc $b, $c, $dst", []>;
289 def XORrr : F3_1<2, 0b000011,
290 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
292 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
293 def XORri : F3_2<2, 0b000011,
294 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
296 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
297 def XORCCrr : F3_1<2, 0b010011,
298 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
299 "xorcc $b, $c, $dst", []>;
300 def XORCCri : F3_2<2, 0b010011,
301 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
302 "xorcc $b, $c, $dst", []>;
303 def XNORrr : F3_1<2, 0b000111,
304 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
305 "xnor $b, $c, $dst", []>;
306 def XNORri : F3_2<2, 0b000111,
307 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
308 "xnor $b, $c, $dst", []>;
309 def XNORCCrr: F3_1<2, 0b010111,
310 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
311 "xnorcc $b, $c, $dst", []>;
312 def XNORCCri: F3_2<2, 0b010111,
313 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
314 "xnorcc $b, $c, $dst", []>;
316 // Section B.12 - Shift Instructions, p. 107
317 def SLLrr : F3_1<2, 0b100101,
318 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
320 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
321 def SLLri : F3_2<2, 0b100101,
322 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
324 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
325 def SRLrr : F3_1<2, 0b100110,
326 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
328 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
329 def SRLri : F3_2<2, 0b100110,
330 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
332 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
333 def SRArr : F3_1<2, 0b100111,
334 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
336 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
337 def SRAri : F3_2<2, 0b100111,
338 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
340 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
342 // Section B.13 - Add Instructions, p. 108
343 def ADDrr : F3_1<2, 0b000000,
344 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
346 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
347 def ADDri : F3_2<2, 0b000000,
348 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
350 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
351 def ADDCCrr : F3_1<2, 0b010000,
352 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
353 "addcc $b, $c, $dst", []>;
354 def ADDCCri : F3_2<2, 0b010000,
355 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
356 "addcc $b, $c, $dst", []>;
357 def ADDXrr : F3_1<2, 0b001000,
358 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
359 "addx $b, $c, $dst", []>;
360 def ADDXri : F3_2<2, 0b001000,
361 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
362 "addx $b, $c, $dst", []>;
363 def ADDXCCrr: F3_1<2, 0b011000,
364 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
365 "addxcc $b, $c, $dst", []>;
366 def ADDXCCri: F3_2<2, 0b011000,
367 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
368 "addxcc $b, $c, $dst", []>;
370 // Section B.15 - Subtract Instructions, p. 110
371 def SUBrr : F3_1<2, 0b000100,
372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
374 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
375 def SUBri : F3_2<2, 0b000100,
376 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
378 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
379 def SUBCCrr : F3_1<2, 0b010100,
380 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
381 "subcc $b, $c, $dst", []>;
382 def SUBCCri : F3_2<2, 0b010100,
383 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
384 "subcc $b, $c, $dst", []>;
385 def SUBXrr : F3_1<2, 0b001100,
386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
387 "subx $b, $c, $dst", []>;
388 def SUBXri : F3_2<2, 0b001100,
389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
390 "subx $b, $c, $dst", []>;
391 def SUBXCCrr: F3_1<2, 0b011100,
392 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
393 "subxcc $b, $c, $dst", []>;
394 def SUBXCCri: F3_2<2, 0b011100,
395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
396 "subxcc $b, $c, $dst", []>;
398 // Section B.18 - Multiply Instructions, p. 113
399 def UMULrr : F3_1<2, 0b001010,
400 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
401 "umul $b, $c, $dst", []>;
402 def UMULri : F3_2<2, 0b001010,
403 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
404 "umul $b, $c, $dst", []>;
405 def SMULrr : F3_1<2, 0b001011,
406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
407 "smul $b, $c, $dst", []>;
408 def SMULri : F3_2<2, 0b001011,
409 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
410 "smul $b, $c, $dst", []>;
411 def UMULCCrr: F3_1<2, 0b011010,
412 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
413 "umulcc $b, $c, $dst", []>;
414 def UMULCCri: F3_2<2, 0b011010,
415 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
416 "umulcc $b, $c, $dst", []>;
417 def SMULCCrr: F3_1<2, 0b011011,
418 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
419 "smulcc $b, $c, $dst", []>;
420 def SMULCCri: F3_2<2, 0b011011,
421 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
422 "smulcc $b, $c, $dst", []>;
424 // Section B.19 - Divide Instructions, p. 115
425 def UDIVrr : F3_1<2, 0b001110,
426 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
427 "udiv $b, $c, $dst", []>;
428 def UDIVri : F3_2<2, 0b001110,
429 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
430 "udiv $b, $c, $dst", []>;
431 def SDIVrr : F3_1<2, 0b001111,
432 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
433 "sdiv $b, $c, $dst", []>;
434 def SDIVri : F3_2<2, 0b001111,
435 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
436 "sdiv $b, $c, $dst", []>;
437 def UDIVCCrr : F3_1<2, 0b011110,
438 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
439 "udivcc $b, $c, $dst", []>;
440 def UDIVCCri : F3_2<2, 0b011110,
441 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
442 "udivcc $b, $c, $dst", []>;
443 def SDIVCCrr : F3_1<2, 0b011111,
444 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
445 "sdivcc $b, $c, $dst", []>;
446 def SDIVCCri : F3_2<2, 0b011111,
447 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
448 "sdivcc $b, $c, $dst", []>;
450 // Section B.20 - SAVE and RESTORE, p. 117
451 def SAVErr : F3_1<2, 0b111100,
452 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
453 "save $b, $c, $dst", []>;
454 def SAVEri : F3_2<2, 0b111100,
455 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
456 "save $b, $c, $dst", []>;
457 def RESTORErr : F3_1<2, 0b111101,
458 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
459 "restore $b, $c, $dst", []>;
460 def RESTOREri : F3_2<2, 0b111101,
461 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
462 "restore $b, $c, $dst", []>;
464 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
466 // conditional branch class:
467 class BranchV8<bits<4> cc, dag ops, string asmstr>
468 : F2_2<cc, 0b010, ops, asmstr> {
470 let isTerminator = 1;
471 let hasDelaySlot = 1;
475 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
476 def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
477 def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
478 def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
479 def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
480 def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
481 def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
482 def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
483 def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
484 def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
485 def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
486 def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
488 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
490 // floating-point conditional branch class:
491 class FPBranchV8<bits<4> cc, dag ops, string asmstr>
492 : F2_2<cc, 0b110, ops, asmstr> {
494 let isTerminator = 1;
495 let hasDelaySlot = 1;
498 def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
499 def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
500 def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
501 def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
502 def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
503 def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
504 def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
505 def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
506 def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
507 def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
508 def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
509 def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
510 def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
511 def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
512 def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
513 def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
517 // Section B.24 - Call and Link Instruction, p. 125
518 // This is the only Format 1 instruction
519 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
521 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
522 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
524 let OperandList = (ops IntRegs:$dst);
527 let Inst{29-0} = disp;
528 let AsmString = "call $dst";
531 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
532 // be an implicit def):
533 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
534 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
535 def JMPLrr : F3_1<2, 0b111000,
536 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
537 "jmpl $b+$c, $dst", []>;
540 // Section B.29 - Write State Register Instructions
541 def WRrr : F3_1<2, 0b110000,
542 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
543 "wr $b, $c, $dst", []>;
544 def WRri : F3_2<2, 0b110000,
545 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
546 "wr $b, $c, $dst", []>;
548 // Convert Integer to Floating-point Instructions, p. 141
549 def FITOS : F3_3<2, 0b110100, 0b011000100,
550 (ops FPRegs:$dst, FPRegs:$src),
552 def FITOD : F3_3<2, 0b110100, 0b011001000,
553 (ops DFPRegs:$dst, DFPRegs:$src),
556 // Convert Floating-point to Integer Instructions, p. 142
557 def FSTOI : F3_3<2, 0b110100, 0b011010001,
558 (ops FPRegs:$dst, FPRegs:$src),
560 def FDTOI : F3_3<2, 0b110100, 0b011010010,
561 (ops DFPRegs:$dst, DFPRegs:$src),
564 // Convert between Floating-point Formats Instructions, p. 143
565 def FSTOD : F3_3<2, 0b110100, 0b011001001,
566 (ops DFPRegs:$dst, FPRegs:$src),
568 def FDTOS : F3_3<2, 0b110100, 0b011000110,
569 (ops FPRegs:$dst, DFPRegs:$src),
572 // Floating-point Move Instructions, p. 144
573 def FMOVS : F3_3<2, 0b110100, 0b000000001,
574 (ops FPRegs:$dst, FPRegs:$src),
576 def FNEGS : F3_3<2, 0b110100, 0b000000101,
577 (ops FPRegs:$dst, FPRegs:$src),
579 def FABSS : F3_3<2, 0b110100, 0b000001001,
580 (ops FPRegs:$dst, FPRegs:$src),
583 // Floating-point Add and Subtract Instructions, p. 146
584 def FADDS : F3_3<2, 0b110100, 0b001000001,
585 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
586 "fadds $src1, $src2, $dst">;
587 def FADDD : F3_3<2, 0b110100, 0b001000010,
588 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
589 "faddd $src1, $src2, $dst">;
590 def FSUBS : F3_3<2, 0b110100, 0b001000101,
591 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
592 "fsubs $src1, $src2, $dst">;
593 def FSUBD : F3_3<2, 0b110100, 0b001000110,
594 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
595 "fsubd $src1, $src2, $dst">;
597 // Floating-point Multiply and Divide Instructions, p. 147
598 def FMULS : F3_3<2, 0b110100, 0b001001001,
599 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
600 "fmuls $src1, $src2, $dst">;
601 def FMULD : F3_3<2, 0b110100, 0b001001010,
602 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
603 "fmuld $src1, $src2, $dst">;
604 def FSMULD : F3_3<2, 0b110100, 0b001101001,
605 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
606 "fsmuld $src1, $src2, $dst">;
607 def FDIVS : F3_3<2, 0b110100, 0b001001101,
608 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
609 "fdivs $src1, $src2, $dst">;
610 def FDIVD : F3_3<2, 0b110100, 0b001001110,
611 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
612 "fdivd $src1, $src2, $dst">;
614 // Floating-point Compare Instructions, p. 148
615 // Note: the 2nd template arg is different for these guys.
616 // Note 2: the result of a FCMP is not available until the 2nd cycle
617 // after the instr is retired, but there is no interlock. This behavior
618 // is modelled with a forced noop after the instruction.
619 def FCMPS : F3_3<2, 0b110101, 0b001010001,
620 (ops FPRegs:$src1, FPRegs:$src2),
621 "fcmps $src1, $src2\n\tnop">;
622 def FCMPD : F3_3<2, 0b110101, 0b001010010,
623 (ops DFPRegs:$src1, DFPRegs:$src2),
624 "fcmpd $src1, $src2\n\tnop">;
625 def FCMPES : F3_3<2, 0b110101, 0b001010101,
626 (ops FPRegs:$src1, FPRegs:$src2),
627 "fcmpes $src1, $src2\n\tnop">;
628 def FCMPED : F3_3<2, 0b110101, 0b001010110,
629 (ops DFPRegs:$src1, DFPRegs:$src2),
630 "fcmped $src1, $src2\n\tnop">;
632 //===----------------------------------------------------------------------===//
633 // Non-Instruction Patterns
634 //===----------------------------------------------------------------------===//
637 def : Pat<(i32 simm13:$val),
638 (ORri G0, imm:$val)>;
639 // Arbitrary immediates.
640 def : Pat<(i32 imm:$val),
641 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;