1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcV8InstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Instruction Pattern Stuff
22 //===----------------------------------------------------------------------===//
24 def simm13 : PatLeaf<(imm), [{
25 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
26 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
29 def LO10 : SDNodeXForm<imm, [{
30 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
33 def HI22 : SDNodeXForm<imm, [{
34 // Transformation function: shift the immediate value down into the low bits.
35 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
38 def SETHIimm : PatLeaf<(imm), [{
39 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
43 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
44 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
47 def MEMrr : Operand<i32> {
48 let PrintMethod = "printMemOperand";
49 let NumMIOperands = 2;
50 let MIOperandInfo = (ops IntRegs, IntRegs);
52 def MEMri : Operand<i32> {
53 let PrintMethod = "printMemOperand";
54 let NumMIOperands = 2;
55 let MIOperandInfo = (ops IntRegs, i32imm);
58 // Branch targets have OtherVT type.
59 def brtarget : Operand<OtherVT>;
60 def calltarget : Operand<i32>;
63 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
65 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
67 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
68 SDTCisVT<2, FlagVT>]>;
70 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
71 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
73 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
75 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
77 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
78 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
79 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
80 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
82 def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
83 def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
85 def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
86 def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
88 def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
89 def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
91 // These are target-independent nodes, but have target-specific formats.
92 def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
93 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
94 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
96 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
97 def call : SDNode<"ISD::CALL", SDT_V8Call,
98 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
100 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
101 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
102 [SDNPHasChain, SDNPOptInFlag]>;
104 //===----------------------------------------------------------------------===//
106 //===----------------------------------------------------------------------===//
108 // Pseudo instructions.
109 class Pseudo<dag ops, string asmstr, list<dag> pattern>
110 : InstV8<ops, asmstr, pattern>;
112 def PHI : Pseudo<(ops variable_ops), "PHI", []>;
113 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
114 "!ADJCALLSTACKDOWN $amt",
115 [(callseq_start imm:$amt)]>;
116 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
117 "!ADJCALLSTACKUP $amt",
118 [(callseq_end imm:$amt)]>;
119 def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
120 "!IMPLICIT_DEF $dst",
121 [(set IntRegs:$dst, (undef))]>;
122 def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
123 [(set FPRegs:$dst, (undef))]>;
124 def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
125 [(set DFPRegs:$dst, (undef))]>;
127 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
129 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
130 "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move
131 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
132 "!FpNEGD $src, $dst",
133 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
134 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
135 "!FpABSD $src, $dst",
136 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
138 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
139 // scheduler into a branch sequence. This has to handle all permutations of
140 // selection between i32/f32/f64 on ICC and FCC.
141 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
142 def SELECT_CC_Int_ICC
143 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
144 "; SELECT_CC_Int_ICC PSEUDO!",
145 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
147 def SELECT_CC_Int_FCC
148 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
149 "; SELECT_CC_Int_FCC PSEUDO!",
150 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
153 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
154 "; SELECT_CC_FP_ICC PSEUDO!",
155 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
158 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
159 "; SELECT_CC_FP_FCC PSEUDO!",
160 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
162 def SELECT_CC_DFP_ICC
163 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
164 "; SELECT_CC_DFP_ICC PSEUDO!",
165 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
167 def SELECT_CC_DFP_FCC
168 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
169 "; SELECT_CC_DFP_FCC PSEUDO!",
170 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
174 // Section A.3 - Synthetic Instructions, p. 85
175 // special cases of JMPL:
176 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
177 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
178 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
181 // Section B.1 - Load Integer Instructions, p. 90
182 def LDSBrr : F3_1<3, 0b001001,
183 (ops IntRegs:$dst, MEMrr:$addr),
184 "ldsb [$addr], $dst",
185 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
186 def LDSBri : F3_2<3, 0b001001,
187 (ops IntRegs:$dst, MEMri:$addr),
188 "ldsb [$addr], $dst",
189 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
190 def LDSHrr : F3_1<3, 0b001010,
191 (ops IntRegs:$dst, MEMrr:$addr),
192 "ldsh [$addr], $dst",
193 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
194 def LDSHri : F3_2<3, 0b001010,
195 (ops IntRegs:$dst, MEMri:$addr),
196 "ldsh [$addr], $dst",
197 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
198 def LDUBrr : F3_1<3, 0b000001,
199 (ops IntRegs:$dst, MEMrr:$addr),
200 "ldub [$addr], $dst",
201 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
202 def LDUBri : F3_2<3, 0b000001,
203 (ops IntRegs:$dst, MEMri:$addr),
204 "ldub [$addr], $dst",
205 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
206 def LDUHrr : F3_1<3, 0b000010,
207 (ops IntRegs:$dst, MEMrr:$addr),
208 "lduh [$addr], $dst",
209 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
210 def LDUHri : F3_2<3, 0b000010,
211 (ops IntRegs:$dst, MEMri:$addr),
212 "lduh [$addr], $dst",
213 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
214 def LDrr : F3_1<3, 0b000000,
215 (ops IntRegs:$dst, MEMrr:$addr),
217 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
218 def LDri : F3_2<3, 0b000000,
219 (ops IntRegs:$dst, MEMri:$addr),
221 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
223 // Section B.2 - Load Floating-point Instructions, p. 92
224 def LDFrr : F3_1<3, 0b100000,
225 (ops FPRegs:$dst, MEMrr:$addr),
227 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
228 def LDFri : F3_2<3, 0b100000,
229 (ops FPRegs:$dst, MEMri:$addr),
231 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
232 def LDDFrr : F3_1<3, 0b100011,
233 (ops DFPRegs:$dst, MEMrr:$addr),
235 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
236 def LDDFri : F3_2<3, 0b100011,
237 (ops DFPRegs:$dst, MEMri:$addr),
239 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
241 // Section B.4 - Store Integer Instructions, p. 95
242 def STBrr : F3_1<3, 0b000101,
243 (ops MEMrr:$addr, IntRegs:$src),
245 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
246 def STBri : F3_2<3, 0b000101,
247 (ops MEMri:$addr, IntRegs:$src),
249 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
250 def STHrr : F3_1<3, 0b000110,
251 (ops MEMrr:$addr, IntRegs:$src),
253 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
254 def STHri : F3_2<3, 0b000110,
255 (ops MEMri:$addr, IntRegs:$src),
257 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
258 def STrr : F3_1<3, 0b000100,
259 (ops MEMrr:$addr, IntRegs:$src),
261 [(store IntRegs:$src, ADDRrr:$addr)]>;
262 def STri : F3_2<3, 0b000100,
263 (ops MEMri:$addr, IntRegs:$src),
265 [(store IntRegs:$src, ADDRri:$addr)]>;
267 // Section B.5 - Store Floating-point Instructions, p. 97
268 def STFrr : F3_1<3, 0b100100,
269 (ops MEMrr:$addr, FPRegs:$src),
271 [(store FPRegs:$src, ADDRrr:$addr)]>;
272 def STFri : F3_2<3, 0b100100,
273 (ops MEMri:$addr, FPRegs:$src),
275 [(store FPRegs:$src, ADDRri:$addr)]>;
276 def STDFrr : F3_1<3, 0b100111,
277 (ops MEMrr:$addr, DFPRegs:$src),
279 [(store DFPRegs:$src, ADDRrr:$addr)]>;
280 def STDFri : F3_2<3, 0b100111,
281 (ops MEMri:$addr, DFPRegs:$src),
283 [(store DFPRegs:$src, ADDRri:$addr)]>;
285 // Section B.9 - SETHI Instruction, p. 104
286 def SETHIi: F2_1<0b100,
287 (ops IntRegs:$dst, i32imm:$src),
289 [(set IntRegs:$dst, SETHIimm:$src)]>;
291 // Section B.10 - NOP Instruction, p. 105
292 // (It's a special case of SETHI)
293 let rd = 0, imm22 = 0 in
294 def NOP : F2_1<0b100, (ops), "nop", []>;
296 // Section B.11 - Logical Instructions, p. 106
297 def ANDrr : F3_1<2, 0b000001,
298 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
300 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
301 def ANDri : F3_2<2, 0b000001,
302 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
304 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
305 def ANDNrr : F3_1<2, 0b000101,
306 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
308 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
309 def ANDNri : F3_2<2, 0b000101,
310 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
311 "andn $b, $c, $dst", []>;
312 def ORrr : F3_1<2, 0b000010,
313 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
315 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
316 def ORri : F3_2<2, 0b000010,
317 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
319 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
320 def ORNrr : F3_1<2, 0b000110,
321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
323 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
324 def ORNri : F3_2<2, 0b000110,
325 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
326 "orn $b, $c, $dst", []>;
327 def XORrr : F3_1<2, 0b000011,
328 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
330 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
331 def XORri : F3_2<2, 0b000011,
332 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
334 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
335 def XNORrr : F3_1<2, 0b000111,
336 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
338 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
339 def XNORri : F3_2<2, 0b000111,
340 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
341 "xnor $b, $c, $dst", []>;
343 // Section B.12 - Shift Instructions, p. 107
344 def SLLrr : F3_1<2, 0b100101,
345 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
347 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
348 def SLLri : F3_2<2, 0b100101,
349 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
351 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
352 def SRLrr : F3_1<2, 0b100110,
353 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
355 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
356 def SRLri : F3_2<2, 0b100110,
357 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
359 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
360 def SRArr : F3_1<2, 0b100111,
361 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
363 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
364 def SRAri : F3_2<2, 0b100111,
365 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
367 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
369 // Section B.13 - Add Instructions, p. 108
370 def ADDrr : F3_1<2, 0b000000,
371 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
373 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
374 def ADDri : F3_2<2, 0b000000,
375 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
377 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
378 def ADDCCrr : F3_1<2, 0b010000,
379 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
380 "addcc $b, $c, $dst", []>;
381 def ADDCCri : F3_2<2, 0b010000,
382 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
383 "addcc $b, $c, $dst", []>;
384 def ADDXrr : F3_1<2, 0b001000,
385 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
386 "addx $b, $c, $dst", []>;
387 def ADDXri : F3_2<2, 0b001000,
388 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
389 "addx $b, $c, $dst", []>;
391 // Section B.15 - Subtract Instructions, p. 110
392 def SUBrr : F3_1<2, 0b000100,
393 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
395 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
396 def SUBri : F3_2<2, 0b000100,
397 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
399 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
400 def SUBXrr : F3_1<2, 0b001100,
401 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
402 "subx $b, $c, $dst", []>;
403 def SUBXri : F3_2<2, 0b001100,
404 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
405 "subx $b, $c, $dst", []>;
406 def SUBCCrr : F3_1<2, 0b010100,
407 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
408 "subcc $b, $c, $dst", []>;
409 def SUBCCri : F3_2<2, 0b010100,
410 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
411 "subcc $b, $c, $dst", []>;
412 def SUBXCCrr: F3_1<2, 0b011100,
413 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
414 "subxcc $b, $c, $dst", []>;
416 // Section B.18 - Multiply Instructions, p. 113
417 def UMULrr : F3_1<2, 0b001010,
418 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
419 "umul $b, $c, $dst", []>;
420 def UMULri : F3_2<2, 0b001010,
421 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
422 "umul $b, $c, $dst", []>;
423 def SMULrr : F3_1<2, 0b001011,
424 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
426 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
427 def SMULri : F3_2<2, 0b001011,
428 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
430 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
432 // Section B.19 - Divide Instructions, p. 115
433 def UDIVrr : F3_1<2, 0b001110,
434 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
435 "udiv $b, $c, $dst", []>;
436 def UDIVri : F3_2<2, 0b001110,
437 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
438 "udiv $b, $c, $dst", []>;
439 def SDIVrr : F3_1<2, 0b001111,
440 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
441 "sdiv $b, $c, $dst", []>;
442 def SDIVri : F3_2<2, 0b001111,
443 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
444 "sdiv $b, $c, $dst", []>;
446 // Section B.20 - SAVE and RESTORE, p. 117
447 def SAVErr : F3_1<2, 0b111100,
448 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
449 "save $b, $c, $dst", []>;
450 def SAVEri : F3_2<2, 0b111100,
451 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
452 "save $b, $c, $dst", []>;
453 def RESTORErr : F3_1<2, 0b111101,
454 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
455 "restore $b, $c, $dst", []>;
456 def RESTOREri : F3_2<2, 0b111101,
457 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
458 "restore $b, $c, $dst", []>;
460 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
462 // conditional branch class:
463 class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
464 : F2_2<cc, 0b010, ops, asmstr, pattern> {
466 let isTerminator = 1;
467 let hasDelaySlot = 1;
472 def BA : BranchV8<0b1000, (ops brtarget:$dst),
475 def BNE : BranchV8<0b1001, (ops brtarget:$dst),
477 [(V8bricc bb:$dst, SETNE, ICC)]>;
478 def BE : BranchV8<0b0001, (ops brtarget:$dst),
480 [(V8bricc bb:$dst, SETEQ, ICC)]>;
481 def BG : BranchV8<0b1010, (ops brtarget:$dst),
483 [(V8bricc bb:$dst, SETGT, ICC)]>;
484 def BLE : BranchV8<0b0010, (ops brtarget:$dst),
486 [(V8bricc bb:$dst, SETLE, ICC)]>;
487 def BGE : BranchV8<0b1011, (ops brtarget:$dst),
489 [(V8bricc bb:$dst, SETGE, ICC)]>;
490 def BL : BranchV8<0b0011, (ops brtarget:$dst),
492 [(V8bricc bb:$dst, SETLT, ICC)]>;
493 def BGU : BranchV8<0b1100, (ops brtarget:$dst),
495 [(V8bricc bb:$dst, SETUGT, ICC)]>;
496 def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
498 [(V8bricc bb:$dst, SETULE, ICC)]>;
499 def BCC : BranchV8<0b1101, (ops brtarget:$dst),
501 [(V8bricc bb:$dst, SETUGE, ICC)]>;
502 def BCS : BranchV8<0b0101, (ops brtarget:$dst),
504 [(V8bricc bb:$dst, SETULT, ICC)]>;
506 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
508 // floating-point conditional branch class:
509 class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
510 : F2_2<cc, 0b110, ops, asmstr, pattern> {
512 let isTerminator = 1;
513 let hasDelaySlot = 1;
517 def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
519 [(V8brfcc bb:$dst, SETUO, FCC)]>;
520 def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
522 [(V8brfcc bb:$dst, SETGT, FCC)]>;
523 def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
525 [(V8brfcc bb:$dst, SETUGT, FCC)]>;
526 def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
528 [(V8brfcc bb:$dst, SETLT, FCC)]>;
529 def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
531 [(V8brfcc bb:$dst, SETULT, FCC)]>;
532 def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
534 [(V8brfcc bb:$dst, SETONE, FCC)]>;
535 def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
537 [(V8brfcc bb:$dst, SETNE, FCC)]>;
538 def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
540 [(V8brfcc bb:$dst, SETEQ, FCC)]>;
541 def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
543 [(V8brfcc bb:$dst, SETUEQ, FCC)]>;
544 def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
546 [(V8brfcc bb:$dst, SETGE, FCC)]>;
547 def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
549 [(V8brfcc bb:$dst, SETUGE, FCC)]>;
550 def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
552 [(V8brfcc bb:$dst, SETLE, FCC)]>;
553 def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
555 [(V8brfcc bb:$dst, SETULE, FCC)]>;
556 def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
558 [(V8brfcc bb:$dst, SETO, FCC)]>;
562 // Section B.24 - Call and Link Instruction, p. 125
563 // This is the only Format 1 instruction
564 let Uses = [O0, O1, O2, O3, O4, O5],
565 hasDelaySlot = 1, isCall = 1, noResults = 1,
566 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
567 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
568 def CALL : InstV8<(ops calltarget:$dst),
572 let Inst{29-0} = disp;
576 def JMPLrr : F3_1<2, 0b111000,
579 [(call ADDRrr:$ptr)]>;
580 def JMPLri : F3_2<2, 0b111000,
583 [(call ADDRri:$ptr)]>;
586 // Section B.28 - Read State Register Instructions
587 def RDY : F3_1<2, 0b101000,
591 // Section B.29 - Write State Register Instructions
592 def WRYrr : F3_1<2, 0b110000,
593 (ops IntRegs:$b, IntRegs:$c),
594 "wr $b, $c, %y", []>;
595 def WRYri : F3_2<2, 0b110000,
596 (ops IntRegs:$b, i32imm:$c),
597 "wr $b, $c, %y", []>;
599 // Convert Integer to Floating-point Instructions, p. 141
600 def FITOS : F3_3<2, 0b110100, 0b011000100,
601 (ops FPRegs:$dst, FPRegs:$src),
603 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
604 def FITOD : F3_3<2, 0b110100, 0b011001000,
605 (ops DFPRegs:$dst, FPRegs:$src),
607 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
609 // Convert Floating-point to Integer Instructions, p. 142
610 def FSTOI : F3_3<2, 0b110100, 0b011010001,
611 (ops FPRegs:$dst, FPRegs:$src),
613 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
614 def FDTOI : F3_3<2, 0b110100, 0b011010010,
615 (ops FPRegs:$dst, DFPRegs:$src),
617 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
619 // Convert between Floating-point Formats Instructions, p. 143
620 def FSTOD : F3_3<2, 0b110100, 0b011001001,
621 (ops DFPRegs:$dst, FPRegs:$src),
623 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
624 def FDTOS : F3_3<2, 0b110100, 0b011000110,
625 (ops FPRegs:$dst, DFPRegs:$src),
627 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
629 // Floating-point Move Instructions, p. 144
630 def FMOVS : F3_3<2, 0b110100, 0b000000001,
631 (ops FPRegs:$dst, FPRegs:$src),
632 "fmovs $src, $dst", []>;
633 def FNEGS : F3_3<2, 0b110100, 0b000000101,
634 (ops FPRegs:$dst, FPRegs:$src),
636 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
637 def FABSS : F3_3<2, 0b110100, 0b000001001,
638 (ops FPRegs:$dst, FPRegs:$src),
640 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
643 // Floating-point Square Root Instructions, p.145
644 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
645 (ops FPRegs:$dst, FPRegs:$src),
647 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
648 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
649 (ops DFPRegs:$dst, DFPRegs:$src),
651 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
655 // Floating-point Add and Subtract Instructions, p. 146
656 def FADDS : F3_3<2, 0b110100, 0b001000001,
657 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
658 "fadds $src1, $src2, $dst",
659 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
660 def FADDD : F3_3<2, 0b110100, 0b001000010,
661 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
662 "faddd $src1, $src2, $dst",
663 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
664 def FSUBS : F3_3<2, 0b110100, 0b001000101,
665 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
666 "fsubs $src1, $src2, $dst",
667 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
668 def FSUBD : F3_3<2, 0b110100, 0b001000110,
669 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
670 "fsubd $src1, $src2, $dst",
671 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
673 // Floating-point Multiply and Divide Instructions, p. 147
674 def FMULS : F3_3<2, 0b110100, 0b001001001,
675 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
676 "fmuls $src1, $src2, $dst",
677 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
678 def FMULD : F3_3<2, 0b110100, 0b001001010,
679 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
680 "fmuld $src1, $src2, $dst",
681 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
682 def FSMULD : F3_3<2, 0b110100, 0b001101001,
683 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
684 "fsmuld $src1, $src2, $dst",
685 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
686 (fextend FPRegs:$src2)))]>;
687 def FDIVS : F3_3<2, 0b110100, 0b001001101,
688 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
689 "fdivs $src1, $src2, $dst",
690 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
691 def FDIVD : F3_3<2, 0b110100, 0b001001110,
692 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
693 "fdivd $src1, $src2, $dst",
694 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
696 // Floating-point Compare Instructions, p. 148
697 // Note: the 2nd template arg is different for these guys.
698 // Note 2: the result of a FCMP is not available until the 2nd cycle
699 // after the instr is retired, but there is no interlock. This behavior
700 // is modelled with a forced noop after the instruction.
701 def FCMPS : F3_3<2, 0b110101, 0b001010001,
702 (ops FPRegs:$src1, FPRegs:$src2),
703 "fcmps $src1, $src2\n\tnop",
704 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
705 def FCMPD : F3_3<2, 0b110101, 0b001010010,
706 (ops DFPRegs:$src1, DFPRegs:$src2),
707 "fcmpd $src1, $src2\n\tnop",
708 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
710 //===----------------------------------------------------------------------===//
711 // Non-Instruction Patterns
712 //===----------------------------------------------------------------------===//
715 def : Pat<(i32 simm13:$val),
716 (ORri G0, imm:$val)>;
717 // Arbitrary immediates.
718 def : Pat<(i32 imm:$val),
719 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
721 // Global addresses, constant pool entries
722 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
723 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
724 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
725 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
728 def : Pat<(call tglobaladdr:$dst),
729 (CALL tglobaladdr:$dst)>;
730 def : Pat<(call externalsym:$dst),
731 (CALL externalsym:$dst)>;
734 // Map integer extload's to zextloads.
735 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
736 def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
737 def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
738 def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
739 def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
740 def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
742 // zextload bool -> zextload byte
743 def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
744 def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
746 // truncstore bool -> truncstore byte.
747 def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
748 (STBrr ADDRrr:$addr, IntRegs:$src)>;
749 def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
750 (STBri ADDRri:$addr, IntRegs:$src)>;