1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 //===----------------------------------------------------------------------===//
44 //===----------------------------------------------------------------------===//
46 // Pseudo instructions.
47 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
48 let AsmString = asmstr;
49 dag OperandList = ops;
51 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
52 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
54 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
56 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
57 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
59 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
61 // Section A.3 - Synthetic Instructions, p. 85
62 // special cases of JMPL:
63 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
64 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
65 def RET : F3_2<2, 0b111000,
66 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
67 "ret $b, $c, $dst", []>;
68 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
69 def RETL: F3_2<2, 0b111000, (ops),
72 // CMP is a special case of SUBCC where destination is ignored, by setting it to
73 // %g0 (hardwired zero).
74 // FIXME: should keep track of the fact that it defs the integer condition codes
76 def CMPri: F3_2<2, 0b010100,
77 (ops IntRegs:$b, i32imm:$c),
80 // Section B.1 - Load Integer Instructions, p. 90
81 def LDSB: F3_2<3, 0b001001,
82 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
83 "ldsb [$b+$c], $dst", []>;
84 def LDSH: F3_2<3, 0b001010,
85 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
86 "ldsh [$b+$c], $dst", []>;
87 def LDUB: F3_2<3, 0b000001,
88 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
89 "ldub [$b+$c], $dst", []>;
90 def LDUH: F3_2<3, 0b000010,
91 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
92 "lduh [$b+$c], $dst", []>;
93 def LD : F3_2<3, 0b000000,
94 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
95 "ld [$b+$c], $dst", []>;
96 def LDD : F3_2<3, 0b000011,
97 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
98 "ldd [$b+$c], $dst", []>;
100 // Section B.2 - Load Floating-point Instructions, p. 92
101 def LDFrr : F3_1<3, 0b100000,
102 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
104 def LDFri : F3_2<3, 0b100000,
105 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
106 "ld [$b+$c], $dst", []>;
107 def LDDFrr : F3_1<3, 0b100011,
108 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
109 "ldd [$b+$c], $dst">;
110 def LDDFri : F3_2<3, 0b100011,
111 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
112 "ldd [$b+$c], $dst", []>;
113 def LDFSRrr: F3_1<3, 0b100001,
114 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
116 def LDFSRri: F3_2<3, 0b100001,
117 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
118 "ld [$b+$c], $dst", []>;
120 // Section B.4 - Store Integer Instructions, p. 95
121 def STB : F3_2<3, 0b000101,
122 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
123 "stb $src, [$base+$offset]", []>;
124 def STH : F3_2<3, 0b000110,
125 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
126 "sth $src, [$base+$offset]", []>;
127 def ST : F3_2<3, 0b000100,
128 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
129 "st $src, [$base+$offset]", []>;
130 def STD : F3_2<3, 0b000111,
131 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
132 "std $src, [$base+$offset]", []>;
134 // Section B.5 - Store Floating-point Instructions, p. 97
135 def STFrr : F3_1<3, 0b100100,
136 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
137 "st $src, [$base+$offset]">;
138 def STFri : F3_2<3, 0b100100,
139 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
140 "st $src, [$base+$offset]", []>;
141 def STDFrr : F3_1<3, 0b100111,
142 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
143 "std $src, [$base+$offset]">;
144 def STDFri : F3_2<3, 0b100111,
145 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
146 "std $src, [$base+$offset]", []>;
147 def STFSRrr : F3_1<3, 0b100101,
148 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
149 "st $src, [$base+$offset]">;
150 def STFSRri : F3_2<3, 0b100101,
151 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
152 "st $src, [$base+$offset]", []>;
153 def STDFQrr : F3_1<3, 0b100110,
154 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
155 "std $src, [$base+$offset]">;
156 def STDFQri : F3_2<3, 0b100110,
157 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
158 "std $src, [$base+$offset]", []>;
160 // Section B.9 - SETHI Instruction, p. 104
161 def SETHIi: F2_1<0b100,
162 (ops IntRegs:$dst, i32imm:$src),
165 // Section B.10 - NOP Instruction, p. 105
166 // (It's a special case of SETHI)
167 let rd = 0, imm22 = 0 in
168 def NOP : F2_1<0b100, (ops), "nop">;
170 // Section B.11 - Logical Instructions, p. 106
171 def ANDrr : F3_1<2, 0b000001,
172 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
174 def ANDri : F3_2<2, 0b000001,
175 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
177 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
178 def ANDCCrr : F3_1<2, 0b010001,
179 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
180 "andcc $b, $c, $dst">;
181 def ANDCCri : F3_2<2, 0b010001,
182 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
183 "andcc $b, $c, $dst", []>;
184 def ANDNrr : F3_1<2, 0b000101,
185 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
186 "andn $b, $c, $dst">;
187 def ANDNri : F3_2<2, 0b000101,
188 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
189 "andn $b, $c, $dst", []>;
190 def ANDNCCrr: F3_1<2, 0b010101,
191 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
192 "andncc $b, $c, $dst">;
193 def ANDNCCri: F3_2<2, 0b010101,
194 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
195 "andncc $b, $c, $dst", []>;
196 def ORrr : F3_1<2, 0b000010,
197 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
199 def ORri : F3_2<2, 0b000010,
200 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
202 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
203 def ORCCrr : F3_1<2, 0b010010,
204 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
205 "orcc $b, $c, $dst">;
206 def ORCCri : F3_2<2, 0b010010,
207 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
208 "orcc $b, $c, $dst", []>;
209 def ORNrr : F3_1<2, 0b000110,
210 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
212 def ORNri : F3_2<2, 0b000110,
213 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
214 "orn $b, $c, $dst", []>;
215 def ORNCCrr : F3_1<2, 0b010110,
216 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
217 "orncc $b, $c, $dst">;
218 def ORNCCri : F3_2<2, 0b010110,
219 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
220 "orncc $b, $c, $dst", []>;
221 def XORrr : F3_1<2, 0b000011,
222 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
224 def XORri : F3_2<2, 0b000011,
225 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
227 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
228 def XORCCrr : F3_1<2, 0b010011,
229 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
230 "xorcc $b, $c, $dst">;
231 def XORCCri : F3_2<2, 0b010011,
232 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
233 "xorcc $b, $c, $dst", []>;
234 def XNORrr : F3_1<2, 0b000111,
235 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
236 "xnor $b, $c, $dst">;
237 def XNORri : F3_2<2, 0b000111,
238 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
239 "xnor $b, $c, $dst", []>;
240 def XNORCCrr: F3_1<2, 0b010111,
241 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
242 "xnorcc $b, $c, $dst">;
243 def XNORCCri: F3_2<2, 0b010111,
244 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
245 "xnorcc $b, $c, $dst", []>;
247 // Section B.12 - Shift Instructions, p. 107
248 def SLLrr : F3_1<2, 0b100101,
249 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
251 def SLLri : F3_2<2, 0b100101,
252 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
253 "sll $b, $c, $dst", []>;
254 def SRLrr : F3_1<2, 0b100110,
255 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
257 def SRLri : F3_2<2, 0b100110,
258 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
259 "srl $b, $c, $dst", []>;
260 def SRArr : F3_1<2, 0b100111,
261 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
263 def SRAri : F3_2<2, 0b100111,
264 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
265 "sla $b, $c, $dst", []>;
267 // Section B.13 - Add Instructions, p. 108
268 def ADDrr : F3_1<2, 0b000000,
269 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
271 def ADDri : F3_2<2, 0b000000,
272 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
274 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
275 def ADDCCrr : F3_1<2, 0b010000,
276 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
277 "addcc $b, $c, $dst">;
278 def ADDCCri : F3_2<2, 0b010000,
279 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
280 "addcc $b, $c, $dst", []>;
281 def ADDXrr : F3_1<2, 0b001000,
282 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
283 "addx $b, $c, $dst">;
284 def ADDXri : F3_2<2, 0b001000,
285 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
286 "addx $b, $c, $dst", []>;
287 def ADDXCCrr: F3_1<2, 0b011000,
288 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
289 "addxcc $b, $c, $dst">;
290 def ADDXCCri: F3_2<2, 0b011000,
291 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
292 "addxcc $b, $c, $dst", []>;
294 // Section B.15 - Subtract Instructions, p. 110
295 def SUBrr : F3_1<2, 0b000100,
296 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
298 def SUBri : F3_2<2, 0b000100,
299 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
301 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
302 def SUBCCrr : F3_1<2, 0b010100,
303 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
304 "subcc $b, $c, $dst">;
305 def SUBCCri : F3_2<2, 0b010100,
306 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
307 "subcc $b, $c, $dst", []>;
308 def SUBXrr : F3_1<2, 0b001100,
309 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
310 "subx $b, $c, $dst">;
311 def SUBXri : F3_2<2, 0b001100,
312 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
313 "subx $b, $c, $dst", []>;
314 def SUBXCCrr: F3_1<2, 0b011100,
315 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
316 "subxcc $b, $c, $dst">;
317 def SUBXCCri: F3_2<2, 0b011100,
318 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
319 "subxcc $b, $c, $dst", []>;
321 // Section B.18 - Multiply Instructions, p. 113
322 def UMULrr : F3_1<2, 0b001010,
323 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
324 "umul $b, $c, $dst">;
325 def UMULri : F3_2<2, 0b001010,
326 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
327 "umul $b, $c, $dst", []>;
328 def SMULrr : F3_1<2, 0b001011,
329 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
330 "smul $b, $c, $dst">;
331 def SMULri : F3_2<2, 0b001011,
332 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
333 "smul $b, $c, $dst", []>;
334 def UMULCCrr: F3_1<2, 0b011010,
335 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
336 "umulcc $b, $c, $dst">;
337 def UMULCCri: F3_2<2, 0b011010,
338 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
339 "umulcc $b, $c, $dst", []>;
340 def SMULCCrr: F3_1<2, 0b011011,
341 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
342 "smulcc $b, $c, $dst">;
343 def SMULCCri: F3_2<2, 0b011011,
344 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
345 "smulcc $b, $c, $dst", []>;
347 // Section B.19 - Divide Instructions, p. 115
348 def UDIVrr : F3_1<2, 0b001110,
349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
350 "udiv $b, $c, $dst">;
351 def UDIVri : F3_2<2, 0b001110,
352 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
353 "udiv $b, $c, $dst", []>;
354 def SDIVrr : F3_1<2, 0b001111,
355 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
356 "sdiv $b, $c, $dst">;
357 def SDIVri : F3_2<2, 0b001111,
358 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
359 "sdiv $b, $c, $dst", []>;
360 def UDIVCCrr : F3_1<2, 0b011110,
361 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
362 "udivcc $b, $c, $dst">;
363 def UDIVCCri : F3_2<2, 0b011110,
364 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
365 "udivcc $b, $c, $dst", []>;
366 def SDIVCCrr : F3_1<2, 0b011111,
367 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
368 "sdivcc $b, $c, $dst">;
369 def SDIVCCri : F3_2<2, 0b011111,
370 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
371 "sdivcc $b, $c, $dst", []>;
373 // Section B.20 - SAVE and RESTORE, p. 117
374 def SAVErr : F3_1<2, 0b111100,
375 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
376 "save $b, $c, $dst">;
377 def SAVEri : F3_2<2, 0b111100,
378 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
379 "save $b, $c, $dst", []>;
380 def RESTORErr : F3_1<2, 0b111101,
381 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
382 "restore $b, $c, $dst">;
383 def RESTOREri : F3_2<2, 0b111101,
384 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
385 "restore $b, $c, $dst", []>;
387 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
389 // conditional branch class:
390 class BranchV8<bits<4> cc, dag ops, string asmstr>
391 : F2_2<cc, 0b010, ops, asmstr> {
393 let isTerminator = 1;
394 let hasDelaySlot = 1;
398 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
399 def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
400 def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
401 def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
402 def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
403 def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
404 def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
405 def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
406 def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
407 def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
408 def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
409 def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
411 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
413 // floating-point conditional branch class:
414 class FPBranchV8<bits<4> cc, dag ops, string asmstr>
415 : F2_2<cc, 0b110, ops, asmstr> {
417 let isTerminator = 1;
418 let hasDelaySlot = 1;
421 def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
422 def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
423 def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
424 def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
425 def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
426 def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
427 def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
428 def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
429 def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
430 def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
431 def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
432 def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
433 def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
434 def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
435 def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
436 def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
440 // Section B.24 - Call and Link Instruction, p. 125
441 // This is the only Format 1 instruction
442 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
444 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
445 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
447 let OperandList = (ops IntRegs:$dst);
450 let Inst{29-0} = disp;
451 let AsmString = "call $dst";
454 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
455 // be an implicit def):
456 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
457 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
458 def JMPLrr : F3_1<2, 0b111000,
459 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
463 // Section B.29 - Write State Register Instructions
464 def WRrr : F3_1<2, 0b110000,
465 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
467 def WRri : F3_2<2, 0b110000,
468 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
469 "wr $b, $c, $dst", []>;
471 // Convert Integer to Floating-point Instructions, p. 141
472 def FITOS : F3_3<2, 0b110100, 0b011000100,
473 (ops FPRegs:$dst, FPRegs:$src),
475 def FITOD : F3_3<2, 0b110100, 0b011001000,
476 (ops DFPRegs:$dst, DFPRegs:$src),
479 // Convert Floating-point to Integer Instructions, p. 142
480 def FSTOI : F3_3<2, 0b110100, 0b011010001,
481 (ops FPRegs:$dst, FPRegs:$src),
483 def FDTOI : F3_3<2, 0b110100, 0b011010010,
484 (ops DFPRegs:$dst, DFPRegs:$src),
487 // Convert between Floating-point Formats Instructions, p. 143
488 def FSTOD : F3_3<2, 0b110100, 0b011001001,
489 (ops DFPRegs:$dst, FPRegs:$src),
491 def FDTOS : F3_3<2, 0b110100, 0b011000110,
492 (ops FPRegs:$dst, DFPRegs:$src),
495 // Floating-point Move Instructions, p. 144
496 def FMOVS : F3_3<2, 0b110100, 0b000000001,
497 (ops FPRegs:$dst, FPRegs:$src),
499 def FNEGS : F3_3<2, 0b110100, 0b000000101,
500 (ops FPRegs:$dst, FPRegs:$src),
502 def FABSS : F3_3<2, 0b110100, 0b000001001,
503 (ops FPRegs:$dst, FPRegs:$src),
506 // Floating-point Add and Subtract Instructions, p. 146
507 def FADDS : F3_3<2, 0b110100, 0b001000001,
508 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
509 "fadds $src1, $src2, $dst">;
510 def FADDD : F3_3<2, 0b110100, 0b001000010,
511 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
512 "faddd $src1, $src2, $dst">;
513 def FSUBS : F3_3<2, 0b110100, 0b001000101,
514 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
515 "fsubs $src1, $src2, $dst">;
516 def FSUBD : F3_3<2, 0b110100, 0b001000110,
517 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
518 "fsubd $src1, $src2, $dst">;
520 // Floating-point Multiply and Divide Instructions, p. 147
521 def FMULS : F3_3<2, 0b110100, 0b001001001,
522 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
523 "fmuls $src1, $src2, $dst">;
524 def FMULD : F3_3<2, 0b110100, 0b001001010,
525 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
526 "fmuld $src1, $src2, $dst">;
527 def FSMULD : F3_3<2, 0b110100, 0b001101001,
528 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
529 "fsmuld $src1, $src2, $dst">;
530 def FDIVS : F3_3<2, 0b110100, 0b001001101,
531 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
532 "fdivs $src1, $src2, $dst">;
533 def FDIVD : F3_3<2, 0b110100, 0b001001110,
534 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
535 "fdivd $src1, $src2, $dst">;
537 // Floating-point Compare Instructions, p. 148
538 // Note: the 2nd template arg is different for these guys.
539 // Note 2: the result of a FCMP is not available until the 2nd cycle
540 // after the instr is retired, but there is no interlock. This behavior
541 // is modelled with a forced noop after the instruction.
542 def FCMPS : F3_3<2, 0b110101, 0b001010001,
543 (ops FPRegs:$src1, FPRegs:$src2),
544 "fcmps $src1, $src2\n\tnop">;
545 def FCMPD : F3_3<2, 0b110101, 0b001010010,
546 (ops DFPRegs:$src1, DFPRegs:$src2),
547 "fcmpd $src1, $src2\n\tnop">;
548 def FCMPES : F3_3<2, 0b110101, 0b001010101,
549 (ops FPRegs:$src1, FPRegs:$src2),
550 "fcmpes $src1, $src2\n\tnop">;
551 def FCMPED : F3_3<2, 0b110101, 0b001010110,
552 (ops DFPRegs:$src1, DFPRegs:$src2),
553 "fcmped $src1, $src2\n\tnop">;