1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // HasHardQuad - This is true when the target processor supports quad floating
43 // point instructions.
44 def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
46 // UseDeprecatedInsts - This predicate is true when the target processor is a
47 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
48 // to use when appropriate. In either of these cases, the instruction selector
49 // will pick deprecated instructions.
50 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
52 //===----------------------------------------------------------------------===//
53 // Instruction Pattern Stuff
54 //===----------------------------------------------------------------------===//
56 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
58 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
60 def LO10 : SDNodeXForm<imm, [{
61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
65 def HI22 : SDNodeXForm<imm, [{
66 // Transformation function: shift the immediate value down into the low bits.
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
70 def SETHIimm : PatLeaf<(imm), [{
71 return isShiftedUInt<22, 10>(N->getZExtValue());
75 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
79 def SparcMEMrrAsmOperand : AsmOperandClass {
81 let ParserMethod = "parseMEMOperand";
84 def SparcMEMriAsmOperand : AsmOperandClass {
86 let ParserMethod = "parseMEMOperand";
89 def MEMrr : Operand<iPTR> {
90 let PrintMethod = "printMemOperand";
91 let MIOperandInfo = (ops ptr_rc, ptr_rc);
92 let ParserMatchClass = SparcMEMrrAsmOperand;
94 def MEMri : Operand<iPTR> {
95 let PrintMethod = "printMemOperand";
96 let MIOperandInfo = (ops ptr_rc, i32imm);
97 let ParserMatchClass = SparcMEMriAsmOperand;
100 def TLSSym : Operand<iPTR>;
102 // Branch targets have OtherVT type.
103 def brtarget : Operand<OtherVT> {
104 let EncoderMethod = "getBranchTargetOpValue";
107 def calltarget : Operand<i32> {
108 let EncoderMethod = "getCallTargetOpValue";
111 // Operand for printing out a condition code.
112 let PrintMethod = "printCCOperand" in
113 def CCOp : Operand<i32>;
116 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
118 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
120 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
122 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
124 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
126 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
128 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
130 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
133 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
135 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
137 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
138 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
139 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
140 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
141 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
143 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
144 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
146 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
147 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
148 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
149 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
151 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
152 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
153 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
155 // These are target-independent nodes, but have target-specific formats.
156 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
157 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
160 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
161 [SDNPHasChain, SDNPOutGlue]>;
162 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
165 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
166 def call : SDNode<"SPISD::CALL", SDT_SPCall,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
170 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
171 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
172 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
174 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
175 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
177 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
178 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
179 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
183 def getPCX : Operand<i32> {
184 let PrintMethod = "printGetPCX";
187 //===----------------------------------------------------------------------===//
188 // SPARC Flag Conditions
189 //===----------------------------------------------------------------------===//
191 // Note that these values must be kept in sync with the CCOp::CondCode enum
193 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
194 def ICC_NE : ICC_VAL< 9>; // Not Equal
195 def ICC_E : ICC_VAL< 1>; // Equal
196 def ICC_G : ICC_VAL<10>; // Greater
197 def ICC_LE : ICC_VAL< 2>; // Less or Equal
198 def ICC_GE : ICC_VAL<11>; // Greater or Equal
199 def ICC_L : ICC_VAL< 3>; // Less
200 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
201 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
202 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
203 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
204 def ICC_POS : ICC_VAL<14>; // Positive
205 def ICC_NEG : ICC_VAL< 6>; // Negative
206 def ICC_VC : ICC_VAL<15>; // Overflow Clear
207 def ICC_VS : ICC_VAL< 7>; // Overflow Set
209 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
210 def FCC_U : FCC_VAL<23>; // Unordered
211 def FCC_G : FCC_VAL<22>; // Greater
212 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
213 def FCC_L : FCC_VAL<20>; // Less
214 def FCC_UL : FCC_VAL<19>; // Unordered or Less
215 def FCC_LG : FCC_VAL<18>; // Less or Greater
216 def FCC_NE : FCC_VAL<17>; // Not Equal
217 def FCC_E : FCC_VAL<25>; // Equal
218 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
219 def FCC_GE : FCC_VAL<25>; // Greater or Equal
220 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
221 def FCC_LE : FCC_VAL<27>; // Less or Equal
222 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
223 def FCC_O : FCC_VAL<29>; // Ordered
225 //===----------------------------------------------------------------------===//
226 // Instruction Class Templates
227 //===----------------------------------------------------------------------===//
229 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
230 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
231 RegisterClass RC, ValueType Ty, Operand immOp> {
232 def rr : F3_1<2, Op3Val,
233 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
234 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
235 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
236 def ri : F3_2<2, Op3Val,
237 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
238 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
239 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
242 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
244 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
245 def rr : F3_1<2, Op3Val,
246 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
247 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
248 def ri : F3_2<2, Op3Val,
249 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
250 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
253 //===----------------------------------------------------------------------===//
255 //===----------------------------------------------------------------------===//
257 // Pseudo instructions.
258 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
259 : InstSP<outs, ins, asmstr, pattern> {
260 let isCodeGenOnly = 1;
266 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
269 let Defs = [O6], Uses = [O6] in {
270 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
271 "!ADJCALLSTACKDOWN $amt",
272 [(callseq_start timm:$amt)]>;
273 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
274 "!ADJCALLSTACKUP $amt1",
275 [(callseq_end timm:$amt1, timm:$amt2)]>;
278 let hasSideEffects = 1, mayStore = 1 in {
279 let rd = 0, rs1 = 0, rs2 = 0 in
280 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
282 [(flushw)]>, Requires<[HasV9]>;
283 let rd = 0, rs1 = 1, simm13 = 3 in
284 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
290 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
293 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
294 // instruction selection into a branch sequence. This has to handle all
295 // permutations of selection between i32/f32/f64 on ICC and FCC.
296 // Expanded after instruction selection.
297 let Uses = [ICC], usesCustomInserter = 1 in {
298 def SELECT_CC_Int_ICC
299 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
300 "; SELECT_CC_Int_ICC PSEUDO!",
301 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
303 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
304 "; SELECT_CC_FP_ICC PSEUDO!",
305 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
307 def SELECT_CC_DFP_ICC
308 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
309 "; SELECT_CC_DFP_ICC PSEUDO!",
310 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
312 def SELECT_CC_QFP_ICC
313 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
314 "; SELECT_CC_QFP_ICC PSEUDO!",
315 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
318 let usesCustomInserter = 1, Uses = [FCC] in {
320 def SELECT_CC_Int_FCC
321 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
322 "; SELECT_CC_Int_FCC PSEUDO!",
323 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
326 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
327 "; SELECT_CC_FP_FCC PSEUDO!",
328 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
329 def SELECT_CC_DFP_FCC
330 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
331 "; SELECT_CC_DFP_FCC PSEUDO!",
332 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
333 def SELECT_CC_QFP_FCC
334 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
335 "; SELECT_CC_QFP_FCC PSEUDO!",
336 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
340 // Section A.3 - Synthetic Instructions, p. 85
341 // special cases of JMPL:
342 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
343 let rd = 0, rs1 = 15 in
344 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
345 "jmp %o7+$val", [(retflag simm13:$val)]>;
347 let rd = 0, rs1 = 31 in
348 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
352 // Section B.1 - Load Integer Instructions, p. 90
353 def LDSBrr : F3_1<3, 0b001001,
354 (outs IntRegs:$dst), (ins MEMrr:$addr),
355 "ldsb [$addr], $dst",
356 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
357 def LDSBri : F3_2<3, 0b001001,
358 (outs IntRegs:$dst), (ins MEMri:$addr),
359 "ldsb [$addr], $dst",
360 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
361 def LDSHrr : F3_1<3, 0b001010,
362 (outs IntRegs:$dst), (ins MEMrr:$addr),
363 "ldsh [$addr], $dst",
364 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
365 def LDSHri : F3_2<3, 0b001010,
366 (outs IntRegs:$dst), (ins MEMri:$addr),
367 "ldsh [$addr], $dst",
368 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
369 def LDUBrr : F3_1<3, 0b000001,
370 (outs IntRegs:$dst), (ins MEMrr:$addr),
371 "ldub [$addr], $dst",
372 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
373 def LDUBri : F3_2<3, 0b000001,
374 (outs IntRegs:$dst), (ins MEMri:$addr),
375 "ldub [$addr], $dst",
376 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
377 def LDUHrr : F3_1<3, 0b000010,
378 (outs IntRegs:$dst), (ins MEMrr:$addr),
379 "lduh [$addr], $dst",
380 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
381 def LDUHri : F3_2<3, 0b000010,
382 (outs IntRegs:$dst), (ins MEMri:$addr),
383 "lduh [$addr], $dst",
384 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
385 def LDrr : F3_1<3, 0b000000,
386 (outs IntRegs:$dst), (ins MEMrr:$addr),
388 [(set i32:$dst, (load ADDRrr:$addr))]>;
389 def LDri : F3_2<3, 0b000000,
390 (outs IntRegs:$dst), (ins MEMri:$addr),
392 [(set i32:$dst, (load ADDRri:$addr))]>;
394 // Section B.2 - Load Floating-point Instructions, p. 92
395 def LDFrr : F3_1<3, 0b100000,
396 (outs FPRegs:$dst), (ins MEMrr:$addr),
398 [(set f32:$dst, (load ADDRrr:$addr))]>;
399 def LDFri : F3_2<3, 0b100000,
400 (outs FPRegs:$dst), (ins MEMri:$addr),
402 [(set f32:$dst, (load ADDRri:$addr))]>;
403 def LDDFrr : F3_1<3, 0b100011,
404 (outs DFPRegs:$dst), (ins MEMrr:$addr),
406 [(set f64:$dst, (load ADDRrr:$addr))]>;
407 def LDDFri : F3_2<3, 0b100011,
408 (outs DFPRegs:$dst), (ins MEMri:$addr),
410 [(set f64:$dst, (load ADDRri:$addr))]>;
411 def LDQFrr : F3_1<3, 0b100010,
412 (outs QFPRegs:$dst), (ins MEMrr:$addr),
414 [(set f128:$dst, (load ADDRrr:$addr))]>,
415 Requires<[HasV9, HasHardQuad]>;
416 def LDQFri : F3_2<3, 0b100010,
417 (outs QFPRegs:$dst), (ins MEMri:$addr),
419 [(set f128:$dst, (load ADDRri:$addr))]>,
420 Requires<[HasV9, HasHardQuad]>;
422 // Section B.4 - Store Integer Instructions, p. 95
423 def STBrr : F3_1<3, 0b000101,
424 (outs), (ins MEMrr:$addr, IntRegs:$rd),
426 [(truncstorei8 i32:$rd, ADDRrr:$addr)]>;
427 def STBri : F3_2<3, 0b000101,
428 (outs), (ins MEMri:$addr, IntRegs:$rd),
430 [(truncstorei8 i32:$rd, ADDRri:$addr)]>;
431 def STHrr : F3_1<3, 0b000110,
432 (outs), (ins MEMrr:$addr, IntRegs:$rd),
434 [(truncstorei16 i32:$rd, ADDRrr:$addr)]>;
435 def STHri : F3_2<3, 0b000110,
436 (outs), (ins MEMri:$addr, IntRegs:$rd),
438 [(truncstorei16 i32:$rd, ADDRri:$addr)]>;
439 def STrr : F3_1<3, 0b000100,
440 (outs), (ins MEMrr:$addr, IntRegs:$rd),
442 [(store i32:$rd, ADDRrr:$addr)]>;
443 def STri : F3_2<3, 0b000100,
444 (outs), (ins MEMri:$addr, IntRegs:$rd),
446 [(store i32:$rd, ADDRri:$addr)]>;
448 // Section B.5 - Store Floating-point Instructions, p. 97
449 def STFrr : F3_1<3, 0b100100,
450 (outs), (ins MEMrr:$addr, FPRegs:$rd),
452 [(store f32:$rd, ADDRrr:$addr)]>;
453 def STFri : F3_2<3, 0b100100,
454 (outs), (ins MEMri:$addr, FPRegs:$rd),
456 [(store f32:$rd, ADDRri:$addr)]>;
457 def STDFrr : F3_1<3, 0b100111,
458 (outs), (ins MEMrr:$addr, DFPRegs:$rd),
460 [(store f64:$rd, ADDRrr:$addr)]>;
461 def STDFri : F3_2<3, 0b100111,
462 (outs), (ins MEMri:$addr, DFPRegs:$rd),
464 [(store f64:$rd, ADDRri:$addr)]>;
465 def STQFrr : F3_1<3, 0b100110,
466 (outs), (ins MEMrr:$addr, QFPRegs:$rd),
468 [(store f128:$rd, ADDRrr:$addr)]>,
469 Requires<[HasV9, HasHardQuad]>;
470 def STQFri : F3_2<3, 0b100110,
471 (outs), (ins MEMri:$addr, QFPRegs:$rd),
473 [(store f128:$rd, ADDRri:$addr)]>,
474 Requires<[HasV9, HasHardQuad]>;
476 // Section B.9 - SETHI Instruction, p. 104
477 def SETHIi: F2_1<0b100,
478 (outs IntRegs:$rd), (ins i32imm:$imm22),
480 [(set i32:$rd, SETHIimm:$imm22)]>;
482 // Section B.10 - NOP Instruction, p. 105
483 // (It's a special case of SETHI)
484 let rd = 0, imm22 = 0 in
485 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
487 // Section B.11 - Logical Instructions, p. 106
488 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
490 def ANDNrr : F3_1<2, 0b000101,
491 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
492 "andn $rs1, $rs2, $rd",
493 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
494 def ANDNri : F3_2<2, 0b000101,
495 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
496 "andn $rs1, $simm13, $rd", []>;
498 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
500 def ORNrr : F3_1<2, 0b000110,
501 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
502 "orn $rs1, $rs2, $rd",
503 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
504 def ORNri : F3_2<2, 0b000110,
505 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
506 "orn $rs1, $simm13, $rd", []>;
507 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
509 def XNORrr : F3_1<2, 0b000111,
510 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
511 "xnor $rs1, $rs2, $rd",
512 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
513 def XNORri : F3_2<2, 0b000111,
514 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
515 "xnor $rs1, $simm13, $rd", []>;
517 // Section B.12 - Shift Instructions, p. 107
518 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
519 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
520 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
522 // Section B.13 - Add Instructions, p. 108
523 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
525 // "LEA" forms of add (patterns to make tblgen happy)
526 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
527 def LEA_ADDri : F3_2<2, 0b000000,
528 (outs IntRegs:$dst), (ins MEMri:$addr),
529 "add ${addr:arith}, $dst",
530 [(set iPTR:$dst, ADDRri:$addr)]>;
533 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
535 let Uses = [ICC], Defs = [ICC] in
536 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
538 // Section B.15 - Subtract Instructions, p. 110
539 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
540 let Uses = [ICC], Defs = [ICC] in
541 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
544 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
546 let Defs = [ICC], rd = 0 in {
547 def CMPrr : F3_1<2, 0b010100,
548 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
550 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
551 def CMPri : F3_2<2, 0b010100,
552 (outs), (ins IntRegs:$rs1, i32imm:$simm13),
554 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
557 // Section B.18 - Multiply Instructions, p. 113
559 defm UMUL : F3_12np<"umul", 0b001010>;
560 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
563 // Section B.19 - Divide Instructions, p. 115
565 defm UDIV : F3_12np<"udiv", 0b001110>;
566 defm SDIV : F3_12np<"sdiv", 0b001111>;
569 // Section B.20 - SAVE and RESTORE, p. 117
570 defm SAVE : F3_12np<"save" , 0b111100>;
571 defm RESTORE : F3_12np<"restore", 0b111101>;
573 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
575 // unconditional branch class.
576 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
577 : F2_2<0b010, (outs), ins, asmstr, pattern> {
579 let isTerminator = 1;
580 let hasDelaySlot = 1;
585 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
587 // conditional branch class:
588 class BranchSP<dag ins, string asmstr, list<dag> pattern>
589 : F2_2<0b010, (outs), ins, asmstr, pattern> {
591 let isTerminator = 1;
592 let hasDelaySlot = 1;
595 // Indirect branch instructions.
596 let isTerminator = 1, isBarrier = 1,
597 hasDelaySlot = 1, isBranch =1,
598 isIndirectBranch = 1, rd = 0 in {
599 def BINDrr : F3_1<2, 0b111000,
600 (outs), (ins MEMrr:$ptr),
602 [(brind ADDRrr:$ptr)]>;
603 def BINDri : F3_2<2, 0b111000,
604 (outs), (ins MEMri:$ptr),
606 [(brind ADDRri:$ptr)]>;
610 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
612 [(SPbricc bb:$imm22, imm:$cond)]>;
614 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
616 // floating-point conditional branch class:
617 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
618 : F2_2<0b110, (outs), ins, asmstr, pattern> {
620 let isTerminator = 1;
621 let hasDelaySlot = 1;
625 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
627 [(SPbrfcc bb:$imm22, imm:$cond)]>;
630 // Section B.24 - Call and Link Instruction, p. 125
631 // This is the only Format 1 instruction
633 hasDelaySlot = 1, isCall = 1 in {
634 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
638 let Inst{29-0} = disp;
642 def JMPLrr : F3_1<2, 0b111000,
643 (outs), (ins MEMrr:$ptr, variable_ops),
645 [(call ADDRrr:$ptr)]> { let rd = 15; }
646 def JMPLri : F3_2<2, 0b111000,
647 (outs), (ins MEMri:$ptr, variable_ops),
649 [(call ADDRri:$ptr)]> { let rd = 15; }
652 // Section B.28 - Read State Register Instructions
653 let Uses = [Y], rs1 = 0, rs2 = 0 in
654 def RDY : F3_1<2, 0b101000,
655 (outs IntRegs:$dst), (ins),
658 // Section B.29 - Write State Register Instructions
659 let Defs = [Y], rd = 0 in {
660 def WRYrr : F3_1<2, 0b110000,
661 (outs), (ins IntRegs:$b, IntRegs:$c),
662 "wr $b, $c, %y", []>;
663 def WRYri : F3_2<2, 0b110000,
664 (outs), (ins IntRegs:$b, i32imm:$c),
665 "wr $b, $c, %y", []>;
667 // Convert Integer to Floating-point Instructions, p. 141
668 def FITOS : F3_3u<2, 0b110100, 0b011000100,
669 (outs FPRegs:$dst), (ins FPRegs:$src),
671 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
672 def FITOD : F3_3u<2, 0b110100, 0b011001000,
673 (outs DFPRegs:$dst), (ins FPRegs:$src),
675 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
676 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
677 (outs QFPRegs:$dst), (ins FPRegs:$src),
679 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
680 Requires<[HasHardQuad]>;
682 // Convert Floating-point to Integer Instructions, p. 142
683 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
684 (outs FPRegs:$dst), (ins FPRegs:$src),
686 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
687 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
688 (outs FPRegs:$dst), (ins DFPRegs:$src),
690 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
691 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
692 (outs FPRegs:$dst), (ins QFPRegs:$src),
694 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
695 Requires<[HasHardQuad]>;
697 // Convert between Floating-point Formats Instructions, p. 143
698 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
699 (outs DFPRegs:$dst), (ins FPRegs:$src),
701 [(set f64:$dst, (fextend f32:$src))]>;
702 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
703 (outs QFPRegs:$dst), (ins FPRegs:$src),
705 [(set f128:$dst, (fextend f32:$src))]>,
706 Requires<[HasHardQuad]>;
707 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
708 (outs FPRegs:$dst), (ins DFPRegs:$src),
710 [(set f32:$dst, (fround f64:$src))]>;
711 def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
712 (outs QFPRegs:$dst), (ins DFPRegs:$src),
714 [(set f128:$dst, (fextend f64:$src))]>,
715 Requires<[HasHardQuad]>;
716 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
717 (outs FPRegs:$dst), (ins QFPRegs:$src),
719 [(set f32:$dst, (fround f128:$src))]>,
720 Requires<[HasHardQuad]>;
721 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
722 (outs DFPRegs:$dst), (ins QFPRegs:$src),
724 [(set f64:$dst, (fround f128:$src))]>,
725 Requires<[HasHardQuad]>;
727 // Floating-point Move Instructions, p. 144
728 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
729 (outs FPRegs:$dst), (ins FPRegs:$src),
730 "fmovs $src, $dst", []>;
731 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
732 (outs FPRegs:$dst), (ins FPRegs:$src),
734 [(set f32:$dst, (fneg f32:$src))]>;
735 def FABSS : F3_3u<2, 0b110100, 0b000001001,
736 (outs FPRegs:$dst), (ins FPRegs:$src),
738 [(set f32:$dst, (fabs f32:$src))]>;
741 // Floating-point Square Root Instructions, p.145
742 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
743 (outs FPRegs:$dst), (ins FPRegs:$src),
745 [(set f32:$dst, (fsqrt f32:$src))]>;
746 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
747 (outs DFPRegs:$dst), (ins DFPRegs:$src),
749 [(set f64:$dst, (fsqrt f64:$src))]>;
750 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
751 (outs QFPRegs:$dst), (ins QFPRegs:$src),
753 [(set f128:$dst, (fsqrt f128:$src))]>,
754 Requires<[HasHardQuad]>;
758 // Floating-point Add and Subtract Instructions, p. 146
759 def FADDS : F3_3<2, 0b110100, 0b001000001,
760 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
761 "fadds $src1, $src2, $dst",
762 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
763 def FADDD : F3_3<2, 0b110100, 0b001000010,
764 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
765 "faddd $src1, $src2, $dst",
766 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
767 def FADDQ : F3_3<2, 0b110100, 0b001000011,
768 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
769 "faddq $src1, $src2, $dst",
770 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
771 Requires<[HasHardQuad]>;
773 def FSUBS : F3_3<2, 0b110100, 0b001000101,
774 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
775 "fsubs $src1, $src2, $dst",
776 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
777 def FSUBD : F3_3<2, 0b110100, 0b001000110,
778 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
779 "fsubd $src1, $src2, $dst",
780 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
781 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
782 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
783 "fsubq $src1, $src2, $dst",
784 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
785 Requires<[HasHardQuad]>;
788 // Floating-point Multiply and Divide Instructions, p. 147
789 def FMULS : F3_3<2, 0b110100, 0b001001001,
790 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
791 "fmuls $src1, $src2, $dst",
792 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
793 def FMULD : F3_3<2, 0b110100, 0b001001010,
794 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
795 "fmuld $src1, $src2, $dst",
796 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
797 def FMULQ : F3_3<2, 0b110100, 0b001001011,
798 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
799 "fmulq $src1, $src2, $dst",
800 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
801 Requires<[HasHardQuad]>;
803 def FSMULD : F3_3<2, 0b110100, 0b001101001,
804 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
805 "fsmuld $src1, $src2, $dst",
806 [(set f64:$dst, (fmul (fextend f32:$src1),
807 (fextend f32:$src2)))]>;
808 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
809 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
810 "fdmulq $src1, $src2, $dst",
811 [(set f128:$dst, (fmul (fextend f64:$src1),
812 (fextend f64:$src2)))]>,
813 Requires<[HasHardQuad]>;
815 def FDIVS : F3_3<2, 0b110100, 0b001001101,
816 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
817 "fdivs $src1, $src2, $dst",
818 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
819 def FDIVD : F3_3<2, 0b110100, 0b001001110,
820 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
821 "fdivd $src1, $src2, $dst",
822 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
823 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
824 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
825 "fdivq $src1, $src2, $dst",
826 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
827 Requires<[HasHardQuad]>;
829 // Floating-point Compare Instructions, p. 148
830 // Note: the 2nd template arg is different for these guys.
831 // Note 2: the result of a FCMP is not available until the 2nd cycle
832 // after the instr is retired, but there is no interlock in Sparc V8.
833 // This behavior is modeled with a forced noop after the instruction in
836 let Defs = [FCC] in {
837 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
838 (outs), (ins FPRegs:$src1, FPRegs:$src2),
839 "fcmps $src1, $src2",
840 [(SPcmpfcc f32:$src1, f32:$src2)]>;
841 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
842 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
843 "fcmpd $src1, $src2",
844 [(SPcmpfcc f64:$src1, f64:$src2)]>;
845 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
846 (outs), (ins QFPRegs:$src1, QFPRegs:$src2),
847 "fcmpq $src1, $src2",
848 [(SPcmpfcc f128:$src1, f128:$src2)]>,
849 Requires<[HasHardQuad]>;
852 //===----------------------------------------------------------------------===//
853 // Instructions for Thread Local Storage(TLS).
854 //===----------------------------------------------------------------------===//
855 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
856 def TLS_ADDrr : F3_1<2, 0b000000,
858 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
859 "add $rs1, $rs2, $rd, $sym",
861 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
864 def TLS_LDrr : F3_1<3, 0b000000,
865 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
866 "ld [$addr], $dst, $sym",
868 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
870 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
871 def TLS_CALL : InstSP<(outs),
872 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
874 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
877 let Inst{29-0} = disp;
881 //===----------------------------------------------------------------------===//
883 //===----------------------------------------------------------------------===//
885 // V9 Conditional Moves.
886 let Predicates = [HasV9], Constraints = "$f = $rd" in {
887 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
888 let Uses = [ICC], cc = 0b100 in {
890 : F4_1<0b101100, (outs IntRegs:$rd),
891 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
892 "mov$cond %icc, $rs2, $rd",
893 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
896 : F4_2<0b101100, (outs IntRegs:$rd),
897 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
898 "mov$cond %icc, $simm11, $rd",
900 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
903 let Uses = [FCC], cc = 0b000 in {
905 : F4_1<0b101100, (outs IntRegs:$rd),
906 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
907 "mov$cond %fcc0, $rs2, $rd",
908 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
910 : F4_2<0b101100, (outs IntRegs:$rd),
911 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
912 "mov$cond %fcc0, $simm11, $rd",
914 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
917 let Uses = [ICC], opf_cc = 0b100 in {
919 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
920 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
921 "fmovs$cond %icc, $rs2, $rd",
922 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
924 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
925 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
926 "fmovd$cond %icc, $rs2, $rd",
927 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
929 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
930 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
931 "fmovq$cond %icc, $rs2, $rd",
932 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
933 Requires<[HasHardQuad]>;
936 let Uses = [FCC], opf_cc = 0b000 in {
938 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
939 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
940 "fmovs$cond %fcc0, $rs2, $rd",
941 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
943 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
944 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
945 "fmovd$cond %fcc0, $rs2, $rd",
946 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
948 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
949 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
950 "fmovq$cond %fcc0, $rs2, $rd",
951 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
952 Requires<[HasHardQuad]>;
957 // Floating-Point Move Instructions, p. 164 of the V9 manual.
958 let Predicates = [HasV9] in {
959 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
960 (outs DFPRegs:$dst), (ins DFPRegs:$src),
961 "fmovd $src, $dst", []>;
962 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
963 (outs QFPRegs:$dst), (ins QFPRegs:$src),
964 "fmovq $src, $dst", []>,
965 Requires<[HasHardQuad]>;
966 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
967 (outs DFPRegs:$dst), (ins DFPRegs:$src),
969 [(set f64:$dst, (fneg f64:$src))]>;
970 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
971 (outs QFPRegs:$dst), (ins QFPRegs:$src),
973 [(set f128:$dst, (fneg f128:$src))]>,
974 Requires<[HasHardQuad]>;
975 def FABSD : F3_3u<2, 0b110100, 0b000001010,
976 (outs DFPRegs:$dst), (ins DFPRegs:$src),
978 [(set f64:$dst, (fabs f64:$src))]>;
979 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
980 (outs QFPRegs:$dst), (ins QFPRegs:$src),
982 [(set f128:$dst, (fabs f128:$src))]>,
983 Requires<[HasHardQuad]>;
986 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
987 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
989 def POPCrr : F3_1<2, 0b101110,
990 (outs IntRegs:$dst), (ins IntRegs:$src),
991 "popc $src, $dst", []>, Requires<[HasV9]>;
992 def : Pat<(ctpop i32:$src),
993 (POPCrr (SRLri $src, 0))>;
996 let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
997 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
999 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1000 def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
1001 "membar $simm13", []>;
1003 let Constraints = "$val = $rd" in {
1004 def SWAPrr : F3_1<3, 0b001111,
1005 (outs IntRegs:$rd), (ins IntRegs:$val, MEMrr:$addr),
1006 "swap [$addr], $rd",
1007 [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
1008 def SWAPri : F3_2<3, 0b001111,
1009 (outs IntRegs:$rd), (ins IntRegs:$val, MEMri:$addr),
1010 "swap [$addr], $rd",
1011 [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
1014 let Predicates = [HasV9], Constraints = "$swap = $rd" in
1015 def CASrr: F3_1<3, 0b111100,
1016 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1018 "cas [$rs1], $rs2, $rd",
1020 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1022 //===----------------------------------------------------------------------===//
1023 // Non-Instruction Patterns
1024 //===----------------------------------------------------------------------===//
1026 // Small immediates.
1027 def : Pat<(i32 simm13:$val),
1028 (ORri (i32 G0), imm:$val)>;
1029 // Arbitrary immediates.
1030 def : Pat<(i32 imm:$val),
1031 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1034 // Global addresses, constant pool entries
1035 let Predicates = [Is32Bit] in {
1037 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1038 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1039 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1040 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1042 // GlobalTLS addresses
1043 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1044 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1045 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1046 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1047 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1048 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1051 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1052 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1054 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1055 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1056 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1057 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1058 (ADDri $r, tblockaddress:$in)>;
1062 def : Pat<(call tglobaladdr:$dst),
1063 (CALL tglobaladdr:$dst)>;
1064 def : Pat<(call texternalsym:$dst),
1065 (CALL texternalsym:$dst)>;
1067 // Map integer extload's to zextloads.
1068 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1069 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1070 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1071 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1072 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1073 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1075 // zextload bool -> zextload byte
1076 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1077 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1079 // store 0, addr -> store %g0, addr
1080 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1081 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1083 // store bar for all atomic_fence in V8.
1084 let Predicates = [HasNoV9] in
1085 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1087 // atomic_load_32 addr -> load addr
1088 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1089 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1091 // atomic_store_32 val, addr -> store val, addr
1092 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1093 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1096 include "SparcInstr64Bit.td"
1097 include "SparcInstrAliases.td"