1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 def LO10 : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
46 def HI22 : SDNodeXForm<imm, [{
47 // Transformation function: shift the immediate value down into the low bits.
48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
51 def SETHIimm : PatLeaf<(imm), [{
52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
56 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
57 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
60 def MEMrr : Operand<i32> {
61 let PrintMethod = "printMemOperand";
62 let NumMIOperands = 2;
63 let MIOperandInfo = (ops IntRegs, IntRegs);
65 def MEMri : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let NumMIOperands = 2;
68 let MIOperandInfo = (ops IntRegs, i32imm);
71 //===----------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
75 // Pseudo instructions.
76 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
77 let AsmString = asmstr;
78 dag OperandList = ops;
80 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
81 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
83 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
85 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
86 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
88 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
90 // Section A.3 - Synthetic Instructions, p. 85
91 // special cases of JMPL:
92 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
93 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
94 def RET : F3_2<2, 0b111000,
95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
96 "ret $b, $c, $dst", []>;
97 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
98 def RETL: F3_2<2, 0b111000, (ops),
101 // CMP is a special case of SUBCC where destination is ignored, by setting it to
102 // %g0 (hardwired zero).
103 // FIXME: should keep track of the fact that it defs the integer condition codes
105 def CMPri: F3_2<2, 0b010100,
106 (ops IntRegs:$b, i32imm:$c),
109 // Section B.1 - Load Integer Instructions, p. 90
110 def LDSBrr : F3_1<3, 0b001001,
111 (ops IntRegs:$dst, MEMrr:$addr),
112 "ldsb [$addr], $dst",
113 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
114 def LDSBri : F3_2<3, 0b001001,
115 (ops IntRegs:$dst, MEMri:$addr),
116 "ldsb [$addr], $dst",
117 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
118 def LDSHrr : F3_1<3, 0b001010,
119 (ops IntRegs:$dst, MEMrr:$addr),
120 "ldsh [$addr], $dst",
121 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
122 def LDSHri : F3_2<3, 0b001010,
123 (ops IntRegs:$dst, MEMri:$addr),
124 "ldsh [$addr], $dst",
125 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
126 def LDUBrr : F3_1<3, 0b000001,
127 (ops IntRegs:$dst, MEMrr:$addr),
128 "ldub [$addr], $dst",
129 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
130 def LDUBri : F3_2<3, 0b000001,
131 (ops IntRegs:$dst, MEMri:$addr),
132 "ldub [$addr], $dst",
133 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
134 def LDUHrr : F3_1<3, 0b000010,
135 (ops IntRegs:$dst, MEMrr:$addr),
136 "lduh [$addr], $dst",
137 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
138 def LDUHri : F3_2<3, 0b000010,
139 (ops IntRegs:$dst, MEMri:$addr),
140 "lduh [$addr], $dst",
141 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
142 def LDrr : F3_1<3, 0b000000,
143 (ops IntRegs:$dst, MEMrr:$addr),
145 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
146 def LDri : F3_2<3, 0b000000,
147 (ops IntRegs:$dst, MEMri:$addr),
149 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
150 def LDDrr : F3_1<3, 0b000011,
151 (ops IntRegs:$dst, MEMrr:$addr),
152 "ldd [$addr], $dst", []>;
153 def LDDri : F3_2<3, 0b000011,
154 (ops IntRegs:$dst, MEMri:$addr),
155 "ldd [$addr], $dst", []>;
157 // Section B.2 - Load Floating-point Instructions, p. 92
158 def LDFrr : F3_1<3, 0b100000,
159 (ops FPRegs:$dst, MEMrr:$addr),
161 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
162 def LDFri : F3_2<3, 0b100000,
163 (ops FPRegs:$dst, MEMri:$addr),
165 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
166 def LDDFrr : F3_1<3, 0b100011,
167 (ops DFPRegs:$dst, MEMrr:$addr),
169 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
170 def LDDFri : F3_2<3, 0b100011,
171 (ops DFPRegs:$dst, MEMri:$addr),
173 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
175 // Section B.4 - Store Integer Instructions, p. 95
176 def STBrr : F3_1<3, 0b000101,
177 (ops MEMrr:$addr, IntRegs:$src),
179 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
180 def STBri : F3_2<3, 0b000101,
181 (ops MEMri:$addr, IntRegs:$src),
183 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
184 def STHrr : F3_1<3, 0b000110,
185 (ops MEMrr:$addr, IntRegs:$src),
187 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
188 def STHri : F3_2<3, 0b000110,
189 (ops MEMri:$addr, IntRegs:$src),
191 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
192 def STrr : F3_1<3, 0b000100,
193 (ops MEMrr:$addr, IntRegs:$src),
195 [(store IntRegs:$src, ADDRrr:$addr)]>;
196 def STri : F3_2<3, 0b000100,
197 (ops MEMri:$addr, IntRegs:$src),
199 [(store IntRegs:$src, ADDRri:$addr)]>;
200 def STDrr : F3_1<3, 0b000111,
201 (ops MEMrr:$addr, IntRegs:$src),
202 "std $src, [$addr]", []>;
203 def STDri : F3_2<3, 0b000111,
204 (ops MEMri:$addr, IntRegs:$src),
205 "std $src, [$addr]", []>;
207 // Section B.5 - Store Floating-point Instructions, p. 97
208 def STFrr : F3_1<3, 0b100100,
209 (ops MEMrr:$addr, FPRegs:$src),
211 [(store FPRegs:$src, ADDRrr:$addr)]>;
212 def STFri : F3_2<3, 0b100100,
213 (ops MEMri:$addr, FPRegs:$src),
215 [(store FPRegs:$src, ADDRri:$addr)]>;
216 def STDFrr : F3_1<3, 0b100111,
217 (ops MEMrr:$addr, DFPRegs:$src),
219 [(store DFPRegs:$src, ADDRrr:$addr)]>;
220 def STDFri : F3_2<3, 0b100111,
221 (ops MEMri:$addr, DFPRegs:$src),
223 [(store DFPRegs:$src, ADDRri:$addr)]>;
225 // Section B.9 - SETHI Instruction, p. 104
226 def SETHIi: F2_1<0b100,
227 (ops IntRegs:$dst, i32imm:$src),
229 [(set IntRegs:$dst, SETHIimm:$src)]>;
231 // Section B.10 - NOP Instruction, p. 105
232 // (It's a special case of SETHI)
233 let rd = 0, imm22 = 0 in
234 def NOP : F2_1<0b100, (ops), "nop", []>;
236 // Section B.11 - Logical Instructions, p. 106
237 def ANDrr : F3_1<2, 0b000001,
238 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
240 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
241 def ANDri : F3_2<2, 0b000001,
242 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
244 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
245 def ANDNrr : F3_1<2, 0b000101,
246 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
248 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
249 def ANDNri : F3_2<2, 0b000101,
250 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
251 "andn $b, $c, $dst", []>;
252 def ORrr : F3_1<2, 0b000010,
253 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
255 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
256 def ORri : F3_2<2, 0b000010,
257 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
259 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
260 def ORNrr : F3_1<2, 0b000110,
261 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
263 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
264 def ORNri : F3_2<2, 0b000110,
265 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
266 "orn $b, $c, $dst", []>;
267 def XORrr : F3_1<2, 0b000011,
268 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
270 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
271 def XORri : F3_2<2, 0b000011,
272 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
274 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
275 def XNORrr : F3_1<2, 0b000111,
276 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
278 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
279 def XNORri : F3_2<2, 0b000111,
280 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
281 "xnor $b, $c, $dst", []>;
283 // Section B.12 - Shift Instructions, p. 107
284 def SLLrr : F3_1<2, 0b100101,
285 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
287 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
288 def SLLri : F3_2<2, 0b100101,
289 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
291 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
292 def SRLrr : F3_1<2, 0b100110,
293 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
295 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
296 def SRLri : F3_2<2, 0b100110,
297 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
299 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
300 def SRArr : F3_1<2, 0b100111,
301 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
303 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
304 def SRAri : F3_2<2, 0b100111,
305 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
307 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
309 // Section B.13 - Add Instructions, p. 108
310 def ADDrr : F3_1<2, 0b000000,
311 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
313 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
314 def ADDri : F3_2<2, 0b000000,
315 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
317 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
318 def ADDCCrr : F3_1<2, 0b010000,
319 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
320 "addcc $b, $c, $dst", []>;
321 def ADDCCri : F3_2<2, 0b010000,
322 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
323 "addcc $b, $c, $dst", []>;
324 def ADDXrr : F3_1<2, 0b001000,
325 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
326 "addx $b, $c, $dst", []>;
327 def ADDXri : F3_2<2, 0b001000,
328 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
329 "addx $b, $c, $dst", []>;
331 // Section B.15 - Subtract Instructions, p. 110
332 def SUBrr : F3_1<2, 0b000100,
333 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
335 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
336 def SUBri : F3_2<2, 0b000100,
337 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
339 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
340 def SUBXrr : F3_1<2, 0b001100,
341 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
342 "subx $b, $c, $dst", []>;
343 def SUBXri : F3_2<2, 0b001100,
344 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
345 "subx $b, $c, $dst", []>;
346 def SUBCCrr : F3_1<2, 0b010100,
347 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
348 "subcc $b, $c, $dst", []>;
349 def SUBCCri : F3_2<2, 0b010100,
350 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
351 "subcc $b, $c, $dst", []>;
352 def SUBXCCrr: F3_1<2, 0b011100,
353 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
354 "subxcc $b, $c, $dst", []>;
356 // Section B.18 - Multiply Instructions, p. 113
357 def UMULrr : F3_1<2, 0b001010,
358 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
359 "umul $b, $c, $dst", []>;
360 def UMULri : F3_2<2, 0b001010,
361 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
362 "umul $b, $c, $dst", []>;
363 def SMULrr : F3_1<2, 0b001011,
364 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
365 "smul $b, $c, $dst", []>;
366 def SMULri : F3_2<2, 0b001011,
367 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
368 "smul $b, $c, $dst", []>;
370 // Section B.19 - Divide Instructions, p. 115
371 def UDIVrr : F3_1<2, 0b001110,
372 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
373 "udiv $b, $c, $dst", []>;
374 def UDIVri : F3_2<2, 0b001110,
375 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
376 "udiv $b, $c, $dst", []>;
377 def SDIVrr : F3_1<2, 0b001111,
378 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
379 "sdiv $b, $c, $dst", []>;
380 def SDIVri : F3_2<2, 0b001111,
381 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
382 "sdiv $b, $c, $dst", []>;
384 // Section B.20 - SAVE and RESTORE, p. 117
385 def SAVErr : F3_1<2, 0b111100,
386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
387 "save $b, $c, $dst", []>;
388 def SAVEri : F3_2<2, 0b111100,
389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
390 "save $b, $c, $dst", []>;
391 def RESTORErr : F3_1<2, 0b111101,
392 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
393 "restore $b, $c, $dst", []>;
394 def RESTOREri : F3_2<2, 0b111101,
395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
396 "restore $b, $c, $dst", []>;
398 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
400 // conditional branch class:
401 class BranchV8<bits<4> cc, dag ops, string asmstr>
402 : F2_2<cc, 0b010, ops, asmstr> {
404 let isTerminator = 1;
405 let hasDelaySlot = 1;
409 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
410 def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
411 def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
412 def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
413 def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
414 def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
415 def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
416 def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
417 def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
418 def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
419 def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
420 def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
422 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
424 // floating-point conditional branch class:
425 class FPBranchV8<bits<4> cc, dag ops, string asmstr>
426 : F2_2<cc, 0b110, ops, asmstr> {
428 let isTerminator = 1;
429 let hasDelaySlot = 1;
432 def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
433 def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
434 def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
435 def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
436 def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
437 def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
438 def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
439 def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
440 def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
441 def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
442 def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
443 def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
444 def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
445 def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
446 def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
447 def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
451 // Section B.24 - Call and Link Instruction, p. 125
452 // This is the only Format 1 instruction
453 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
455 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
456 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
458 let OperandList = (ops IntRegs:$dst);
461 let Inst{29-0} = disp;
462 let AsmString = "call $dst";
465 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
466 // be an implicit def):
467 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
468 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
469 def JMPLrr : F3_1<2, 0b111000,
470 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
471 "jmpl $b+$c, $dst", []>;
474 // Section B.29 - Write State Register Instructions
475 def WRrr : F3_1<2, 0b110000,
476 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
477 "wr $b, $c, $dst", []>;
478 def WRri : F3_2<2, 0b110000,
479 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
480 "wr $b, $c, $dst", []>;
482 // Convert Integer to Floating-point Instructions, p. 141
483 def FITOS : F3_3<2, 0b110100, 0b011000100,
484 (ops FPRegs:$dst, FPRegs:$src),
486 def FITOD : F3_3<2, 0b110100, 0b011001000,
487 (ops DFPRegs:$dst, DFPRegs:$src),
490 // Convert Floating-point to Integer Instructions, p. 142
491 def FSTOI : F3_3<2, 0b110100, 0b011010001,
492 (ops FPRegs:$dst, FPRegs:$src),
494 def FDTOI : F3_3<2, 0b110100, 0b011010010,
495 (ops DFPRegs:$dst, DFPRegs:$src),
498 // Convert between Floating-point Formats Instructions, p. 143
499 def FSTOD : F3_3<2, 0b110100, 0b011001001,
500 (ops DFPRegs:$dst, FPRegs:$src),
502 def FDTOS : F3_3<2, 0b110100, 0b011000110,
503 (ops FPRegs:$dst, DFPRegs:$src),
506 // Floating-point Move Instructions, p. 144
507 def FMOVS : F3_3<2, 0b110100, 0b000000001,
508 (ops FPRegs:$dst, FPRegs:$src),
510 def FNEGS : F3_3<2, 0b110100, 0b000000101,
511 (ops FPRegs:$dst, FPRegs:$src),
513 def FABSS : F3_3<2, 0b110100, 0b000001001,
514 (ops FPRegs:$dst, FPRegs:$src),
517 // Floating-point Add and Subtract Instructions, p. 146
518 def FADDS : F3_3<2, 0b110100, 0b001000001,
519 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
520 "fadds $src1, $src2, $dst">;
521 def FADDD : F3_3<2, 0b110100, 0b001000010,
522 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
523 "faddd $src1, $src2, $dst">;
524 def FSUBS : F3_3<2, 0b110100, 0b001000101,
525 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
526 "fsubs $src1, $src2, $dst">;
527 def FSUBD : F3_3<2, 0b110100, 0b001000110,
528 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
529 "fsubd $src1, $src2, $dst">;
531 // Floating-point Multiply and Divide Instructions, p. 147
532 def FMULS : F3_3<2, 0b110100, 0b001001001,
533 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
534 "fmuls $src1, $src2, $dst">;
535 def FMULD : F3_3<2, 0b110100, 0b001001010,
536 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
537 "fmuld $src1, $src2, $dst">;
538 def FSMULD : F3_3<2, 0b110100, 0b001101001,
539 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
540 "fsmuld $src1, $src2, $dst">;
541 def FDIVS : F3_3<2, 0b110100, 0b001001101,
542 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
543 "fdivs $src1, $src2, $dst">;
544 def FDIVD : F3_3<2, 0b110100, 0b001001110,
545 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
546 "fdivd $src1, $src2, $dst">;
548 // Floating-point Compare Instructions, p. 148
549 // Note: the 2nd template arg is different for these guys.
550 // Note 2: the result of a FCMP is not available until the 2nd cycle
551 // after the instr is retired, but there is no interlock. This behavior
552 // is modelled with a forced noop after the instruction.
553 def FCMPS : F3_3<2, 0b110101, 0b001010001,
554 (ops FPRegs:$src1, FPRegs:$src2),
555 "fcmps $src1, $src2\n\tnop">;
556 def FCMPD : F3_3<2, 0b110101, 0b001010010,
557 (ops DFPRegs:$src1, DFPRegs:$src2),
558 "fcmpd $src1, $src2\n\tnop">;
560 //===----------------------------------------------------------------------===//
561 // Non-Instruction Patterns
562 //===----------------------------------------------------------------------===//
565 def : Pat<(i32 simm13:$val),
566 (ORri G0, imm:$val)>;
567 // Arbitrary immediates.
568 def : Pat<(i32 imm:$val),
569 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;