1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcV8InstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Instruction Pattern Stuff
22 //===----------------------------------------------------------------------===//
24 def simm13 : PatLeaf<(imm), [{
25 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
26 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
29 def LO10 : SDNodeXForm<imm, [{
30 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
33 def HI22 : SDNodeXForm<imm, [{
34 // Transformation function: shift the immediate value down into the low bits.
35 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
38 def SETHIimm : PatLeaf<(imm), [{
39 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
43 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
44 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
47 def MEMrr : Operand<i32> {
48 let PrintMethod = "printMemOperand";
49 let NumMIOperands = 2;
50 let MIOperandInfo = (ops IntRegs, IntRegs);
52 def MEMri : Operand<i32> {
53 let PrintMethod = "printMemOperand";
54 let NumMIOperands = 2;
55 let MIOperandInfo = (ops IntRegs, i32imm);
58 // Branch targets have OtherVT type.
59 def brtarget : Operand<OtherVT>;
60 def calltarget : Operand<i32>;
63 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
65 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
67 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
68 SDTCisVT<2, FlagVT>]>;
70 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
71 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
73 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
74 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
75 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
76 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
78 def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
79 def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
81 def V8ftoi : SDNode<"V8ISD::FTOI", SDTFPUnaryOp>;
82 def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>;
84 def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
85 def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
87 // These are target-independent nodes, but have target-specific formats.
88 def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
89 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
90 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
92 def SDT_V8Call : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisVT<1, i32>,
93 SDTCisVT<2, FlagVT>]>;
94 def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
96 def SDT_V8RetFlag : SDTypeProfile<0, 1, [ SDTCisVT<0, FlagVT>]>;
97 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
99 //===----------------------------------------------------------------------===//
101 //===----------------------------------------------------------------------===//
103 // Pseudo instructions.
104 class Pseudo<dag ops, string asmstr, list<dag> pattern>
105 : InstV8<ops, asmstr, pattern>;
107 def PHI : Pseudo<(ops variable_ops), "PHI", []>;
108 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
109 "!ADJCALLSTACKDOWN $amt",
110 [(callseq_start imm:$amt)]>;
111 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
112 "!ADJCALLSTACKUP $amt",
113 [(callseq_end imm:$amt)]>;
114 def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
115 "!IMPLICIT_DEF $dst",
116 [(set IntRegs:$dst, (undef))]>;
117 def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
118 [(set FPRegs:$dst, (undef))]>;
119 def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
120 [(set DFPRegs:$dst, (undef))]>;
122 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
124 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
125 "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move
126 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
127 "!FpNEGD $src, $dst",
128 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
129 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
130 "!FpABSD $src, $dst",
131 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
133 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
134 // scheduler into a branch sequence. This has to handle all permutations of
135 // selection between i32/f32/f64 on ICC and FCC.
136 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
137 def SELECT_CC_Int_ICC
138 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
139 "; SELECT_CC_Int_ICC PSEUDO!",
140 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
142 def SELECT_CC_Int_FCC
143 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
144 "; SELECT_CC_Int_FCC PSEUDO!",
145 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
148 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
149 "; SELECT_CC_FP_ICC PSEUDO!",
150 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
153 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
154 "; SELECT_CC_FP_FCC PSEUDO!",
155 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
157 def SELECT_CC_DFP_ICC
158 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
159 "; SELECT_CC_DFP_ICC PSEUDO!",
160 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
162 def SELECT_CC_DFP_FCC
163 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
164 "; SELECT_CC_DFP_FCC PSEUDO!",
165 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
169 // Section A.3 - Synthetic Instructions, p. 85
170 // special cases of JMPL:
171 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
172 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
173 def RETL: F3_2<2, 0b111000, (ops),
177 // Section B.1 - Load Integer Instructions, p. 90
178 def LDSBrr : F3_1<3, 0b001001,
179 (ops IntRegs:$dst, MEMrr:$addr),
180 "ldsb [$addr], $dst",
181 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
182 def LDSBri : F3_2<3, 0b001001,
183 (ops IntRegs:$dst, MEMri:$addr),
184 "ldsb [$addr], $dst",
185 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
186 def LDSHrr : F3_1<3, 0b001010,
187 (ops IntRegs:$dst, MEMrr:$addr),
188 "ldsh [$addr], $dst",
189 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
190 def LDSHri : F3_2<3, 0b001010,
191 (ops IntRegs:$dst, MEMri:$addr),
192 "ldsh [$addr], $dst",
193 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
194 def LDUBrr : F3_1<3, 0b000001,
195 (ops IntRegs:$dst, MEMrr:$addr),
196 "ldub [$addr], $dst",
197 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
198 def LDUBri : F3_2<3, 0b000001,
199 (ops IntRegs:$dst, MEMri:$addr),
200 "ldub [$addr], $dst",
201 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
202 def LDUHrr : F3_1<3, 0b000010,
203 (ops IntRegs:$dst, MEMrr:$addr),
204 "lduh [$addr], $dst",
205 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
206 def LDUHri : F3_2<3, 0b000010,
207 (ops IntRegs:$dst, MEMri:$addr),
208 "lduh [$addr], $dst",
209 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
210 def LDrr : F3_1<3, 0b000000,
211 (ops IntRegs:$dst, MEMrr:$addr),
213 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
214 def LDri : F3_2<3, 0b000000,
215 (ops IntRegs:$dst, MEMri:$addr),
217 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
219 // Section B.2 - Load Floating-point Instructions, p. 92
220 def LDFrr : F3_1<3, 0b100000,
221 (ops FPRegs:$dst, MEMrr:$addr),
223 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
224 def LDFri : F3_2<3, 0b100000,
225 (ops FPRegs:$dst, MEMri:$addr),
227 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
228 def LDDFrr : F3_1<3, 0b100011,
229 (ops DFPRegs:$dst, MEMrr:$addr),
231 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
232 def LDDFri : F3_2<3, 0b100011,
233 (ops DFPRegs:$dst, MEMri:$addr),
235 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
237 // Section B.4 - Store Integer Instructions, p. 95
238 def STBrr : F3_1<3, 0b000101,
239 (ops MEMrr:$addr, IntRegs:$src),
241 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
242 def STBri : F3_2<3, 0b000101,
243 (ops MEMri:$addr, IntRegs:$src),
245 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
246 def STHrr : F3_1<3, 0b000110,
247 (ops MEMrr:$addr, IntRegs:$src),
249 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
250 def STHri : F3_2<3, 0b000110,
251 (ops MEMri:$addr, IntRegs:$src),
253 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
254 def STrr : F3_1<3, 0b000100,
255 (ops MEMrr:$addr, IntRegs:$src),
257 [(store IntRegs:$src, ADDRrr:$addr)]>;
258 def STri : F3_2<3, 0b000100,
259 (ops MEMri:$addr, IntRegs:$src),
261 [(store IntRegs:$src, ADDRri:$addr)]>;
263 // Section B.5 - Store Floating-point Instructions, p. 97
264 def STFrr : F3_1<3, 0b100100,
265 (ops MEMrr:$addr, FPRegs:$src),
267 [(store FPRegs:$src, ADDRrr:$addr)]>;
268 def STFri : F3_2<3, 0b100100,
269 (ops MEMri:$addr, FPRegs:$src),
271 [(store FPRegs:$src, ADDRri:$addr)]>;
272 def STDFrr : F3_1<3, 0b100111,
273 (ops MEMrr:$addr, DFPRegs:$src),
275 [(store DFPRegs:$src, ADDRrr:$addr)]>;
276 def STDFri : F3_2<3, 0b100111,
277 (ops MEMri:$addr, DFPRegs:$src),
279 [(store DFPRegs:$src, ADDRri:$addr)]>;
281 // Section B.9 - SETHI Instruction, p. 104
282 def SETHIi: F2_1<0b100,
283 (ops IntRegs:$dst, i32imm:$src),
285 [(set IntRegs:$dst, SETHIimm:$src)]>;
287 // Section B.10 - NOP Instruction, p. 105
288 // (It's a special case of SETHI)
289 let rd = 0, imm22 = 0 in
290 def NOP : F2_1<0b100, (ops), "nop", []>;
292 // Section B.11 - Logical Instructions, p. 106
293 def ANDrr : F3_1<2, 0b000001,
294 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
296 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
297 def ANDri : F3_2<2, 0b000001,
298 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
300 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
301 def ANDNrr : F3_1<2, 0b000101,
302 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
304 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
305 def ANDNri : F3_2<2, 0b000101,
306 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
307 "andn $b, $c, $dst", []>;
308 def ORrr : F3_1<2, 0b000010,
309 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
311 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
312 def ORri : F3_2<2, 0b000010,
313 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
315 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
316 def ORNrr : F3_1<2, 0b000110,
317 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
319 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
320 def ORNri : F3_2<2, 0b000110,
321 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
322 "orn $b, $c, $dst", []>;
323 def XORrr : F3_1<2, 0b000011,
324 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
326 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
327 def XORri : F3_2<2, 0b000011,
328 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
330 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
331 def XNORrr : F3_1<2, 0b000111,
332 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
334 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
335 def XNORri : F3_2<2, 0b000111,
336 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
337 "xnor $b, $c, $dst", []>;
339 // Section B.12 - Shift Instructions, p. 107
340 def SLLrr : F3_1<2, 0b100101,
341 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
343 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
344 def SLLri : F3_2<2, 0b100101,
345 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
347 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
348 def SRLrr : F3_1<2, 0b100110,
349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
351 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
352 def SRLri : F3_2<2, 0b100110,
353 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
355 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
356 def SRArr : F3_1<2, 0b100111,
357 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
359 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
360 def SRAri : F3_2<2, 0b100111,
361 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
363 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
365 // Section B.13 - Add Instructions, p. 108
366 def ADDrr : F3_1<2, 0b000000,
367 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
369 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
370 def ADDri : F3_2<2, 0b000000,
371 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
373 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
374 def ADDCCrr : F3_1<2, 0b010000,
375 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
376 "addcc $b, $c, $dst", []>;
377 def ADDCCri : F3_2<2, 0b010000,
378 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
379 "addcc $b, $c, $dst", []>;
380 def ADDXrr : F3_1<2, 0b001000,
381 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
382 "addx $b, $c, $dst", []>;
383 def ADDXri : F3_2<2, 0b001000,
384 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
385 "addx $b, $c, $dst", []>;
387 // Section B.15 - Subtract Instructions, p. 110
388 def SUBrr : F3_1<2, 0b000100,
389 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
391 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
392 def SUBri : F3_2<2, 0b000100,
393 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
395 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
396 def SUBXrr : F3_1<2, 0b001100,
397 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
398 "subx $b, $c, $dst", []>;
399 def SUBXri : F3_2<2, 0b001100,
400 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
401 "subx $b, $c, $dst", []>;
402 def SUBCCrr : F3_1<2, 0b010100,
403 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
404 "subcc $b, $c, $dst", []>;
405 def SUBCCri : F3_2<2, 0b010100,
406 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
407 "subcc $b, $c, $dst", []>;
408 def SUBXCCrr: F3_1<2, 0b011100,
409 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
410 "subxcc $b, $c, $dst", []>;
412 // Section B.18 - Multiply Instructions, p. 113
413 def UMULrr : F3_1<2, 0b001010,
414 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
415 "umul $b, $c, $dst", []>;
416 def UMULri : F3_2<2, 0b001010,
417 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
418 "umul $b, $c, $dst", []>;
419 def SMULrr : F3_1<2, 0b001011,
420 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
422 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
423 def SMULri : F3_2<2, 0b001011,
424 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
426 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
428 // Section B.19 - Divide Instructions, p. 115
429 def UDIVrr : F3_1<2, 0b001110,
430 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
431 "udiv $b, $c, $dst", []>;
432 def UDIVri : F3_2<2, 0b001110,
433 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
434 "udiv $b, $c, $dst", []>;
435 def SDIVrr : F3_1<2, 0b001111,
436 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
437 "sdiv $b, $c, $dst", []>;
438 def SDIVri : F3_2<2, 0b001111,
439 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
440 "sdiv $b, $c, $dst", []>;
442 // Section B.20 - SAVE and RESTORE, p. 117
443 def SAVErr : F3_1<2, 0b111100,
444 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
445 "save $b, $c, $dst", []>;
446 def SAVEri : F3_2<2, 0b111100,
447 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
448 "save $b, $c, $dst", []>;
449 def RESTORErr : F3_1<2, 0b111101,
450 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
451 "restore $b, $c, $dst", []>;
452 def RESTOREri : F3_2<2, 0b111101,
453 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
454 "restore $b, $c, $dst", []>;
456 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
458 // conditional branch class:
459 class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
460 : F2_2<cc, 0b010, ops, asmstr, pattern> {
462 let isTerminator = 1;
463 let hasDelaySlot = 1;
467 def BA : BranchV8<0b1000, (ops brtarget:$dst),
470 def BNE : BranchV8<0b1001, (ops brtarget:$dst),
472 [(V8bricc bb:$dst, SETNE, ICC)]>;
473 def BE : BranchV8<0b0001, (ops brtarget:$dst),
475 [(V8bricc bb:$dst, SETEQ, ICC)]>;
476 def BG : BranchV8<0b1010, (ops brtarget:$dst),
478 [(V8bricc bb:$dst, SETGT, ICC)]>;
479 def BLE : BranchV8<0b0010, (ops brtarget:$dst),
481 [(V8bricc bb:$dst, SETLE, ICC)]>;
482 def BGE : BranchV8<0b1011, (ops brtarget:$dst),
484 [(V8bricc bb:$dst, SETGE, ICC)]>;
485 def BL : BranchV8<0b0011, (ops brtarget:$dst),
487 [(V8bricc bb:$dst, SETLT, ICC)]>;
488 def BGU : BranchV8<0b1100, (ops brtarget:$dst),
490 [(V8bricc bb:$dst, SETUGT, ICC)]>;
491 def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
493 [(V8bricc bb:$dst, SETULE, ICC)]>;
494 def BCC : BranchV8<0b1101, (ops brtarget:$dst),
496 [(V8bricc bb:$dst, SETUGE, ICC)]>;
497 def BCS : BranchV8<0b0101, (ops brtarget:$dst),
499 [(V8bricc bb:$dst, SETULT, ICC)]>;
501 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
503 // floating-point conditional branch class:
504 class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
505 : F2_2<cc, 0b110, ops, asmstr, pattern> {
507 let isTerminator = 1;
508 let hasDelaySlot = 1;
511 def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
513 [(V8brfcc bb:$dst, SETUO, FCC)]>;
514 def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
516 [(V8brfcc bb:$dst, SETGT, FCC)]>;
517 def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
519 [(V8brfcc bb:$dst, SETUGT, FCC)]>;
520 def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
522 [(V8brfcc bb:$dst, SETLT, FCC)]>;
523 def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
525 [(V8brfcc bb:$dst, SETULT, FCC)]>;
526 def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
528 [(V8brfcc bb:$dst, SETONE, FCC)]>;
529 def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
531 [(V8brfcc bb:$dst, SETNE, FCC)]>;
532 def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
534 [(V8brfcc bb:$dst, SETEQ, FCC)]>;
535 def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
537 [(V8brfcc bb:$dst, SETUEQ, FCC)]>;
538 def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
540 [(V8brfcc bb:$dst, SETGE, FCC)]>;
541 def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
543 [(V8brfcc bb:$dst, SETUGE, FCC)]>;
544 def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
546 [(V8brfcc bb:$dst, SETLE, FCC)]>;
547 def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
549 [(V8brfcc bb:$dst, SETULE, FCC)]>;
550 def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
552 [(V8brfcc bb:$dst, SETO, FCC)]>;
556 // Section B.24 - Call and Link Instruction, p. 125
557 // This is the only Format 1 instruction
558 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1,
559 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
560 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
562 def CALL : InstV8<(ops calltarget:$dst),
564 [(set ICC/*bogus*/, (call tglobaladdr:$dst, ICC/*bogus*/))]> {
567 let Inst{29-0} = disp;
571 def JMPLrr : F3_1<2, 0b111000,
574 [(set ICC/*bogus*/, (call ADDRrr:$ptr, ICC/*bogus*/))]>;
575 def JMPLri : F3_2<2, 0b111000,
578 [(set ICC/*bogus*/, (call ADDRri:$ptr, ICC/*bogus*/))]>;
581 // Section B.28 - Read State Register Instructions
582 def RDY : F3_1<2, 0b101000,
586 // Section B.29 - Write State Register Instructions
587 def WRYrr : F3_1<2, 0b110000,
588 (ops IntRegs:$b, IntRegs:$c),
589 "wr $b, $c, %y", []>;
590 def WRYri : F3_2<2, 0b110000,
591 (ops IntRegs:$b, i32imm:$c),
592 "wr $b, $c, %y", []>;
594 // Convert Integer to Floating-point Instructions, p. 141
595 def FITOS : F3_3<2, 0b110100, 0b011000100,
596 (ops FPRegs:$dst, FPRegs:$src),
598 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
599 def FITOD : F3_3<2, 0b110100, 0b011001000,
600 (ops DFPRegs:$dst, DFPRegs:$src),
602 [(set DFPRegs:$dst, (V8itof DFPRegs:$src))]>;
604 // Convert Floating-point to Integer Instructions, p. 142
605 def FSTOI : F3_3<2, 0b110100, 0b011010001,
606 (ops FPRegs:$dst, FPRegs:$src),
608 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
609 def FDTOI : F3_3<2, 0b110100, 0b011010010,
610 (ops DFPRegs:$dst, DFPRegs:$src),
612 [(set DFPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
614 // Convert between Floating-point Formats Instructions, p. 143
615 def FSTOD : F3_3<2, 0b110100, 0b011001001,
616 (ops DFPRegs:$dst, FPRegs:$src),
618 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
619 def FDTOS : F3_3<2, 0b110100, 0b011000110,
620 (ops FPRegs:$dst, DFPRegs:$src),
622 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
624 // Floating-point Move Instructions, p. 144
625 def FMOVS : F3_3<2, 0b110100, 0b000000001,
626 (ops FPRegs:$dst, FPRegs:$src),
627 "fmovs $src, $dst", []>;
628 def FNEGS : F3_3<2, 0b110100, 0b000000101,
629 (ops FPRegs:$dst, FPRegs:$src),
631 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
632 def FABSS : F3_3<2, 0b110100, 0b000001001,
633 (ops FPRegs:$dst, FPRegs:$src),
635 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
638 // Floating-point Square Root Instructions, p.145
639 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
640 (ops FPRegs:$dst, FPRegs:$src),
642 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
643 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
644 (ops DFPRegs:$dst, DFPRegs:$src),
646 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
650 // Floating-point Add and Subtract Instructions, p. 146
651 def FADDS : F3_3<2, 0b110100, 0b001000001,
652 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
653 "fadds $src1, $src2, $dst",
654 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
655 def FADDD : F3_3<2, 0b110100, 0b001000010,
656 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
657 "faddd $src1, $src2, $dst",
658 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
659 def FSUBS : F3_3<2, 0b110100, 0b001000101,
660 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
661 "fsubs $src1, $src2, $dst",
662 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
663 def FSUBD : F3_3<2, 0b110100, 0b001000110,
664 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
665 "fsubd $src1, $src2, $dst",
666 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
668 // Floating-point Multiply and Divide Instructions, p. 147
669 def FMULS : F3_3<2, 0b110100, 0b001001001,
670 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
671 "fmuls $src1, $src2, $dst",
672 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
673 def FMULD : F3_3<2, 0b110100, 0b001001010,
674 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
675 "fmuld $src1, $src2, $dst",
676 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
677 def FSMULD : F3_3<2, 0b110100, 0b001101001,
678 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
679 "fsmuld $src1, $src2, $dst",
680 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
681 (fextend FPRegs:$src2)))]>;
682 def FDIVS : F3_3<2, 0b110100, 0b001001101,
683 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
684 "fdivs $src1, $src2, $dst",
685 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
686 def FDIVD : F3_3<2, 0b110100, 0b001001110,
687 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
688 "fdivd $src1, $src2, $dst",
689 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
691 // Floating-point Compare Instructions, p. 148
692 // Note: the 2nd template arg is different for these guys.
693 // Note 2: the result of a FCMP is not available until the 2nd cycle
694 // after the instr is retired, but there is no interlock. This behavior
695 // is modelled with a forced noop after the instruction.
696 def FCMPS : F3_3<2, 0b110101, 0b001010001,
697 (ops FPRegs:$src1, FPRegs:$src2),
698 "fcmps $src1, $src2\n\tnop",
699 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
700 def FCMPD : F3_3<2, 0b110101, 0b001010010,
701 (ops DFPRegs:$src1, DFPRegs:$src2),
702 "fcmpd $src1, $src2\n\tnop",
703 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
705 //===----------------------------------------------------------------------===//
706 // Non-Instruction Patterns
707 //===----------------------------------------------------------------------===//
710 def : Pat<(i32 simm13:$val),
711 (ORri G0, imm:$val)>;
712 // Arbitrary immediates.
713 def : Pat<(i32 imm:$val),
714 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
716 // Global addresses, constant pool entries
717 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
718 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
719 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
720 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
722 // Return of a value, which has an input flag.
723 def : Pat<(retflag ICC/*HACK*/), (RETL)>;
725 // Map integer extload's to zextloads.
726 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
727 def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
728 def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
729 def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
730 def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
731 def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
733 // truncstore bool -> truncstore byte.
734 def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
735 (STBrr IntRegs:$src, ADDRrr:$addr)>;
736 def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
737 (STBri IntRegs:$src, ADDRri:$addr)>;