1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrInfo_F2.td"
32 include "SparcV8InstrInfo_F3.td"
34 //===----------------------------------------------------------------------===//
36 //===----------------------------------------------------------------------===//
38 // Pseudo instructions.
42 def ADJCALLSTACKDOWN : InstV8 {
43 let Name = "ADJCALLSTACKDOWN";
45 def ADJCALLSTACKUP : InstV8 {
46 let Name = "ADJCALLSTACKUP";
49 // Section A.3 - Synthetic Instructions, p. 85
50 let isReturn = 1, isTerminator = 1, simm13 = 8 in
51 def RET : F3_2<2, 0b111000, "ret">;
52 let isReturn = 1, isTerminator = 1, simm13 = 8 in
53 def RETL : F3_2<2, 0b111000, "retl">;
55 // Section B.9 - SETHI Instruction, p. 104
56 def SETHIi: F2_1<0b100, "sethi">;
58 // Section B.11 - Logical Instructions, p. 106
59 def ANDri : F3_2<2, 0b000001, "and">;
60 def ORrr : F3_1<2, 0b000010, "or">;
61 def ORri : F3_2<2, 0b000010, "or">;
63 // Section B.12 - Shift Instructions, p. 107
64 def SLLri : F3_1<2, 0b100101, "sll">;
65 def SRLri : F3_1<2, 0b100110, "srl">;
66 def SRAri : F3_1<2, 0b100111, "sra">;
68 // Section B.13 - Add Instructions, p. 108
69 def ADDrr : F3_1<2, 0b000000, "add">;
71 // Section B.15 - Subtract Instructions, p. 110
72 def SUBrr : F3_1<2, 0b000100, "sub">;
74 // Section B.20 - SAVE and RESTORE, p. 117
75 def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
76 def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
77 def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
78 def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
80 // Section B.24 - Call and Link, p. 125
81 // This is the only Format 1 instruction
85 let Inst{29-0} = disp;
90 // Section B.25 - Jump and Link, p. 126
91 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
92 def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd