1 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/IR/Type.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Target/TargetInstrInfo.h"
26 #define GET_REGINFO_TARGET_DESC
27 #include "SparcGenRegisterInfo.inc"
31 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
32 const TargetInstrInfo &tii)
33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
36 const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
38 static const uint16_t CalleeSavedRegs[] = { 0 };
39 return CalleeSavedRegs;
42 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
43 BitVector Reserved(getNumRegs());
44 // FIXME: G1 reserved for now for large imm generation by frame code.
59 const TargetRegisterClass*
60 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
61 unsigned Kind) const {
62 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
66 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
67 int SPAdj, unsigned FIOperandNum,
68 RegScavenger *RS) const {
69 assert(SPAdj == 0 && "Unexpected");
71 MachineInstr &MI = *II;
72 DebugLoc dl = MI.getDebugLoc();
73 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
75 // Addressable stack objects are accessed using neg. offsets from %fp
76 MachineFunction &MF = *MI.getParent()->getParent();
77 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
78 MI.getOperand(FIOperandNum + 1).getImm() +
79 Subtarget.getStackPointerBias();
81 // Replace frame index with a frame pointer reference.
82 if (Offset >= -4096 && Offset <= 4095) {
83 // If the offset is small enough to fit in the immediate field, directly
85 MI.getOperand(FIOperandNum).ChangeToRegister(SP::I6, false);
86 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
88 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
89 // scavenge a register here instead of reserving G1 all of the time.
90 unsigned OffHi = (unsigned)Offset >> 10U;
91 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
93 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
95 // Insert: G1+%lo(offset) into the user.
96 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
97 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
101 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
105 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
106 llvm_unreachable("What is the exception register");
109 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
110 llvm_unreachable("What is the exception handler register");