1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 Subtarget(st), TII(tii) {
33 void SparcRegisterInfo::
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35 unsigned SrcReg, int FI,
36 const TargetRegisterClass *RC) const {
37 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38 if (RC == SP::IntRegsRegisterClass)
39 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40 .addReg(SrcReg, false, false, true);
41 else if (RC == SP::FPRegsRegisterClass)
42 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43 .addReg(SrcReg, false, false, true);
44 else if (RC == SP::DFPRegsRegisterClass)
45 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46 .addReg(SrcReg, false, false, true);
48 assert(0 && "Can't store this register to stack slot");
51 void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
52 SmallVectorImpl<MachineOperand> &Addr,
53 const TargetRegisterClass *RC,
54 SmallVectorImpl<MachineInstr*> &NewMIs) const {
56 if (RC == SP::IntRegsRegisterClass)
58 else if (RC == SP::FPRegsRegisterClass)
60 else if (RC == SP::DFPRegsRegisterClass)
63 assert(0 && "Can't load this register");
64 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
65 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
66 MachineOperand &MO = Addr[i];
68 MIB.addReg(MO.getReg());
69 else if (MO.isImmediate())
70 MIB.addImm(MO.getImmedValue());
72 MIB.addFrameIndex(MO.getFrameIndex());
74 MIB.addReg(SrcReg, false, false, true);
75 NewMIs.push_back(MIB);
79 void SparcRegisterInfo::
80 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
81 unsigned DestReg, int FI,
82 const TargetRegisterClass *RC) const {
83 if (RC == SP::IntRegsRegisterClass)
84 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
85 else if (RC == SP::FPRegsRegisterClass)
86 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
87 else if (RC == SP::DFPRegsRegisterClass)
88 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
90 assert(0 && "Can't load this register from stack slot");
93 void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
94 SmallVectorImpl<MachineOperand> &Addr,
95 const TargetRegisterClass *RC,
96 SmallVectorImpl<MachineInstr*> &NewMIs) const {
98 if (RC == SP::IntRegsRegisterClass)
100 else if (RC == SP::FPRegsRegisterClass)
102 else if (RC == SP::DFPRegsRegisterClass)
105 assert(0 && "Can't load this register");
106 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
107 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
108 MachineOperand &MO = Addr[i];
110 MIB.addReg(MO.getReg());
111 else if (MO.isImmediate())
112 MIB.addImm(MO.getImmedValue());
114 MIB.addFrameIndex(MO.getFrameIndex());
116 NewMIs.push_back(MIB);
120 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator I,
122 unsigned DestReg, unsigned SrcReg,
123 const TargetRegisterClass *DestRC,
124 const TargetRegisterClass *SrcRC) const {
125 if (DestRC != SrcRC) {
126 cerr << "Not yet supported!";
130 if (DestRC == SP::IntRegsRegisterClass)
131 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
132 else if (DestRC == SP::FPRegsRegisterClass)
133 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
134 else if (DestRC == SP::DFPRegsRegisterClass)
135 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
138 assert (0 && "Can't copy this register");
141 void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
142 MachineBasicBlock::iterator I,
144 const MachineInstr *Orig) const {
145 MachineInstr *MI = Orig->clone();
146 MI->getOperand(0).setReg(DestReg);
150 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
153 bool isFloat = false;
154 MachineInstr *NewMI = NULL;
155 switch (MI->getOpcode()) {
157 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
158 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
159 if (OpNum == 0) // COPY -> STORE
160 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
161 .addReg(MI->getOperand(2).getReg());
163 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
164 .addFrameIndex(FI).addImm(0);
171 if (OpNum == 0) // COPY -> STORE
172 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
173 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
175 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
176 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
181 NewMI->copyKillDeadInfo(MI);
185 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
187 static const unsigned CalleeSavedRegs[] = { 0 };
188 return CalleeSavedRegs;
191 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
192 BitVector Reserved(getNumRegs());
193 Reserved.set(SP::G2);
194 Reserved.set(SP::G3);
195 Reserved.set(SP::G4);
196 Reserved.set(SP::O6);
197 Reserved.set(SP::I6);
198 Reserved.set(SP::I7);
199 Reserved.set(SP::G0);
200 Reserved.set(SP::G5);
201 Reserved.set(SP::G6);
202 Reserved.set(SP::G7);
207 const TargetRegisterClass* const*
208 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
209 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
210 return CalleeSavedRegClasses;
213 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
217 void SparcRegisterInfo::
218 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator I) const {
220 MachineInstr &MI = *I;
221 int Size = MI.getOperand(0).getImmedValue();
222 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
225 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
229 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
230 int SPAdj, RegScavenger *RS) const {
231 assert(SPAdj == 0 && "Unexpected");
234 MachineInstr &MI = *II;
235 while (!MI.getOperand(i).isFrameIndex()) {
237 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
240 int FrameIndex = MI.getOperand(i).getFrameIndex();
242 // Addressable stack objects are accessed using neg. offsets from %fp
243 MachineFunction &MF = *MI.getParent()->getParent();
244 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
245 MI.getOperand(i+1).getImmedValue();
247 // Replace frame index with a frame pointer reference.
248 if (Offset >= -4096 && Offset <= 4095) {
249 // If the offset is small enough to fit in the immediate field, directly
251 MI.getOperand(i).ChangeToRegister(SP::I6, false);
252 MI.getOperand(i+1).ChangeToImmediate(Offset);
254 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
255 // scavenge a register here instead of reserving G1 all of the time.
256 unsigned OffHi = (unsigned)Offset >> 10U;
257 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
259 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
261 // Insert: G1+%lo(offset) into the user.
262 MI.getOperand(i).ChangeToRegister(SP::G1, false);
263 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
267 void SparcRegisterInfo::
268 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
270 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
271 MachineBasicBlock &MBB = MF.front();
272 MachineFrameInfo *MFI = MF.getFrameInfo();
274 // Get the number of bytes to allocate from the FrameInfo
275 int NumBytes = (int) MFI->getStackSize();
277 // Emit the correct save instruction based on the number of bytes in
278 // the frame. Minimum stack frame size according to V8 ABI is:
279 // 16 words for register window spill
280 // 1 word for address of returned aggregate-value
281 // + 6 words for passing parameters on the stack
283 // 23 words * 4 bytes per word = 92 bytes
285 // Round up to next doubleword boundary -- a double-word boundary
286 // is required by the ABI.
287 NumBytes = (NumBytes + 7) & ~7;
288 NumBytes = -NumBytes;
290 if (NumBytes >= -4096) {
291 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
292 SP::O6).addImm(NumBytes).addReg(SP::O6);
294 MachineBasicBlock::iterator InsertPt = MBB.begin();
295 // Emit this the hard way. This clobbers G1 which we always know is
297 unsigned OffHi = (unsigned)NumBytes >> 10U;
298 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
300 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
301 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
302 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
303 .addReg(SP::O6).addReg(SP::G1);
307 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
308 MachineBasicBlock &MBB) const {
309 MachineBasicBlock::iterator MBBI = prior(MBB.end());
310 assert(MBBI->getOpcode() == SP::RETL &&
311 "Can only put epilog before 'retl' instruction!");
312 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
316 unsigned SparcRegisterInfo::getRARegister() const {
317 assert(0 && "What is the return address register");
321 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
322 assert(0 && "What is the frame register");
326 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
327 assert(0 && "What is the exception register");
331 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
332 assert(0 && "What is the exception handler register");
336 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
337 assert(0 && "What is the dwarf register number");
341 #include "SparcGenRegisterInfo.inc"