1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 Subtarget(st), TII(tii) {
33 void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator I,
36 const MachineInstr *Orig) const {
37 MachineInstr *MI = Orig->clone();
38 MI->getOperand(0).setReg(DestReg);
42 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
44 static const unsigned CalleeSavedRegs[] = { 0 };
45 return CalleeSavedRegs;
48 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
49 BitVector Reserved(getNumRegs());
64 const TargetRegisterClass* const*
65 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
66 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
67 return CalleeSavedRegClasses;
70 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
74 void SparcRegisterInfo::
75 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator I) const {
77 MachineInstr &MI = *I;
78 int Size = MI.getOperand(0).getImm();
79 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
82 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
86 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
87 int SPAdj, RegScavenger *RS) const {
88 assert(SPAdj == 0 && "Unexpected");
91 MachineInstr &MI = *II;
92 while (!MI.getOperand(i).isFrameIndex()) {
94 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
97 int FrameIndex = MI.getOperand(i).getIndex();
99 // Addressable stack objects are accessed using neg. offsets from %fp
100 MachineFunction &MF = *MI.getParent()->getParent();
101 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
102 MI.getOperand(i+1).getImm();
104 // Replace frame index with a frame pointer reference.
105 if (Offset >= -4096 && Offset <= 4095) {
106 // If the offset is small enough to fit in the immediate field, directly
108 MI.getOperand(i).ChangeToRegister(SP::I6, false);
109 MI.getOperand(i+1).ChangeToImmediate(Offset);
111 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
112 // scavenge a register here instead of reserving G1 all of the time.
113 unsigned OffHi = (unsigned)Offset >> 10U;
114 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
116 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
118 // Insert: G1+%lo(offset) into the user.
119 MI.getOperand(i).ChangeToRegister(SP::G1, false);
120 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
124 void SparcRegisterInfo::
125 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
127 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
128 MachineBasicBlock &MBB = MF.front();
129 MachineFrameInfo *MFI = MF.getFrameInfo();
131 // Get the number of bytes to allocate from the FrameInfo
132 int NumBytes = (int) MFI->getStackSize();
134 // Emit the correct save instruction based on the number of bytes in
135 // the frame. Minimum stack frame size according to V8 ABI is:
136 // 16 words for register window spill
137 // 1 word for address of returned aggregate-value
138 // + 6 words for passing parameters on the stack
140 // 23 words * 4 bytes per word = 92 bytes
142 // Round up to next doubleword boundary -- a double-word boundary
143 // is required by the ABI.
144 NumBytes = (NumBytes + 7) & ~7;
145 NumBytes = -NumBytes;
147 if (NumBytes >= -4096) {
148 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
149 SP::O6).addImm(NumBytes).addReg(SP::O6);
151 MachineBasicBlock::iterator InsertPt = MBB.begin();
152 // Emit this the hard way. This clobbers G1 which we always know is
154 unsigned OffHi = (unsigned)NumBytes >> 10U;
155 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
157 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
158 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
159 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
160 .addReg(SP::O6).addReg(SP::G1);
164 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
165 MachineBasicBlock &MBB) const {
166 MachineBasicBlock::iterator MBBI = prior(MBB.end());
167 assert(MBBI->getOpcode() == SP::RETL &&
168 "Can only put epilog before 'retl' instruction!");
169 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
173 unsigned SparcRegisterInfo::getRARegister() const {
174 assert(0 && "What is the return address register");
178 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
179 assert(0 && "What is the frame register");
183 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
184 assert(0 && "What is the exception register");
188 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
189 assert(0 && "What is the exception handler register");
193 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
194 assert(0 && "What is the dwarf register number");
198 #include "SparcGenRegisterInfo.inc"