1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Type.h"
20 #include "Support/STLExtras.h"
24 SparcV8RegisterInfo::SparcV8RegisterInfo()
25 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26 V8::ADJCALLSTACKUP) {}
28 int SparcV8RegisterInfo::storeRegToStackSlot(
29 MachineBasicBlock &MBB,
30 MachineBasicBlock::iterator I,
31 unsigned SrcReg, int FrameIdx,
32 const TargetRegisterClass *RC) const
34 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
35 if (RC == SparcV8::IntRegsRegisterClass)
36 BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
38 else if (RC == SparcV8::FPRegsRegisterClass)
39 BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
41 else if (RC == SparcV8::DFPRegsRegisterClass)
42 BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
45 assert (0 && "Can't store this register to stack slot");
49 int SparcV8RegisterInfo::loadRegFromStackSlot(
50 MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator I,
52 unsigned DestReg, int FrameIdx,
53 const TargetRegisterClass *RC) const
55 if (RC == SparcV8::IntRegsRegisterClass)
56 BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
57 else if (RC == SparcV8::FPRegsRegisterClass)
58 BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
60 else if (RC == SparcV8::DFPRegsRegisterClass)
61 BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
64 assert (0 && "Can't load this register from stack slot");
68 int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I,
70 unsigned DestReg, unsigned SrcReg,
71 const TargetRegisterClass *RC) const {
72 if (RC == SparcV8::IntRegsRegisterClass)
73 BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
74 else if (RC == SparcV8::FPRegsRegisterClass)
75 BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
77 assert (0 && "Can't copy this register");
81 void SparcV8RegisterInfo::
82 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator I) const {
85 << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
86 << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
91 SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
92 MachineBasicBlock::iterator II) const {
94 MachineInstr &MI = *II;
95 while (!MI.getOperand(i).isFrameIndex()) {
97 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
100 int FrameIndex = MI.getOperand(i).getFrameIndex();
102 // Replace frame index with a frame pointer reference
103 MI.SetMachineOperandReg (i, V8::FP);
105 // Addressable stack objects are accessed using neg. offsets from %fp
106 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
107 MI.getOperand(i+1).getImmedValue();
109 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
112 void SparcV8RegisterInfo::
113 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
115 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
116 MachineBasicBlock &MBB = MF.front();
117 MachineFrameInfo *MFI = MF.getFrameInfo();
119 // Get the number of bytes to allocate from the FrameInfo
120 int NumBytes = (int) MFI->getStackSize();
122 // Emit the correct save instruction based on the number of bytes in the frame.
123 // Minimum stack frame size according to V8 ABI is:
124 // 16 words for register window spill
125 // 1 word for address of returned aggregate-value
126 // + 6 words for passing parameters on the stack
128 // 23 words * 4 bytes per word = 92 bytes
130 // Round up to next doubleword boundary -- a double-word boundary
131 // is required by the ABI.
132 NumBytes = (NumBytes + 7) & ~7;
133 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
134 V8::SP).addImm(-NumBytes).addReg(V8::SP);
137 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
138 MachineBasicBlock &MBB) const {
139 MachineBasicBlock::iterator MBBI = prior(MBB.end());
140 assert(MBBI->getOpcode() == V8::RETL &&
141 "Can only put epilog before 'retl' instruction!");
142 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
145 #include "SparcV8GenRegisterInfo.inc"
147 const TargetRegisterClass*
148 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
149 switch (Ty->getTypeID()) {
150 case Type::FloatTyID: return &FPRegsInstance;
151 case Type::DoubleTyID: return &DFPRegsInstance;
153 case Type::ULongTyID: assert(0 && "Long values do not fit in registers!");
154 default: assert(0 && "Invalid type to getClass!");
156 case Type::SByteTyID:
157 case Type::UByteTyID:
158 case Type::ShortTyID:
159 case Type::UShortTyID:
162 case Type::PointerTyID: return &IntRegsInstance;