1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Type.h"
24 #include "llvm/ADT/BitVector.h"
25 #include "llvm/ADT/STLExtras.h"
28 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
29 const TargetInstrInfo &tii)
30 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
31 Subtarget(st), TII(tii) {
34 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
36 static const unsigned CalleeSavedRegs[] = { 0 };
37 return CalleeSavedRegs;
40 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
41 BitVector Reserved(getNumRegs());
55 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
59 void SparcRegisterInfo::
60 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator I) const {
62 MachineInstr &MI = *I;
63 DebugLoc dl = MI.getDebugLoc();
64 int Size = MI.getOperand(0).getImm();
65 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
73 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
74 int SPAdj, RegScavenger *RS) const {
75 assert(SPAdj == 0 && "Unexpected");
78 MachineInstr &MI = *II;
79 DebugLoc dl = MI.getDebugLoc();
80 while (!MI.getOperand(i).isFI()) {
82 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
85 int FrameIndex = MI.getOperand(i).getIndex();
87 // Addressable stack objects are accessed using neg. offsets from %fp
88 MachineFunction &MF = *MI.getParent()->getParent();
89 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
90 MI.getOperand(i+1).getImm();
92 // Replace frame index with a frame pointer reference.
93 if (Offset >= -4096 && Offset <= 4095) {
94 // If the offset is small enough to fit in the immediate field, directly
96 MI.getOperand(i).ChangeToRegister(SP::I6, false);
97 MI.getOperand(i+1).ChangeToImmediate(Offset);
99 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
100 // scavenge a register here instead of reserving G1 all of the time.
101 unsigned OffHi = (unsigned)Offset >> 10U;
102 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
104 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
106 // Insert: G1+%lo(offset) into the user.
107 MI.getOperand(i).ChangeToRegister(SP::G1, false);
108 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
112 void SparcRegisterInfo::
113 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
115 unsigned SparcRegisterInfo::getRARegister() const {
119 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
123 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
124 llvm_unreachable("What is the exception register");
128 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
129 llvm_unreachable("What is the exception handler register");
133 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
134 return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
137 #include "SparcGenRegisterInfo.inc"