1 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcRegisterInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/IR/Type.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetInstrInfo.h"
28 #define GET_REGINFO_TARGET_DESC
29 #include "SparcGenRegisterInfo.inc"
34 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
35 cl::desc("Reserve application registers (%g2-%g4)"));
37 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
38 : SparcGenRegisterInfo(SP::I7), Subtarget(st) {
41 const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
47 SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
51 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
52 BitVector Reserved(getNumRegs());
53 // FIXME: G1 reserved for now for large imm generation by frame code.
56 // G1-G4 can be used in applications.
57 if (ReserveAppRegisters) {
62 // G5 is not reserved in 64 bit mode.
63 if (!Subtarget.is64Bit())
73 // Unaliased double registers are not available in non-V9 targets.
74 if (!Subtarget.isV9()) {
75 for (unsigned n = 0; n != 16; ++n) {
76 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
84 const TargetRegisterClass*
85 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
86 unsigned Kind) const {
87 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
91 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
92 int SPAdj, unsigned FIOperandNum,
93 RegScavenger *RS) const {
94 assert(SPAdj == 0 && "Unexpected");
96 MachineInstr &MI = *II;
97 DebugLoc dl = MI.getDebugLoc();
98 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
100 // Addressable stack objects are accessed using neg. offsets from %fp
101 MachineFunction &MF = *MI.getParent()->getParent();
102 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
103 MI.getOperand(FIOperandNum + 1).getImm() +
104 Subtarget.getStackPointerBias();
105 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
106 unsigned FramePtr = SP::I6;
107 if (FuncInfo->isLeafProc()) {
108 // Use %sp and adjust offset if needed.
110 int stackSize = MF.getFrameInfo()->getStackSize();
111 Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
114 // Replace frame index with a frame pointer reference.
115 if (Offset >= -4096 && Offset <= 4095) {
116 // If the offset is small enough to fit in the immediate field, directly
118 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
119 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
121 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
122 // scavenge a register here instead of reserving G1 all of the time.
123 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
124 unsigned OffHi = (unsigned)Offset >> 10U;
125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
127 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
129 // Insert: G1+%lo(offset) into the user.
130 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
131 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
135 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
139 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
140 llvm_unreachable("What is the exception register");
143 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
144 llvm_unreachable("What is the exception handler register");