1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Type.h"
20 #include "Support/STLExtras.h"
23 SparcV8RegisterInfo::SparcV8RegisterInfo()
24 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
25 V8::ADJCALLSTACKUP) {}
27 int SparcV8RegisterInfo::storeRegToStackSlot(
28 MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator I,
30 unsigned SrcReg, int FrameIdx,
31 const TargetRegisterClass *RC) const
33 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
34 if (RC == SparcV8::IntRegsRegisterClass)
35 BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
37 else if (RC == SparcV8::FPRegsRegisterClass)
38 BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
40 else if (RC == SparcV8::DFPRegsRegisterClass)
41 BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
44 assert (0 && "Can't store this register to stack slot");
48 int SparcV8RegisterInfo::loadRegFromStackSlot(
49 MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator I,
51 unsigned DestReg, int FrameIdx,
52 const TargetRegisterClass *RC) const
54 if (RC == SparcV8::IntRegsRegisterClass)
55 BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
56 else if (RC == SparcV8::FPRegsRegisterClass)
57 BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
59 else if (RC == SparcV8::DFPRegsRegisterClass)
60 BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
63 assert (0 && "Can't load this register from stack slot");
67 int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator I,
69 unsigned DestReg, unsigned SrcReg,
70 const TargetRegisterClass *RC) const {
71 if (RC == SparcV8::IntRegsRegisterClass)
72 BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
73 else if (RC == SparcV8::FPRegsRegisterClass)
74 BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
76 assert (0 && "Can't copy this register");
80 void SparcV8RegisterInfo::
81 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator I) const {
84 << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
85 << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
90 SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
91 MachineBasicBlock::iterator II) const {
93 MachineInstr &MI = *II;
94 while (!MI.getOperand(i).isFrameIndex()) {
96 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
99 int FrameIndex = MI.getOperand(i).getFrameIndex();
101 // Replace frame index with a frame pointer reference
102 MI.SetMachineOperandReg (i, V8::FP);
104 // Addressable stack objects are accessed using neg. offsets from %fp
105 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
106 MI.getOperand(i+1).getImmedValue();
108 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
111 void SparcV8RegisterInfo::
112 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
114 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
115 MachineBasicBlock &MBB = MF.front();
116 MachineFrameInfo *MFI = MF.getFrameInfo();
118 // Get the number of bytes to allocate from the FrameInfo
119 int NumBytes = (int) MFI->getStackSize();
121 // Emit the correct save instruction based on the number of bytes in the frame.
122 // Minimum stack frame size according to V8 ABI is:
123 // 16 words for register window spill
124 // 1 word for address of returned aggregate-value
125 // + 6 words for passing parameters on the stack
127 // 23 words * 4 bytes per word = 92 bytes
129 // Round up to next doubleword boundary -- a double-word boundary
130 // is required by the ABI.
131 NumBytes = (NumBytes + 7) & ~7;
132 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
133 V8::SP).addImm(-NumBytes).addReg(V8::SP);
136 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
137 MachineBasicBlock &MBB) const {
138 MachineBasicBlock::iterator MBBI = prior(MBB.end());
139 assert(MBBI->getOpcode() == V8::RETL &&
140 "Can only put epilog before 'retl' instruction!");
141 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
144 #include "SparcV8GenRegisterInfo.inc"
146 const TargetRegisterClass*
147 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
148 switch (Ty->getTypeID()) {
149 case Type::FloatTyID: return &FPRegsInstance;
150 case Type::DoubleTyID: return &DFPRegsInstance;
152 case Type::ULongTyID: assert(0 && "Long values do not fit in registers!");
153 default: assert(0 && "Invalid type to getClass!");
155 case Type::SByteTyID:
156 case Type::UByteTyID:
157 case Type::ShortTyID:
158 case Type::UShortTyID:
161 case Type::PointerTyID: return &IntRegsInstance;