1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/IR/LegacyPassManager.h"
18 #include "llvm/Support/TargetRegistry.h"
21 extern "C" void LLVMInitializeSparcTarget() {
22 // Register the target.
23 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
24 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
25 RegisterTargetMachine<SparcelTargetMachine> Z(TheSparcelTarget);
28 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
29 // Sparc is typically big endian, but some are little.
30 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
33 // Some ABIs have 32bit pointers.
37 // Alignments for 64 bit integers.
40 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
41 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
45 Ret += "-f128:64-n32";
55 /// SparcTargetMachine ctor - Create an ILP32 architecture model
57 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
58 StringRef CPU, StringRef FS,
59 const TargetOptions &Options,
60 Reloc::Model RM, CodeModel::Model CM,
61 CodeGenOpt::Level OL, bool is64bit)
62 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
64 TLOF(make_unique<SparcELFTargetObjectFile>()),
65 Subtarget(TT, CPU, FS, *this, is64bit) {
69 SparcTargetMachine::~SparcTargetMachine() {}
72 /// Sparc Code Generator Pass Configuration Options.
73 class SparcPassConfig : public TargetPassConfig {
75 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
76 : TargetPassConfig(TM, PM) {}
78 SparcTargetMachine &getSparcTargetMachine() const {
79 return getTM<SparcTargetMachine>();
82 void addIRPasses() override;
83 bool addInstSelector() override;
84 void addPreEmitPass() override;
88 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
89 return new SparcPassConfig(this, PM);
92 void SparcPassConfig::addIRPasses() {
93 addPass(createAtomicExpandPass(&getSparcTargetMachine()));
95 TargetPassConfig::addIRPasses();
98 bool SparcPassConfig::addInstSelector() {
99 addPass(createSparcISelDag(getSparcTargetMachine()));
103 void SparcPassConfig::addPreEmitPass(){
104 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
107 void SparcV8TargetMachine::anchor() { }
109 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
110 StringRef CPU, StringRef FS,
111 const TargetOptions &Options,
112 Reloc::Model RM, CodeModel::Model CM,
113 CodeGenOpt::Level OL)
114 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
116 void SparcV9TargetMachine::anchor() { }
118 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
119 StringRef CPU, StringRef FS,
120 const TargetOptions &Options,
121 Reloc::Model RM, CodeModel::Model CM,
122 CodeGenOpt::Level OL)
123 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
125 void SparcelTargetMachine::anchor() {}
127 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
128 StringRef CPU, StringRef FS,
129 const TargetOptions &Options,
130 Reloc::Model RM, CodeModel::Model CM,
131 CodeGenOpt::Level OL)
132 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}