1 //===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Sparc specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef SPARCTARGETMACHINE_H
15 #define SPARCTARGETMACHINE_H
17 #include "SparcFrameLowering.h"
18 #include "SparcISelLowering.h"
19 #include "SparcInstrInfo.h"
20 #include "SparcJITInfo.h"
21 #include "SparcSelectionDAGInfo.h"
22 #include "SparcSubtarget.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetFrameLowering.h"
25 #include "llvm/Target/TargetMachine.h"
29 class SparcTargetMachine : public LLVMTargetMachine {
30 SparcSubtarget Subtarget;
31 const DataLayout DL; // Calculates type size & alignment
32 SparcInstrInfo InstrInfo;
33 SparcTargetLowering TLInfo;
34 SparcSelectionDAGInfo TSInfo;
35 SparcFrameLowering FrameLowering;
38 SparcTargetMachine(const Target &T, StringRef TT,
39 StringRef CPU, StringRef FS, const TargetOptions &Options,
40 Reloc::Model RM, CodeModel::Model CM,
41 CodeGenOpt::Level OL, bool is64bit);
43 virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
44 virtual const TargetFrameLowering *getFrameLowering() const {
45 return &FrameLowering;
47 virtual const SparcSubtarget *getSubtargetImpl() const{ return &Subtarget; }
48 virtual const SparcRegisterInfo *getRegisterInfo() const {
49 return &InstrInfo.getRegisterInfo();
51 virtual const SparcTargetLowering* getTargetLowering() const {
54 virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
57 virtual SparcJITInfo *getJITInfo() {
60 virtual const DataLayout *getDataLayout() const { return &DL; }
62 // Pass Pipeline Configuration
63 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
64 virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
67 /// SparcV8TargetMachine - Sparc 32-bit target machine
69 class SparcV8TargetMachine : public SparcTargetMachine {
70 virtual void anchor();
72 SparcV8TargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
76 CodeGenOpt::Level OL);
79 /// SparcV9TargetMachine - Sparc 64-bit target machine
81 class SparcV9TargetMachine : public SparcTargetMachine {
82 virtual void anchor();
84 SparcV9TargetMachine(const Target &T, StringRef TT,
85 StringRef CPU, StringRef FS,
86 const TargetOptions &Options,
87 Reloc::Model RM, CodeModel::Model CM,
88 CodeGenOpt::Level OL);
91 } // end namespace llvm