1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Instructions.h"
17 #include "llvm/IntrinsicLowering.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Support/GetElementPtrTypeIterator.h"
25 #include "llvm/Support/InstVisitor.h"
26 #include "llvm/Support/CFG.h"
30 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
32 MachineFunction *F; // The function we are compiling into
33 MachineBasicBlock *BB; // The current MBB we are compiling
35 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
37 // MBBMap - Mapping between LLVM BB -> Machine BB
38 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
40 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
42 /// runOnFunction - Top level implementation of instruction selection for
43 /// the entire function.
45 bool runOnFunction(Function &Fn);
47 virtual const char *getPassName() const {
48 return "SparcV8 Simple Instruction Selection";
51 /// visitBasicBlock - This method is called when we are visiting a new basic
52 /// block. This simply creates a new MachineBasicBlock to emit code into
53 /// and adds it to the current MachineFunction. Subsequent visit* for
54 /// instructions will be invoked for all instructions in the basic block.
56 void visitBasicBlock(BasicBlock &LLVM_BB) {
57 BB = MBBMap[&LLVM_BB];
60 void visitBinaryOperator(Instruction &I);
61 void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); }
62 void visitSetCondInst(Instruction &I);
63 void visitCallInst(CallInst &I);
64 void visitReturnInst(ReturnInst &RI);
66 void visitInstruction(Instruction &I) {
67 std::cerr << "Unhandled instruction: " << I;
71 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
72 /// function, lowering any calls to unknown intrinsic functions into the
73 /// equivalent LLVM code.
74 void LowerUnknownIntrinsicFunctionCalls(Function &F);
75 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
77 /// copyConstantToRegister - Output the instructions required to put the
78 /// specified constant into the specified register.
80 void copyConstantToRegister(MachineBasicBlock *MBB,
81 MachineBasicBlock::iterator IP,
82 Constant *C, unsigned R);
84 /// makeAnotherReg - This method returns the next register number we haven't
87 /// Long values are handled somewhat specially. They are always allocated
88 /// as pairs of 32 bit integer values. The register number returned is the
89 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
90 /// of the long value.
92 unsigned makeAnotherReg(const Type *Ty) {
93 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
94 "Current target doesn't have SparcV8 reg info??");
95 const SparcV8RegisterInfo *MRI =
96 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
97 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
98 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
99 // Create the lower part
100 F->getSSARegMap()->createVirtualRegister(RC);
101 // Create the upper part.
102 return F->getSSARegMap()->createVirtualRegister(RC)-1;
105 // Add the mapping of regnumber => reg class to MachineFunction
106 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
107 return F->getSSARegMap()->createVirtualRegister(RC);
110 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
111 unsigned getReg(Value *V) {
112 // Just append to the end of the current bb.
113 MachineBasicBlock::iterator It = BB->end();
114 return getReg(V, BB, It);
116 unsigned getReg(Value *V, MachineBasicBlock *MBB,
117 MachineBasicBlock::iterator IPt) {
118 unsigned &Reg = RegMap[V];
120 Reg = makeAnotherReg(V->getType());
123 // If this operand is a constant, emit the code to copy the constant into
124 // the register here...
126 if (Constant *C = dyn_cast<Constant>(V)) {
127 copyConstantToRegister(MBB, IPt, C, Reg);
128 RegMap.erase(V); // Assign a new name to this constant if ref'd again
129 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
130 // Move the address of the global into the register
131 unsigned TmpReg = makeAnotherReg(V->getType());
132 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
133 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
134 .addGlobalAddress (GV);
135 RegMap.erase(V); // Assign a new name to this address if ref'd again
144 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
145 return new V8ISel(TM);
149 cByte, cShort, cInt, cLong, cFloat, cDouble
152 static TypeClass getClass (const Type *T) {
153 switch (T->getPrimitiveID ()) {
154 case Type::UByteTyID: case Type::SByteTyID: return cByte;
155 case Type::UShortTyID: case Type::ShortTyID: return cShort;
156 case Type::UIntTyID: case Type::IntTyID: return cInt;
157 case Type::ULongTyID: case Type::LongTyID: return cLong;
158 case Type::FloatTyID: return cFloat;
159 case Type::DoubleTyID: return cDouble;
161 assert (0 && "Type of unknown class passed to getClass?");
165 static TypeClass getClassB(const Type *T) {
166 if (T == Type::BoolTy) return cByte;
172 /// copyConstantToRegister - Output the instructions required to put the
173 /// specified constant into the specified register.
175 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
176 MachineBasicBlock::iterator IP,
177 Constant *C, unsigned R) {
178 if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
179 unsigned Class = getClass(C->getType());
180 uint64_t Val = CI->getRawValue ();
183 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
186 unsigned TmpReg = makeAnotherReg (C->getType ());
187 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
188 .addImm (((uint16_t) Val) >> 10);
189 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
190 .addImm (((uint16_t) Val) & 0x03ff);
194 unsigned TmpReg = makeAnotherReg (C->getType ());
195 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
196 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
197 .addImm (((uint32_t) Val) & 0x03ff);
201 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
202 uint32_t topHalf = (uint32_t) (Val >> 32);
203 uint32_t bottomHalf = (uint32_t)Val;
204 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
205 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
206 .addImm (topHalf & 0x03ff);
207 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
208 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
209 .addImm (bottomHalf & 0x03ff);
213 std::cerr << "Offending constant: " << *C << "\n";
214 assert (0 && "Can't copy this kind of constant into register yet");
219 std::cerr << "Offending constant: " << *C << "\n";
220 assert (0 && "Can't copy this kind of constant into register yet");
223 bool V8ISel::runOnFunction(Function &Fn) {
224 // First pass over the function, lower any unknown intrinsic functions
225 // with the IntrinsicLowering class.
226 LowerUnknownIntrinsicFunctionCalls(Fn);
228 F = &MachineFunction::construct(&Fn, TM);
230 // Create all of the machine basic blocks for the function...
231 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
232 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
236 // Set up a frame object for the return address. This is used by the
237 // llvm.returnaddress & llvm.frameaddress intrinisics.
238 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
240 // Copy incoming arguments off of the stack and out of fixed registers.
241 //LoadArgumentsToVirtualRegs(Fn);
243 // Instruction select everything except PHI nodes
246 // Select the PHI nodes
252 // We always build a machine code representation for the function
256 void V8ISel::visitCallInst(CallInst &I) {
257 assert (I.getNumOperands () < 8
258 && "Can't handle pushing excess call args on the stack yet");
259 static const unsigned IncomingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
261 for (unsigned i = 1; i < 7; ++i)
262 if (i < I.getNumOperands ()) {
263 unsigned ArgReg = getReg (I.getOperand (i));
264 // Schlep it over into the incoming arg register
265 BuildMI (BB, V8::ORrr, 2, IncomingArgRegs[i]).addReg (V8::G0)
269 unsigned DestReg = getReg (I);
270 BuildMI (BB, V8::CALL, 1).addPCDisp (I.getOperand (0));
271 if (I.getType ()->getPrimitiveID () == Type::VoidTyID)
273 // Deal w/ return value
274 switch (getClass (I.getType ())) {
278 // Schlep it over into the destination register
279 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
282 visitInstruction (I);
287 void V8ISel::visitReturnInst(ReturnInst &I) {
288 if (I.getNumOperands () == 1) {
289 unsigned RetValReg = getReg (I.getOperand (0));
290 switch (getClass (I.getOperand (0)->getType ())) {
294 // Schlep it over into i0 (where it will become o0 after restore).
295 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
298 visitInstruction (I);
303 // Just emit a 'retl' instruction to return.
304 BuildMI(BB, V8::RETL, 0);
308 void V8ISel::visitBinaryOperator (Instruction &I) {
309 unsigned DestReg = getReg (I);
310 unsigned Op0Reg = getReg (I.getOperand (0));
311 unsigned Op1Reg = getReg (I.getOperand (1));
313 unsigned ResultReg = DestReg;
314 if (getClassB(I.getType()) != cInt)
315 ResultReg = makeAnotherReg (I.getType ());
316 unsigned OpCase = ~0;
318 // FIXME: support long, ulong, fp.
319 switch (I.getOpcode ()) {
320 case Instruction::Add: OpCase = 0; break;
321 case Instruction::Sub: OpCase = 1; break;
322 case Instruction::Mul: OpCase = 2; break;
323 case Instruction::And: OpCase = 3; break;
324 case Instruction::Or: OpCase = 4; break;
325 case Instruction::Xor: OpCase = 5; break;
326 case Instruction::Shl: OpCase = 6; break;
327 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
329 case Instruction::Div:
330 case Instruction::Rem: {
331 unsigned Dest = ResultReg;
332 if (I.getOpcode() == Instruction::Rem)
333 Dest = makeAnotherReg(I.getType());
335 // FIXME: this is probably only right for 32 bit operands.
336 if (I.getType ()->isSigned()) {
337 unsigned Tmp = makeAnotherReg (I.getType ());
338 // Sign extend into the Y register
339 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
340 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
341 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
343 // Zero extend into the Y register, ie, just set it to zero
344 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
345 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
348 if (I.getOpcode() == Instruction::Rem) {
349 unsigned Tmp = makeAnotherReg (I.getType ());
350 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
351 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
356 visitInstruction (I);
361 static const unsigned Opcodes[] = {
362 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
363 V8::SLLrr, V8::SRLrr, V8::SRArr
365 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
368 switch (getClass (I.getType ())) {
370 if (I.getType ()->isSigned ()) { // add byte
371 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
372 } else { // add ubyte
373 unsigned TmpReg = makeAnotherReg (I.getType ());
374 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
375 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
379 if (I.getType ()->isSigned ()) { // add short
380 unsigned TmpReg = makeAnotherReg (I.getType ());
381 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
382 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
383 } else { // add ushort
384 unsigned TmpReg = makeAnotherReg (I.getType ());
385 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
386 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
390 // Nothing todo here.
393 visitInstruction (I);
398 void V8ISel::visitSetCondInst(Instruction &I) {
399 unsigned Op0Reg = getReg (I.getOperand (0));
400 unsigned Op1Reg = getReg (I.getOperand (1));
401 unsigned DestReg = getReg (I);
403 // Compare the two values.
404 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
406 // Put 0 into a register.
407 //unsigned ZeroReg = makeAnotheRReg(Type::IntTy);
408 //BuildMI(BB, V8::ORri, 2, ZeroReg).addReg(V8::G0).addReg(V8::G0);
411 switch (I.getOpcode()) {
412 default: assert(0 && "Unknown setcc instruction!");
413 case Instruction::SetEQ:
414 case Instruction::SetNE:
415 case Instruction::SetLT:
416 case Instruction::SetGT:
417 case Instruction::SetLE:
418 case Instruction::SetGE:
422 // FIXME: We need either conditional moves like the V9 has (e.g. movge), or we
423 // need to be able to turn a single LLVM basic block into multiple machine
424 // code basic blocks. For now, it probably makes sense to emit Sparc V9
425 // instructions until the code generator is upgraded. Note that this should
426 // only happen when the setcc cannot be folded into the branch, but this needs
427 // to be handled correctly!
434 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
435 /// function, lowering any calls to unknown intrinsic functions into the
436 /// equivalent LLVM code.
437 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
438 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
439 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
440 if (CallInst *CI = dyn_cast<CallInst>(I++))
441 if (Function *F = CI->getCalledFunction())
442 switch (F->getIntrinsicID()) {
443 case Intrinsic::not_intrinsic: break;
445 // All other intrinsic calls we must lower.
446 Instruction *Before = CI->getPrev();
447 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
448 if (Before) { // Move iterator to instruction after call
457 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
458 unsigned TmpReg1, TmpReg2;
460 default: assert(0 && "Intrinsic not supported!");