1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Instructions.h"
17 #include "llvm/IntrinsicLowering.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/GetElementPtrTypeIterator.h"
26 #include "llvm/Support/InstVisitor.h"
27 #include "llvm/Support/CFG.h"
31 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
33 MachineFunction *F; // The function we are compiling into
34 MachineBasicBlock *BB; // The current MBB we are compiling
36 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
38 // MBBMap - Mapping between LLVM BB -> Machine BB
39 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
41 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
43 /// runOnFunction - Top level implementation of instruction selection for
44 /// the entire function.
46 bool runOnFunction(Function &Fn);
48 virtual const char *getPassName() const {
49 return "SparcV8 Simple Instruction Selection";
52 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
53 /// constant expression GEP support.
55 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
56 Value *Src, User::op_iterator IdxBegin,
57 User::op_iterator IdxEnd, unsigned TargetReg);
59 /// visitBasicBlock - This method is called when we are visiting a new basic
60 /// block. This simply creates a new MachineBasicBlock to emit code into
61 /// and adds it to the current MachineFunction. Subsequent visit* for
62 /// instructions will be invoked for all instructions in the basic block.
64 void visitBasicBlock(BasicBlock &LLVM_BB) {
65 BB = MBBMap[&LLVM_BB];
68 void visitBinaryOperator(Instruction &I);
69 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
70 void visitSetCondInst(Instruction &I);
71 void visitCallInst(CallInst &I);
72 void visitReturnInst(ReturnInst &I);
73 void visitBranchInst(BranchInst &I);
74 void visitCastInst(CastInst &I);
75 void visitLoadInst(LoadInst &I);
76 void visitStoreInst(StoreInst &I);
77 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
78 void visitGetElementPtrInst(GetElementPtrInst &I);
82 void visitInstruction(Instruction &I) {
83 std::cerr << "Unhandled instruction: " << I;
87 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
88 /// function, lowering any calls to unknown intrinsic functions into the
89 /// equivalent LLVM code.
90 void LowerUnknownIntrinsicFunctionCalls(Function &F);
91 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
93 void LoadArgumentsToVirtualRegs(Function *F);
95 /// copyConstantToRegister - Output the instructions required to put the
96 /// specified constant into the specified register.
98 void copyConstantToRegister(MachineBasicBlock *MBB,
99 MachineBasicBlock::iterator IP,
100 Constant *C, unsigned R);
102 /// makeAnotherReg - This method returns the next register number we haven't
105 /// Long values are handled somewhat specially. They are always allocated
106 /// as pairs of 32 bit integer values. The register number returned is the
107 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
108 /// of the long value.
110 unsigned makeAnotherReg(const Type *Ty) {
111 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
112 "Current target doesn't have SparcV8 reg info??");
113 const SparcV8RegisterInfo *MRI =
114 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
115 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
116 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
117 // Create the lower part
118 F->getSSARegMap()->createVirtualRegister(RC);
119 // Create the upper part.
120 return F->getSSARegMap()->createVirtualRegister(RC)-1;
123 // Add the mapping of regnumber => reg class to MachineFunction
124 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
125 return F->getSSARegMap()->createVirtualRegister(RC);
128 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
129 unsigned getReg(Value *V) {
130 // Just append to the end of the current bb.
131 MachineBasicBlock::iterator It = BB->end();
132 return getReg(V, BB, It);
134 unsigned getReg(Value *V, MachineBasicBlock *MBB,
135 MachineBasicBlock::iterator IPt) {
136 unsigned &Reg = RegMap[V];
138 Reg = makeAnotherReg(V->getType());
141 // If this operand is a constant, emit the code to copy the constant into
142 // the register here...
144 if (Constant *C = dyn_cast<Constant>(V)) {
145 copyConstantToRegister(MBB, IPt, C, Reg);
146 RegMap.erase(V); // Assign a new name to this constant if ref'd again
147 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
148 // Move the address of the global into the register
149 unsigned TmpReg = makeAnotherReg(V->getType());
150 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
151 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
152 .addGlobalAddress (GV);
153 RegMap.erase(V); // Assign a new name to this address if ref'd again
162 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
163 return new V8ISel(TM);
167 cByte, cShort, cInt, cLong, cFloat, cDouble
170 static TypeClass getClass (const Type *T) {
171 switch (T->getPrimitiveID ()) {
172 case Type::UByteTyID: case Type::SByteTyID: return cByte;
173 case Type::UShortTyID: case Type::ShortTyID: return cShort;
174 case Type::PointerTyID:
175 case Type::UIntTyID: case Type::IntTyID: return cInt;
176 case Type::ULongTyID: case Type::LongTyID: return cLong;
177 case Type::FloatTyID: return cFloat;
178 case Type::DoubleTyID: return cDouble;
180 assert (0 && "Type of unknown class passed to getClass?");
184 static TypeClass getClassB(const Type *T) {
185 if (T == Type::BoolTy) return cByte;
191 /// copyConstantToRegister - Output the instructions required to put the
192 /// specified constant into the specified register.
194 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
195 MachineBasicBlock::iterator IP,
196 Constant *C, unsigned R) {
197 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
198 switch (CE->getOpcode()) {
199 case Instruction::GetElementPtr:
200 emitGEPOperation(MBB, IP, CE->getOperand(0),
201 CE->op_begin()+1, CE->op_end(), R);
204 std::cerr << "Copying this constant expr not yet handled: " << *CE;
209 if (C->getType()->isIntegral ()) {
211 unsigned Class = getClassB (C->getType ());
212 if (Class == cLong) {
213 unsigned TmpReg = makeAnotherReg (Type::IntTy);
214 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
215 // Copy the value into the register pair.
216 // R = top(more-significant) half, R+1 = bottom(less-significant) half
217 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
218 unsigned topHalf = Val & 0xffffffffU;
219 unsigned bottomHalf = Val >> 32;
220 unsigned HH = topHalf >> 10;
221 unsigned HM = topHalf & 0x03ff;
222 unsigned LM = bottomHalf >> 10;
223 unsigned LO = bottomHalf & 0x03ff;
224 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(HH);
225 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
227 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg2).addImm(LM);
228 BuildMI (*MBB, IP, V8::ORri, 2, R+1).addReg (TmpReg2)
233 assert(Class <= cInt && "Type not handled yet!");
235 if (C->getType() == Type::BoolTy) {
236 Val = (C == ConstantBool::True);
238 ConstantInt *CI = dyn_cast<ConstantInt> (C);
239 Val = CI->getRawValue ();
243 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
246 unsigned TmpReg = makeAnotherReg (C->getType ());
247 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
248 .addImm (((uint16_t) Val) >> 10);
249 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
250 .addImm (((uint16_t) Val) & 0x03ff);
254 unsigned TmpReg = makeAnotherReg (C->getType ());
255 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
256 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
257 .addImm (((uint32_t) Val) & 0x03ff);
261 std::cerr << "Offending constant: " << *C << "\n";
262 assert (0 && "Can't copy this kind of constant into register yet");
265 } else if (isa<ConstantPointerNull>(C)) {
266 // Copy zero (null pointer) to the register.
267 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm (0);
268 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
269 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
270 // that SETHI %reg,global == SETHI %reg,%hi(global) and
271 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
272 unsigned TmpReg = makeAnotherReg (C->getType ());
273 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress (CPR->getValue());
274 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
275 .addGlobalAddress (CPR->getValue ());
277 std::cerr << "Offending constant: " << *C << "\n";
278 assert (0 && "Can't copy this kind of constant into register yet");
282 void V8ISel::LoadArgumentsToVirtualRegs (Function *F) {
283 unsigned ArgOffset = 0;
284 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
285 V8::I3, V8::I4, V8::I5 };
286 assert (F->asize () < 7
287 && "Can't handle loading excess call args off the stack yet");
289 for (Function::aiterator I = F->abegin(), E = F->aend(); I != E; ++I) {
290 unsigned Reg = getReg(*I);
291 switch (getClassB(I->getType())) {
295 BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
296 .addReg (IncomingArgRegs[ArgOffset]);
299 assert (0 && "Only <=32-bit, integral arguments currently handled");
306 bool V8ISel::runOnFunction(Function &Fn) {
307 // First pass over the function, lower any unknown intrinsic functions
308 // with the IntrinsicLowering class.
309 LowerUnknownIntrinsicFunctionCalls(Fn);
311 F = &MachineFunction::construct(&Fn, TM);
313 // Create all of the machine basic blocks for the function...
314 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
315 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
319 // Set up a frame object for the return address. This is used by the
320 // llvm.returnaddress & llvm.frameaddress intrinisics.
321 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
323 // Copy incoming arguments off of the stack and out of fixed registers.
324 LoadArgumentsToVirtualRegs(&Fn);
326 // Instruction select everything except PHI nodes
329 // Select the PHI nodes
335 // We always build a machine code representation for the function
339 void V8ISel::visitCastInst(CastInst &I) {
340 unsigned SrcReg = getReg (I.getOperand (0));
341 unsigned DestReg = getReg (I);
342 const Type *oldTy = I.getOperand (0)->getType ();
343 const Type *newTy = I.getType ();
344 unsigned oldTyClass = getClassB (oldTy);
345 unsigned newTyClass = getClassB (newTy);
347 if (oldTyClass < cLong && newTyClass < cLong) {
348 if (oldTyClass >= newTyClass) {
349 // Emit a reg->reg copy to do a equal-size or narrowing cast,
350 // and do sign/zero extension (necessary if we change signedness).
351 unsigned TmpReg1 = makeAnotherReg (newTy);
352 unsigned TmpReg2 = makeAnotherReg (newTy);
353 BuildMI (BB, V8::ORrr, 2, TmpReg1).addReg (V8::G0).addReg (SrcReg);
354 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
355 BuildMI (BB, V8::SLLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
356 if (newTy->isSigned ()) { // sign-extend with SRA
357 BuildMI(BB, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
358 } else { // zero-extend with SRL
359 BuildMI(BB, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
362 unsigned TmpReg1 = makeAnotherReg (oldTy);
363 unsigned TmpReg2 = makeAnotherReg (newTy);
364 unsigned TmpReg3 = makeAnotherReg (newTy);
365 // Widening integer cast. Make sure it's fully sign/zero-extended
366 // wrt the input type, then make sure it's fully sign/zero-extended wrt
367 // the output type. Kind of stupid, but simple...
368 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (oldTy));
369 BuildMI (BB, V8::SLLri, 2, TmpReg1).addZImm (shiftWidth).addReg(SrcReg);
370 if (oldTy->isSigned ()) { // sign-extend with SRA
371 BuildMI(BB, V8::SRAri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
372 } else { // zero-extend with SRL
373 BuildMI(BB, V8::SRLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
375 shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
376 BuildMI (BB, V8::SLLri, 2, TmpReg3).addZImm (shiftWidth).addReg(TmpReg2);
377 if (newTy->isSigned ()) { // sign-extend with SRA
378 BuildMI(BB, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
379 } else { // zero-extend with SRL
380 BuildMI(BB, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
384 std::cerr << "Casts w/ long, fp, double still unsupported: " << I;
389 void V8ISel::visitLoadInst(LoadInst &I) {
390 unsigned DestReg = getReg (I);
391 unsigned PtrReg = getReg (I.getOperand (0));
392 switch (getClassB (I.getType ())) {
394 if (I.getType ()->isSigned ())
395 BuildMI (BB, V8::LDSBmr, 1, DestReg).addReg (PtrReg).addSImm(0);
397 BuildMI (BB, V8::LDUBmr, 1, DestReg).addReg (PtrReg).addSImm(0);
400 if (I.getType ()->isSigned ())
401 BuildMI (BB, V8::LDSHmr, 1, DestReg).addReg (PtrReg).addSImm(0);
403 BuildMI (BB, V8::LDUHmr, 1, DestReg).addReg (PtrReg).addSImm(0);
406 BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
409 BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
412 std::cerr << "Load instruction not handled: " << I;
418 void V8ISel::visitStoreInst(StoreInst &I) {
419 Value *SrcVal = I.getOperand (0);
420 unsigned SrcReg = getReg (SrcVal);
421 unsigned PtrReg = getReg (I.getOperand (1));
422 switch (getClassB (SrcVal->getType ())) {
424 BuildMI (BB, V8::STBrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
427 BuildMI (BB, V8::STHrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
430 BuildMI (BB, V8::STrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
433 BuildMI (BB, V8::STDrm, 1, SrcReg).addReg (PtrReg).addSImm(0);
436 std::cerr << "Store instruction not handled: " << I;
442 void V8ISel::visitCallInst(CallInst &I) {
443 assert (I.getNumOperands () < 8
444 && "Can't handle pushing excess call args on the stack yet");
445 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
447 for (unsigned i = 1; i < 7; ++i)
448 if (i < I.getNumOperands ()) {
449 unsigned ArgReg = getReg (I.getOperand (i));
450 // Schlep it over into the incoming arg register
451 BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0)
455 BuildMI (BB, V8::CALL, 1).addPCDisp (I.getOperand (0));
456 if (I.getType () == Type::VoidTy)
458 unsigned DestReg = getReg (I);
459 // Deal w/ return value
460 switch (getClass (I.getType ())) {
464 // Schlep it over into the destination register
465 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
468 std::cerr << "Return type of call instruction not handled: " << I;
473 void V8ISel::visitReturnInst(ReturnInst &I) {
474 if (I.getNumOperands () == 1) {
475 unsigned RetValReg = getReg (I.getOperand (0));
476 switch (getClass (I.getOperand (0)->getType ())) {
480 // Schlep it over into i0 (where it will become o0 after restore).
481 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
484 std::cerr << "Return instruction of this type not handled: " << I;
489 // Just emit a 'retl' instruction to return.
490 BuildMI(BB, V8::RETL, 0);
494 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
495 Function::iterator I = BB; ++I; // Get iterator to next block
496 return I != BB->getParent()->end() ? &*I : 0;
499 /// visitBranchInst - Handles conditional and unconditional branches.
501 void V8ISel::visitBranchInst(BranchInst &I) {
502 // Update machine-CFG edges
503 BB->addSuccessor (MBBMap[I.getSuccessor(0)]);
504 if (I.isConditional())
505 BB->addSuccessor (MBBMap[I.getSuccessor(1)]);
507 BasicBlock *NextBB = getBlockAfter(I.getParent()); // BB after current one
509 BasicBlock *takenSucc = I.getSuccessor (0);
510 if (!I.isConditional()) { // Unconditional branch?
511 if (I.getSuccessor(0) != NextBB)
512 BuildMI (BB, V8::BA, 1).addPCDisp (takenSucc);
516 unsigned CondReg = getReg (I.getCondition ());
517 BasicBlock *notTakenSucc = I.getSuccessor (1);
518 // Set Z condition code if CondReg was false
519 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
520 if (notTakenSucc == NextBB) {
521 if (takenSucc != NextBB)
522 BuildMI (BB, V8::BNE, 1).addPCDisp (takenSucc);
524 BuildMI (BB, V8::BE, 1).addPCDisp (notTakenSucc);
525 if (takenSucc != NextBB)
526 BuildMI (BB, V8::BA, 1).addPCDisp (takenSucc);
530 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
531 /// constant expression GEP support.
533 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
534 MachineBasicBlock::iterator IP,
535 Value *Src, User::op_iterator IdxBegin,
536 User::op_iterator IdxEnd, unsigned TargetReg) {
537 const TargetData &TD = TM.getTargetData ();
538 const Type *Ty = Src->getType ();
539 unsigned basePtrReg = getReg (Src);
541 // GEPs have zero or more indices; we must perform a struct access
542 // or array access for each one.
543 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
546 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
547 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
548 // It's a struct access. idx is the index into the structure,
549 // which names the field. Use the TargetData structure to
550 // pick out what the layout of the structure is in memory.
551 // Use the (constant) structure index's value to find the
552 // right byte offset from the StructLayout class's list of
553 // structure member offsets.
554 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
555 unsigned memberOffset =
556 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
557 // Emit an ADD to add memberOffset to the basePtr.
558 BuildMI (*MBB, IP, V8::ADDri, 2,
559 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
560 // The next type is the member of the structure selected by the
562 Ty = StTy->getElementType (fieldIndex);
563 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
564 // It's an array or pointer access: [ArraySize x ElementType].
565 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
566 // must find the size of the pointed-to type (Not coincidentally, the next
567 // type is the type of the elements in the array).
568 Ty = SqTy->getElementType ();
569 unsigned elementSize = TD.getTypeSize (Ty);
570 unsigned idxReg = getReg (idx, MBB, IP);
571 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
572 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
573 BuildMI (*MBB, IP, V8::ORri, 2,
574 elementSizeReg).addZImm (elementSize).addReg (V8::G0);
575 // Emit a SMUL to multiply the register holding the index by
576 // elementSize, putting the result in OffsetReg.
577 BuildMI (*MBB, IP, V8::SMULrr, 2,
578 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
579 // Emit an ADD to add OffsetReg to the basePtr.
580 BuildMI (*MBB, IP, V8::ADDrr, 2,
581 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
583 basePtrReg = nextBasePtrReg;
585 // After we have processed all the indices, the result is left in
586 // basePtrReg. Move it to the register where we were expected to
588 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
591 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
592 unsigned outputReg = getReg (I);
593 emitGEPOperation (BB, BB->end (), I.getOperand (0),
594 I.op_begin ()+1, I.op_end (), outputReg);
598 void V8ISel::visitBinaryOperator (Instruction &I) {
599 unsigned DestReg = getReg (I);
600 unsigned Op0Reg = getReg (I.getOperand (0));
601 unsigned Op1Reg = getReg (I.getOperand (1));
603 unsigned ResultReg = DestReg;
604 if (getClassB(I.getType()) != cInt)
605 ResultReg = makeAnotherReg (I.getType ());
606 unsigned OpCase = ~0;
608 // FIXME: support long, ulong, fp.
609 switch (I.getOpcode ()) {
610 case Instruction::Add: OpCase = 0; break;
611 case Instruction::Sub: OpCase = 1; break;
612 case Instruction::Mul: OpCase = 2; break;
613 case Instruction::And: OpCase = 3; break;
614 case Instruction::Or: OpCase = 4; break;
615 case Instruction::Xor: OpCase = 5; break;
616 case Instruction::Shl: OpCase = 6; break;
617 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
619 case Instruction::Div:
620 case Instruction::Rem: {
621 unsigned Dest = ResultReg;
622 if (I.getOpcode() == Instruction::Rem)
623 Dest = makeAnotherReg(I.getType());
625 // FIXME: this is probably only right for 32 bit operands.
626 if (I.getType ()->isSigned()) {
627 unsigned Tmp = makeAnotherReg (I.getType ());
628 // Sign extend into the Y register
629 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
630 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
631 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
633 // Zero extend into the Y register, ie, just set it to zero
634 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
635 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
638 if (I.getOpcode() == Instruction::Rem) {
639 unsigned Tmp = makeAnotherReg (I.getType ());
640 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
641 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
646 visitInstruction (I);
651 static const unsigned Opcodes[] = {
652 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
653 V8::SLLrr, V8::SRLrr, V8::SRArr
655 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
658 switch (getClass (I.getType ())) {
660 if (I.getType ()->isSigned ()) { // add byte
661 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
662 } else { // add ubyte
663 unsigned TmpReg = makeAnotherReg (I.getType ());
664 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
665 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
669 if (I.getType ()->isSigned ()) { // add short
670 unsigned TmpReg = makeAnotherReg (I.getType ());
671 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
672 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
673 } else { // add ushort
674 unsigned TmpReg = makeAnotherReg (I.getType ());
675 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
676 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
680 // Nothing todo here.
683 visitInstruction (I);
688 void V8ISel::visitSetCondInst(Instruction &I) {
689 unsigned Op0Reg = getReg (I.getOperand (0));
690 unsigned Op1Reg = getReg (I.getOperand (1));
691 unsigned DestReg = getReg (I);
692 const Type *Ty = I.getOperand (0)->getType ();
694 // Compare the two values.
695 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
698 switch (I.getOpcode()) {
699 default: assert(0 && "Unknown setcc instruction!");
700 case Instruction::SetEQ: BranchIdx = 0; break;
701 case Instruction::SetNE: BranchIdx = 1; break;
702 case Instruction::SetLT: BranchIdx = 2; break;
703 case Instruction::SetGT: BranchIdx = 3; break;
704 case Instruction::SetLE: BranchIdx = 4; break;
705 case Instruction::SetGE: BranchIdx = 5; break;
707 static unsigned OpcodeTab[12] = {
710 V8::BE, V8::BE, // seteq = be be
711 V8::BNE, V8::BNE, // setne = bne bne
712 V8::BCS, V8::BL, // setlt = bcs bl
713 V8::BGU, V8::BG, // setgt = bgu bg
714 V8::BLEU, V8::BLE, // setle = bleu ble
715 V8::BCC, V8::BGE // setge = bcc bge
717 unsigned Opcode = OpcodeTab[BranchIdx + (Ty->isSigned() ? 1 : 0)];
718 MachineBasicBlock *Copy1MBB, *Copy0MBB, *CopyCondMBB;
719 MachineBasicBlock::iterator IP;
721 // Cond. Branch from BB --> either Copy1MBB or Copy0MBB --> CopyCondMBB
722 // Then once we're done with the SetCC, BB = CopyCondMBB.
723 BasicBlock *LLVM_BB = BB.getBasicBlock ();
724 unsigned Cond0Reg = makeAnotherReg (I.getType ());
725 unsigned Cond1Reg = makeAnotherReg (I.getType ());
726 F->getBasicBlockList ().push_back (Copy1MBB = new MachineBasicBlock (LLVM_BB));
727 F->getBasicBlockList ().push_back (Copy0MBB = new MachineBasicBlock (LLVM_BB));
728 F->getBasicBlockList ().push_back (CopyCondMBB = new MachineBasicBlock (LLVM_BB));
729 BuildMI (BB, Opcode, 1).addMBB (Copy1MBB);
730 BuildMI (BB, V8::BA, 1).addMBB (Copy0MBB);
731 IP = Copy1MBB->begin ();
732 BuildMI (*Copy1MBB, IP, V8::ORri, 2, Cond1Reg).addZImm (1).addReg (V8::G0);
733 BuildMI (*Copy1MBB, IP, V8::BA, 1).addMBB (CopyCondMBB);
734 IP = Copy0MBB->begin ();
735 BuildMI (*Copy0MBB, IP, V8::ORri, 2, Cond0Reg).addZImm (0).addReg (V8::G0);
736 BuildMI (*Copy0MBB, IP, V8::BA, 1).addMBB (CopyCondMBB);
737 // What should go in CopyCondMBB: PHI, then OR to copy cond. reg to DestReg
744 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
745 /// function, lowering any calls to unknown intrinsic functions into the
746 /// equivalent LLVM code.
747 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
748 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
749 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
750 if (CallInst *CI = dyn_cast<CallInst>(I++))
751 if (Function *F = CI->getCalledFunction())
752 switch (F->getIntrinsicID()) {
753 case Intrinsic::not_intrinsic: break;
755 // All other intrinsic calls we must lower.
756 Instruction *Before = CI->getPrev();
757 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
758 if (Before) { // Move iterator to instruction after call
767 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
768 unsigned TmpReg1, TmpReg2;
770 default: assert(0 && "Intrinsic not supported!");