1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
34 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
36 MachineFunction *F; // The function we are compiling into
37 MachineBasicBlock *BB; // The current MBB we are compiling
39 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
41 // MBBMap - Mapping between LLVM BB -> Machine BB
42 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
44 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
46 /// runOnFunction - Top level implementation of instruction selection for
47 /// the entire function.
49 bool runOnFunction(Function &Fn);
51 virtual const char *getPassName() const {
52 return "SparcV8 Simple Instruction Selection";
55 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
56 /// constant expression GEP support.
58 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
59 Value *Src, User::op_iterator IdxBegin,
60 User::op_iterator IdxEnd, unsigned TargetReg);
62 /// emitCastOperation - Common code shared between visitCastInst and
63 /// constant expression cast support.
65 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
66 Value *Src, const Type *DestTy, unsigned TargetReg);
68 /// visitBasicBlock - This method is called when we are visiting a new basic
69 /// block. This simply creates a new MachineBasicBlock to emit code into
70 /// and adds it to the current MachineFunction. Subsequent visit* for
71 /// instructions will be invoked for all instructions in the basic block.
73 void visitBasicBlock(BasicBlock &LLVM_BB) {
74 BB = MBBMap[&LLVM_BB];
77 void visitBinaryOperator(Instruction &I);
78 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
79 void visitSetCondInst(SetCondInst &I);
80 void visitCallInst(CallInst &I);
81 void visitReturnInst(ReturnInst &I);
82 void visitBranchInst(BranchInst &I);
83 void visitCastInst(CastInst &I);
84 void visitLoadInst(LoadInst &I);
85 void visitStoreInst(StoreInst &I);
86 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
87 void visitGetElementPtrInst(GetElementPtrInst &I);
88 void visitAllocaInst(AllocaInst &I);
90 void visitInstruction(Instruction &I) {
91 std::cerr << "Unhandled instruction: " << I;
95 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
96 /// function, lowering any calls to unknown intrinsic functions into the
97 /// equivalent LLVM code.
98 void LowerUnknownIntrinsicFunctionCalls(Function &F);
99 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
101 void LoadArgumentsToVirtualRegs(Function *F);
103 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
104 /// because we have to generate our sources into the source basic blocks,
105 /// not the current one.
107 void SelectPHINodes();
109 /// copyConstantToRegister - Output the instructions required to put the
110 /// specified constant into the specified register.
112 void copyConstantToRegister(MachineBasicBlock *MBB,
113 MachineBasicBlock::iterator IP,
114 Constant *C, unsigned R);
116 /// makeAnotherReg - This method returns the next register number we haven't
119 /// Long values are handled somewhat specially. They are always allocated
120 /// as pairs of 32 bit integer values. The register number returned is the
121 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
122 /// of the long value.
124 unsigned makeAnotherReg(const Type *Ty) {
125 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
126 "Current target doesn't have SparcV8 reg info??");
127 const SparcV8RegisterInfo *MRI =
128 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
129 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
130 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
131 // Create the lower part
132 F->getSSARegMap()->createVirtualRegister(RC);
133 // Create the upper part.
134 return F->getSSARegMap()->createVirtualRegister(RC)-1;
137 // Add the mapping of regnumber => reg class to MachineFunction
138 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
139 return F->getSSARegMap()->createVirtualRegister(RC);
142 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
143 unsigned getReg(Value *V) {
144 // Just append to the end of the current bb.
145 MachineBasicBlock::iterator It = BB->end();
146 return getReg(V, BB, It);
148 unsigned getReg(Value *V, MachineBasicBlock *MBB,
149 MachineBasicBlock::iterator IPt) {
150 unsigned &Reg = RegMap[V];
152 Reg = makeAnotherReg(V->getType());
155 // If this operand is a constant, emit the code to copy the constant into
156 // the register here...
158 if (Constant *C = dyn_cast<Constant>(V)) {
159 copyConstantToRegister(MBB, IPt, C, Reg);
160 RegMap.erase(V); // Assign a new name to this constant if ref'd again
161 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
162 // Move the address of the global into the register
163 unsigned TmpReg = makeAnotherReg(V->getType());
164 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
165 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
166 .addGlobalAddress (GV);
167 RegMap.erase(V); // Assign a new name to this address if ref'd again
176 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
177 return new V8ISel(TM);
181 cByte, cShort, cInt, cLong, cFloat, cDouble
184 static TypeClass getClass (const Type *T) {
185 switch (T->getTypeID()) {
186 case Type::UByteTyID: case Type::SByteTyID: return cByte;
187 case Type::UShortTyID: case Type::ShortTyID: return cShort;
188 case Type::PointerTyID:
189 case Type::UIntTyID: case Type::IntTyID: return cInt;
190 case Type::ULongTyID: case Type::LongTyID: return cLong;
191 case Type::FloatTyID: return cFloat;
192 case Type::DoubleTyID: return cDouble;
194 assert (0 && "Type of unknown class passed to getClass?");
198 static TypeClass getClassB(const Type *T) {
199 if (T == Type::BoolTy) return cByte;
205 /// copyConstantToRegister - Output the instructions required to put the
206 /// specified constant into the specified register.
208 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
209 MachineBasicBlock::iterator IP,
210 Constant *C, unsigned R) {
211 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
212 switch (CE->getOpcode()) {
213 case Instruction::GetElementPtr:
214 emitGEPOperation(MBB, IP, CE->getOperand(0),
215 CE->op_begin()+1, CE->op_end(), R);
217 case Instruction::Cast:
218 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
221 std::cerr << "Copying this constant expr not yet handled: " << *CE;
226 if (C->getType()->isIntegral ()) {
228 unsigned Class = getClassB (C->getType ());
229 if (Class == cLong) {
230 unsigned TmpReg = makeAnotherReg (Type::IntTy);
231 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
232 // Copy the value into the register pair.
233 // R = top(more-significant) half, R+1 = bottom(less-significant) half
234 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
235 unsigned topHalf = Val & 0xffffffffU;
236 unsigned bottomHalf = Val >> 32;
237 unsigned HH = topHalf >> 10;
238 unsigned HM = topHalf & 0x03ff;
239 unsigned LM = bottomHalf >> 10;
240 unsigned LO = bottomHalf & 0x03ff;
241 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addZImm(HH);
242 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
244 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg2).addZImm(LM);
245 BuildMI (*MBB, IP, V8::ORri, 2, R+1).addReg (TmpReg2)
250 assert(Class <= cInt && "Type not handled yet!");
252 if (C->getType() == Type::BoolTy) {
253 Val = (C == ConstantBool::True);
255 ConstantInt *CI = cast<ConstantInt> (C);
256 Val = CI->getRawValue ();
259 case cByte: Val = (int8_t) Val; break;
260 case cShort: Val = (int16_t) Val; break;
261 case cInt: Val = (int32_t) Val; break;
263 std::cerr << "Offending constant: " << *C << "\n";
264 assert (0 && "Can't copy this kind of constant into register yet");
268 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
269 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
270 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
272 unsigned TmpReg = makeAnotherReg (C->getType ());
273 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
274 .addSImm (((uint32_t) Val) >> 10);
275 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
276 .addSImm (((uint32_t) Val) & 0x03ff);
279 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
280 // We need to spill the constant to memory...
281 MachineConstantPool *CP = F->getConstantPool();
282 unsigned CPI = CP->getConstantPoolIndex(CFP);
283 const Type *Ty = CFP->getType();
285 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
286 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
287 BuildMI (*MBB, IP, LoadOpcode, 2, R).addConstantPoolIndex (CPI).addSImm (0);
288 } else if (isa<ConstantPointerNull>(C)) {
289 // Copy zero (null pointer) to the register.
290 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
291 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
292 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
293 // that SETHI %reg,global == SETHI %reg,%hi(global) and
294 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
295 unsigned TmpReg = makeAnotherReg (C->getType ());
296 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress (CPR->getValue());
297 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
298 .addGlobalAddress (CPR->getValue ());
300 std::cerr << "Offending constant: " << *C << "\n";
301 assert (0 && "Can't copy this kind of constant into register yet");
305 void V8ISel::LoadArgumentsToVirtualRegs (Function *F) {
306 unsigned ArgOffset = 0;
307 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
308 V8::I3, V8::I4, V8::I5 };
309 assert (F->asize () < 7
310 && "Can't handle loading excess call args off the stack yet");
312 for (Function::aiterator I = F->abegin(), E = F->aend(); I != E; ++I) {
313 unsigned Reg = getReg(*I);
314 switch (getClassB(I->getType())) {
318 BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
319 .addReg (IncomingArgRegs[ArgOffset]);
322 assert (0 && "Only <=32-bit, integral arguments currently handled");
329 void V8ISel::SelectPHINodes() {
330 const TargetInstrInfo &TII = *TM.getInstrInfo();
331 const Function &LF = *F->getFunction(); // The LLVM function...
332 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
333 const BasicBlock *BB = I;
334 MachineBasicBlock &MBB = *MBBMap[I];
336 // Loop over all of the PHI nodes in the LLVM basic block...
337 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
338 for (BasicBlock::const_iterator I = BB->begin();
339 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
341 // Create a new machine instr PHI node, and insert it.
342 unsigned PHIReg = getReg(*PN);
343 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
344 V8::PHI, PN->getNumOperands(), PHIReg);
346 MachineInstr *LongPhiMI = 0;
347 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
348 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
349 V8::PHI, PN->getNumOperands(), PHIReg+1);
351 // PHIValues - Map of blocks to incoming virtual registers. We use this
352 // so that we only initialize one incoming value for a particular block,
353 // even if the block has multiple entries in the PHI node.
355 std::map<MachineBasicBlock*, unsigned> PHIValues;
357 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
358 MachineBasicBlock *PredMBB = 0;
359 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
360 PE = MBB.pred_end (); PI != PE; ++PI)
361 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
365 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
368 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
369 PHIValues.lower_bound(PredMBB);
371 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
372 // We already inserted an initialization of the register for this
373 // predecessor. Recycle it.
374 ValReg = EntryIt->second;
377 // Get the incoming value into a virtual register.
379 Value *Val = PN->getIncomingValue(i);
381 // If this is a constant or GlobalValue, we may have to insert code
382 // into the basic block to compute it into a virtual register.
383 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
384 isa<GlobalValue>(Val)) {
385 // Simple constants get emitted at the end of the basic block,
386 // before any terminator instructions. We "know" that the code to
387 // move a constant into a register will never clobber any flags.
388 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
390 // Because we don't want to clobber any values which might be in
391 // physical registers with the computation of this constant (which
392 // might be arbitrarily complex if it is a constant expression),
393 // just insert the computation at the top of the basic block.
394 MachineBasicBlock::iterator PI = PredMBB->begin();
396 // Skip over any PHI nodes though!
397 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
400 ValReg = getReg(Val, PredMBB, PI);
403 // Remember that we inserted a value for this PHI for this predecessor
404 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
407 PhiMI->addRegOperand(ValReg);
408 PhiMI->addMachineBasicBlockOperand(PredMBB);
410 LongPhiMI->addRegOperand(ValReg+1);
411 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
415 // Now that we emitted all of the incoming values for the PHI node, make
416 // sure to reposition the InsertPoint after the PHI that we just added.
417 // This is needed because we might have inserted a constant into this
418 // block, right after the PHI's which is before the old insert point!
419 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
425 bool V8ISel::runOnFunction(Function &Fn) {
426 // First pass over the function, lower any unknown intrinsic functions
427 // with the IntrinsicLowering class.
428 LowerUnknownIntrinsicFunctionCalls(Fn);
430 F = &MachineFunction::construct(&Fn, TM);
432 // Create all of the machine basic blocks for the function...
433 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
434 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
438 // Set up a frame object for the return address. This is used by the
439 // llvm.returnaddress & llvm.frameaddress intrinisics.
440 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
442 // Copy incoming arguments off of the stack and out of fixed registers.
443 LoadArgumentsToVirtualRegs(&Fn);
445 // Instruction select everything except PHI nodes
448 // Select the PHI nodes
454 // We always build a machine code representation for the function
458 void V8ISel::visitCastInst(CastInst &I) {
459 Value *Op = I.getOperand(0);
460 unsigned DestReg = getReg(I);
461 MachineBasicBlock::iterator MI = BB->end();
462 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
465 /// emitCastOperation - Common code shared between visitCastInst and constant
466 /// expression cast support.
468 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
469 MachineBasicBlock::iterator IP,
470 Value *Src, const Type *DestTy,
472 const Type *SrcTy = Src->getType();
473 unsigned SrcClass = getClassB(SrcTy);
474 unsigned DestClass = getClassB(DestTy);
475 unsigned SrcReg = getReg(Src, BB, IP);
477 const Type *oldTy = SrcTy;
478 const Type *newTy = DestTy;
479 unsigned oldTyClass = SrcClass;
480 unsigned newTyClass = DestClass;
482 if (oldTyClass < cLong && newTyClass < cLong) {
483 if (oldTyClass >= newTyClass) {
484 // Emit a reg->reg copy to do a equal-size or narrowing cast,
485 // and do sign/zero extension (necessary if we change signedness).
486 unsigned TmpReg1 = makeAnotherReg (newTy);
487 unsigned TmpReg2 = makeAnotherReg (newTy);
488 BuildMI (*BB, IP, V8::ORrr, 2, TmpReg1).addReg (V8::G0).addReg (SrcReg);
489 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
490 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
491 if (newTy->isSigned ()) { // sign-extend with SRA
492 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
493 } else { // zero-extend with SRL
494 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
497 unsigned TmpReg1 = makeAnotherReg (oldTy);
498 unsigned TmpReg2 = makeAnotherReg (newTy);
499 unsigned TmpReg3 = makeAnotherReg (newTy);
500 // Widening integer cast. Make sure it's fully sign/zero-extended
501 // wrt the input type, then make sure it's fully sign/zero-extended wrt
502 // the output type. Kind of stupid, but simple...
503 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (oldTy));
504 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg1).addZImm (shiftWidth).addReg(SrcReg);
505 if (oldTy->isSigned ()) { // sign-extend with SRA
506 BuildMI(*BB, IP, V8::SRAri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
507 } else { // zero-extend with SRL
508 BuildMI(*BB, IP, V8::SRLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
510 shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
511 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg3).addZImm (shiftWidth).addReg(TmpReg2);
512 if (newTy->isSigned ()) { // sign-extend with SRA
513 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
514 } else { // zero-extend with SRL
515 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
519 if (newTyClass == cFloat) {
520 assert (oldTyClass != cLong && "cast long to float not implemented yet");
521 switch (oldTyClass) {
523 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
526 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
529 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
530 // cast int to float. Store it to a stack slot and then load
531 // it using ldf into a floating point register. then do fitos.
532 unsigned TmpReg = makeAnotherReg (newTy);
533 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
534 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
536 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
537 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
541 } else if (newTyClass == cDouble) {
542 assert (oldTyClass != cLong && "cast long to double not implemented yet");
543 switch (oldTyClass) {
545 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
548 // go through memory, for now
549 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
550 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
551 BuildMI (*BB, IP, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
553 BuildMI (*BB, IP, V8::LDDFri, 2, DestReg).addFrameIndex (FI)
558 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
559 unsigned TmpReg = makeAnotherReg (newTy);
560 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
561 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
563 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
564 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
569 std::cerr << "Cast still unsupported: SrcTy = "
570 << *SrcTy << ", DestTy = " << *DestTy << "\n";
576 void V8ISel::visitLoadInst(LoadInst &I) {
577 unsigned DestReg = getReg (I);
578 unsigned PtrReg = getReg (I.getOperand (0));
579 switch (getClassB (I.getType ())) {
581 if (I.getType ()->isSigned ())
582 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
584 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
587 if (I.getType ()->isSigned ())
588 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
590 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
593 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
596 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
597 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
600 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
603 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
606 std::cerr << "Load instruction not handled: " << I;
612 void V8ISel::visitStoreInst(StoreInst &I) {
613 Value *SrcVal = I.getOperand (0);
614 unsigned SrcReg = getReg (SrcVal);
615 unsigned PtrReg = getReg (I.getOperand (1));
616 switch (getClassB (SrcVal->getType ())) {
618 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
621 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
624 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
627 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
628 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
631 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
634 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
637 std::cerr << "Store instruction not handled: " << I;
643 void V8ISel::visitCallInst(CallInst &I) {
644 MachineInstr *TheCall;
645 // Is it an intrinsic function call?
646 if (Function *F = I.getCalledFunction()) {
647 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
648 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
654 assert (I.getNumOperands () < 8
655 && "Can't handle pushing excess call args on the stack yet");
656 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
658 for (unsigned i = 1; i < 7; ++i)
659 if (i < I.getNumOperands ()) {
660 assert (getClassB (I.getOperand (i)->getType ()) < cLong
661 && "Can't handle long or fp function call arguments yet");
662 unsigned ArgReg = getReg (I.getOperand (i));
663 // Schlep it over into the incoming arg register
664 BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0)
668 // Emit call instruction
669 if (Function *F = I.getCalledFunction ()) {
670 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
671 } else { // Emit an indirect call...
672 unsigned Reg = getReg (I.getCalledValue ());
673 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
676 // Deal w/ return value: schlep it over into the destination register
677 if (I.getType () == Type::VoidTy)
679 unsigned DestReg = getReg (I);
680 switch (getClass (I.getType ())) {
684 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
687 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
690 std::cerr << "Return type of call instruction not handled: " << I;
695 void V8ISel::visitReturnInst(ReturnInst &I) {
696 if (I.getNumOperands () == 1) {
697 unsigned RetValReg = getReg (I.getOperand (0));
698 switch (getClass (I.getOperand (0)->getType ())) {
702 // Schlep it over into i0 (where it will become o0 after restore).
703 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
706 std::cerr << "Return instruction of this type not handled: " << I;
711 // Just emit a 'retl' instruction to return.
712 BuildMI(BB, V8::RETL, 0);
716 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
717 Function::iterator I = BB; ++I; // Get iterator to next block
718 return I != BB->getParent()->end() ? &*I : 0;
721 /// visitBranchInst - Handles conditional and unconditional branches.
723 void V8ISel::visitBranchInst(BranchInst &I) {
724 BasicBlock *takenSucc = I.getSuccessor (0);
725 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
726 BB->addSuccessor (takenSuccMBB);
727 if (I.isConditional()) { // conditional branch
728 BasicBlock *notTakenSucc = I.getSuccessor (1);
729 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
730 BB->addSuccessor (notTakenSuccMBB);
732 // CondReg=(<condition>);
733 // If (CondReg==0) goto notTakenSuccMBB;
734 unsigned CondReg = getReg (I.getCondition ());
735 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
736 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
738 // goto takenSuccMBB;
739 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
742 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
743 /// constant expression GEP support.
745 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
746 MachineBasicBlock::iterator IP,
747 Value *Src, User::op_iterator IdxBegin,
748 User::op_iterator IdxEnd, unsigned TargetReg) {
749 const TargetData &TD = TM.getTargetData ();
750 const Type *Ty = Src->getType ();
751 unsigned basePtrReg = getReg (Src, MBB, IP);
753 // GEPs have zero or more indices; we must perform a struct access
754 // or array access for each one.
755 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
758 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
759 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
760 // It's a struct access. idx is the index into the structure,
761 // which names the field. Use the TargetData structure to
762 // pick out what the layout of the structure is in memory.
763 // Use the (constant) structure index's value to find the
764 // right byte offset from the StructLayout class's list of
765 // structure member offsets.
766 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
767 unsigned memberOffset =
768 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
769 // Emit an ADD to add memberOffset to the basePtr.
770 BuildMI (*MBB, IP, V8::ADDri, 2,
771 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
772 // The next type is the member of the structure selected by the
774 Ty = StTy->getElementType (fieldIndex);
775 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
776 // It's an array or pointer access: [ArraySize x ElementType].
777 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
778 // must find the size of the pointed-to type (Not coincidentally, the next
779 // type is the type of the elements in the array).
780 Ty = SqTy->getElementType ();
781 unsigned elementSize = TD.getTypeSize (Ty);
782 unsigned idxReg = getReg (idx, MBB, IP);
783 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
784 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
785 copyConstantToRegister (MBB, IP,
786 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
787 // Emit a SMUL to multiply the register holding the index by
788 // elementSize, putting the result in OffsetReg.
789 BuildMI (*MBB, IP, V8::SMULrr, 2,
790 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
791 // Emit an ADD to add OffsetReg to the basePtr.
792 BuildMI (*MBB, IP, V8::ADDrr, 2,
793 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
795 basePtrReg = nextBasePtrReg;
797 // After we have processed all the indices, the result is left in
798 // basePtrReg. Move it to the register where we were expected to
800 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
803 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
804 unsigned outputReg = getReg (I);
805 emitGEPOperation (BB, BB->end (), I.getOperand (0),
806 I.op_begin ()+1, I.op_end (), outputReg);
810 void V8ISel::visitBinaryOperator (Instruction &I) {
811 unsigned DestReg = getReg (I);
812 unsigned Op0Reg = getReg (I.getOperand (0));
813 unsigned Op1Reg = getReg (I.getOperand (1));
815 unsigned Class = getClassB (I.getType());
816 unsigned OpCase = ~0;
819 switch (I.getOpcode ()) {
820 case Instruction::Add: OpCase = 0; break;
821 case Instruction::Sub: OpCase = 1; break;
822 case Instruction::Mul: OpCase = 2; break;
823 case Instruction::Div: OpCase = 3; break;
824 default: visitInstruction (I); return;
826 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
827 V8::FSUBS, V8::FSUBD,
828 V8::FMULS, V8::FMULD,
829 V8::FDIVS, V8::FDIVD };
830 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
831 .addReg (Op0Reg).addReg (Op1Reg);
835 unsigned ResultReg = DestReg;
837 ResultReg = makeAnotherReg (I.getType ());
839 // FIXME: support long, ulong, fp.
840 switch (I.getOpcode ()) {
841 case Instruction::Add: OpCase = 0; break;
842 case Instruction::Sub: OpCase = 1; break;
843 case Instruction::Mul: OpCase = 2; break;
844 case Instruction::And: OpCase = 3; break;
845 case Instruction::Or: OpCase = 4; break;
846 case Instruction::Xor: OpCase = 5; break;
847 case Instruction::Shl: OpCase = 6; break;
848 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
850 case Instruction::Div:
851 case Instruction::Rem: {
852 unsigned Dest = ResultReg;
853 if (I.getOpcode() == Instruction::Rem)
854 Dest = makeAnotherReg(I.getType());
856 // FIXME: this is probably only right for 32 bit operands.
857 if (I.getType ()->isSigned()) {
858 unsigned Tmp = makeAnotherReg (I.getType ());
859 // Sign extend into the Y register
860 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
861 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
862 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
864 // Zero extend into the Y register, ie, just set it to zero
865 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
866 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
869 if (I.getOpcode() == Instruction::Rem) {
870 unsigned Tmp = makeAnotherReg (I.getType ());
871 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
872 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
877 visitInstruction (I);
881 static const unsigned Opcodes[] = {
882 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
883 V8::SLLrr, V8::SRLrr, V8::SRArr
886 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
889 switch (getClass (I.getType ())) {
891 if (I.getType ()->isSigned ()) { // add byte
892 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
893 } else { // add ubyte
894 unsigned TmpReg = makeAnotherReg (I.getType ());
895 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
896 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
900 if (I.getType ()->isSigned ()) { // add short
901 unsigned TmpReg = makeAnotherReg (I.getType ());
902 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
903 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
904 } else { // add ushort
905 unsigned TmpReg = makeAnotherReg (I.getType ());
906 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
907 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
911 // Nothing todo here.
914 // Only support and, or, xor.
915 if (OpCase < 3 || OpCase > 5) {
916 visitInstruction (I);
919 // Do the other half of the value:
920 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
924 visitInstruction (I);
928 void V8ISel::visitSetCondInst(SetCondInst &I) {
929 unsigned Op0Reg = getReg (I.getOperand (0));
930 unsigned Op1Reg = getReg (I.getOperand (1));
931 unsigned DestReg = getReg (I);
932 const Type *Ty = I.getOperand (0)->getType ();
934 assert (getClass (Ty) < cLong && "can't setcc on longs or fp yet");
935 // Compare the two values.
936 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
939 switch (I.getOpcode()) {
940 default: assert(0 && "Unknown setcc instruction!");
941 case Instruction::SetEQ: BranchIdx = 0; break;
942 case Instruction::SetNE: BranchIdx = 1; break;
943 case Instruction::SetLT: BranchIdx = 2; break;
944 case Instruction::SetGT: BranchIdx = 3; break;
945 case Instruction::SetLE: BranchIdx = 4; break;
946 case Instruction::SetGE: BranchIdx = 5; break;
948 static unsigned OpcodeTab[12] = {
951 V8::BE, V8::BE, // seteq = be be
952 V8::BNE, V8::BNE, // setne = bne bne
953 V8::BCS, V8::BL, // setlt = bcs bl
954 V8::BGU, V8::BG, // setgt = bgu bg
955 V8::BLEU, V8::BLE, // setle = bleu ble
956 V8::BCC, V8::BGE // setge = bcc bge
958 unsigned Opcode = OpcodeTab[2*BranchIdx + (Ty->isSigned() ? 1 : 0)];
960 MachineBasicBlock *thisMBB = BB;
961 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
964 // subcc %reg0, %reg1, %g0
968 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
969 // if we could insert other, non-terminator instructions after the
970 // bCC. But MBB->getFirstTerminator() can't understand this.
971 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
972 F->getBasicBlockList ().push_back (copy1MBB);
973 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
974 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
975 F->getBasicBlockList ().push_back (copy0MBB);
976 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
977 // Update machine-CFG edges
978 BB->addSuccessor (copy1MBB);
979 BB->addSuccessor (copy0MBB);
982 // %FalseValue = or %G0, 0
985 unsigned FalseValue = makeAnotherReg (I.getType ());
986 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
987 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
988 F->getBasicBlockList ().push_back (sinkMBB);
989 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
990 // Update machine-CFG edges
991 BB->addSuccessor (sinkMBB);
993 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
994 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
995 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
996 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
999 // %TrueValue = or %G0, 1
1002 unsigned TrueValue = makeAnotherReg (I.getType ());
1003 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1004 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1005 // Update machine-CFG edges
1006 BB->addSuccessor (sinkMBB);
1009 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1012 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1013 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1016 void V8ISel::visitAllocaInst(AllocaInst &I) {
1017 // Find the data size of the alloca inst's getAllocatedType.
1018 const Type *Ty = I.getAllocatedType();
1019 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1021 unsigned ArraySizeReg = getReg (I.getArraySize ());
1022 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1023 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1024 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1025 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1027 // StackAdjReg = (ArraySize * TySize) rounded up to nearest doubleword boundary
1028 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1030 // Round up TmpReg1 to nearest doubleword boundary:
1031 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1032 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1034 // Subtract size from stack pointer, thereby allocating some space.
1035 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1037 // Put a pointer to the space into the result register, by copying
1038 // the stack pointer.
1039 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1041 // Inform the Frame Information that we have just allocated a variable-sized
1043 F->getFrameInfo()->CreateVariableSizedObject();
1046 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1047 /// function, lowering any calls to unknown intrinsic functions into the
1048 /// equivalent LLVM code.
1049 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1050 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1051 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1052 if (CallInst *CI = dyn_cast<CallInst>(I++))
1053 if (Function *F = CI->getCalledFunction())
1054 switch (F->getIntrinsicID()) {
1055 case Intrinsic::not_intrinsic: break;
1057 // All other intrinsic calls we must lower.
1058 Instruction *Before = CI->getPrev();
1059 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1060 if (Before) { // Move iterator to instruction after call
1069 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1070 unsigned TmpReg1, TmpReg2;
1072 default: assert(0 && "Intrinsic not supported!");