1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Instructions.h"
17 #include "llvm/IntrinsicLowering.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Support/GetElementPtrTypeIterator.h"
25 #include "llvm/Support/InstVisitor.h"
26 #include "llvm/Support/CFG.h"
30 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
32 MachineFunction *F; // The function we are compiling into
33 MachineBasicBlock *BB; // The current MBB we are compiling
35 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
37 // MBBMap - Mapping between LLVM BB -> Machine BB
38 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
40 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
42 /// runOnFunction - Top level implementation of instruction selection for
43 /// the entire function.
45 bool runOnFunction(Function &Fn);
47 virtual const char *getPassName() const {
48 return "SparcV8 Simple Instruction Selection";
51 /// visitBasicBlock - This method is called when we are visiting a new basic
52 /// block. This simply creates a new MachineBasicBlock to emit code into
53 /// and adds it to the current MachineFunction. Subsequent visit* for
54 /// instructions will be invoked for all instructions in the basic block.
56 void visitBasicBlock(BasicBlock &LLVM_BB) {
57 BB = MBBMap[&LLVM_BB];
60 void visitBinaryOperator(Instruction &I);
61 void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); }
62 void visitSetCondInst(Instruction &I);
63 void visitCallInst(CallInst &I);
64 void visitReturnInst(ReturnInst &I);
65 void visitCastInst(CastInst &I);
66 void visitLoadInst(LoadInst &I);
67 void visitStoreInst(StoreInst &I);
69 void visitInstruction(Instruction &I) {
70 std::cerr << "Unhandled instruction: " << I;
74 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
75 /// function, lowering any calls to unknown intrinsic functions into the
76 /// equivalent LLVM code.
77 void LowerUnknownIntrinsicFunctionCalls(Function &F);
78 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
80 void LoadArgumentsToVirtualRegs(Function *F);
82 /// copyConstantToRegister - Output the instructions required to put the
83 /// specified constant into the specified register.
85 void copyConstantToRegister(MachineBasicBlock *MBB,
86 MachineBasicBlock::iterator IP,
87 Constant *C, unsigned R);
89 /// makeAnotherReg - This method returns the next register number we haven't
92 /// Long values are handled somewhat specially. They are always allocated
93 /// as pairs of 32 bit integer values. The register number returned is the
94 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
95 /// of the long value.
97 unsigned makeAnotherReg(const Type *Ty) {
98 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
99 "Current target doesn't have SparcV8 reg info??");
100 const SparcV8RegisterInfo *MRI =
101 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
102 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
103 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
104 // Create the lower part
105 F->getSSARegMap()->createVirtualRegister(RC);
106 // Create the upper part.
107 return F->getSSARegMap()->createVirtualRegister(RC)-1;
110 // Add the mapping of regnumber => reg class to MachineFunction
111 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
112 return F->getSSARegMap()->createVirtualRegister(RC);
115 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
116 unsigned getReg(Value *V) {
117 // Just append to the end of the current bb.
118 MachineBasicBlock::iterator It = BB->end();
119 return getReg(V, BB, It);
121 unsigned getReg(Value *V, MachineBasicBlock *MBB,
122 MachineBasicBlock::iterator IPt) {
123 unsigned &Reg = RegMap[V];
125 Reg = makeAnotherReg(V->getType());
128 // If this operand is a constant, emit the code to copy the constant into
129 // the register here...
131 if (Constant *C = dyn_cast<Constant>(V)) {
132 copyConstantToRegister(MBB, IPt, C, Reg);
133 RegMap.erase(V); // Assign a new name to this constant if ref'd again
134 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
135 // Move the address of the global into the register
136 unsigned TmpReg = makeAnotherReg(V->getType());
137 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
138 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
139 .addGlobalAddress (GV);
140 RegMap.erase(V); // Assign a new name to this address if ref'd again
149 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
150 return new V8ISel(TM);
154 cByte, cShort, cInt, cLong, cFloat, cDouble
157 static TypeClass getClass (const Type *T) {
158 switch (T->getPrimitiveID ()) {
159 case Type::UByteTyID: case Type::SByteTyID: return cByte;
160 case Type::UShortTyID: case Type::ShortTyID: return cShort;
161 case Type::PointerTyID:
162 case Type::UIntTyID: case Type::IntTyID: return cInt;
163 case Type::ULongTyID: case Type::LongTyID: return cLong;
164 case Type::FloatTyID: return cFloat;
165 case Type::DoubleTyID: return cDouble;
167 assert (0 && "Type of unknown class passed to getClass?");
171 static TypeClass getClassB(const Type *T) {
172 if (T == Type::BoolTy) return cByte;
178 /// copyConstantToRegister - Output the instructions required to put the
179 /// specified constant into the specified register.
181 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
182 MachineBasicBlock::iterator IP,
183 Constant *C, unsigned R) {
184 if (C->getType()->isIntegral ()) {
186 if (C->getType() == Type::BoolTy) {
187 Val = (C == ConstantBool::True);
189 ConstantInt *CI = dyn_cast<ConstantInt> (C);
190 Val = CI->getRawValue ();
192 switch (getClassB (C->getType ())) {
194 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val);
197 unsigned TmpReg = makeAnotherReg (C->getType ());
198 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
199 .addImm (((uint16_t) Val) >> 10);
200 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
201 .addImm (((uint16_t) Val) & 0x03ff);
205 unsigned TmpReg = makeAnotherReg (C->getType ());
206 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10);
207 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
208 .addImm (((uint32_t) Val) & 0x03ff);
212 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
213 uint32_t topHalf = (uint32_t) (Val >> 32);
214 uint32_t bottomHalf = (uint32_t)Val;
215 #if 0 // FIXME: This does not appear to be correct; it assigns SSA reg R twice.
216 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
217 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
218 .addImm (topHalf & 0x03ff);
219 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
220 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
221 .addImm (bottomHalf & 0x03ff);
223 std::cerr << "Offending constant: " << *C << "\n";
224 assert (0 && "Can't copy this kind of constant into register yet");
229 std::cerr << "Offending constant: " << *C << "\n";
230 assert (0 && "Can't copy this kind of constant into register yet");
235 std::cerr << "Offending constant: " << *C << "\n";
236 assert (0 && "Can't copy this kind of constant into register yet");
239 void V8ISel::LoadArgumentsToVirtualRegs (Function *F) {
240 unsigned ArgOffset = 0;
241 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
242 V8::I3, V8::I4, V8::I5 };
243 assert (F->asize () < 7
244 && "Can't handle loading excess call args off the stack yet");
246 for (Function::aiterator I = F->abegin(), E = F->aend(); I != E; ++I) {
247 unsigned Reg = getReg(*I);
248 switch (getClassB(I->getType())) {
252 BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
253 .addReg (IncomingArgRegs[ArgOffset]);
256 assert (0 && "Only <=32-bit, integral arguments currently handled");
263 bool V8ISel::runOnFunction(Function &Fn) {
264 // First pass over the function, lower any unknown intrinsic functions
265 // with the IntrinsicLowering class.
266 LowerUnknownIntrinsicFunctionCalls(Fn);
268 F = &MachineFunction::construct(&Fn, TM);
270 // Create all of the machine basic blocks for the function...
271 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
272 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
276 // Set up a frame object for the return address. This is used by the
277 // llvm.returnaddress & llvm.frameaddress intrinisics.
278 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
280 // Copy incoming arguments off of the stack and out of fixed registers.
281 LoadArgumentsToVirtualRegs(&Fn);
283 // Instruction select everything except PHI nodes
286 // Select the PHI nodes
292 // We always build a machine code representation for the function
296 void V8ISel::visitCastInst(CastInst &I) {
297 unsigned SrcReg = getReg (I.getOperand (0));
298 unsigned DestReg = getReg (I);
299 const Type *oldTy = I.getOperand (0)->getType ();
300 const Type *newTy = I.getType ();
301 unsigned oldTyClass = getClassB (oldTy);
302 unsigned newTyClass = getClassB (newTy);
304 if (oldTyClass < cLong && newTyClass < cLong && oldTyClass >= newTyClass) {
305 // Emit a reg->reg copy to do a equal-size or non-narrowing cast,
306 // and do sign/zero extension (necessary if we change signedness).
307 unsigned TempReg1 = makeAnotherReg (newTy);
308 unsigned TempReg2 = makeAnotherReg (newTy);
309 BuildMI (BB, V8::ORrr, 2, TempReg1).addReg (V8::G0).addReg (SrcReg);
310 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
311 BuildMI (BB, V8::SLLri, 2, TempReg2).addZImm (shiftWidth).addReg (TempReg1);
312 if (newTy->isSigned ()) { // sign-extend with SRA
313 BuildMI(BB, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg (TempReg2);
314 } else { // zero-extend with SRL
315 BuildMI(BB, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg (TempReg2);
318 std::cerr << "Casts w/ long, fp, double, or widening still unsupported: "
324 void V8ISel::visitLoadInst(LoadInst &I) {
325 unsigned DestReg = getReg (I);
326 unsigned PtrReg = getReg (I.getOperand (0));
327 switch (getClass (I.getType ())) {
329 if (I.getType ()->isSigned ())
330 BuildMI (BB, V8::LDSBmr, 1, DestReg).addReg (PtrReg).addSImm(0);
332 BuildMI (BB, V8::LDUBmr, 1, DestReg).addReg (PtrReg).addSImm(0);
335 if (I.getType ()->isSigned ())
336 BuildMI (BB, V8::LDSHmr, 1, DestReg).addReg (PtrReg).addSImm(0);
338 BuildMI (BB, V8::LDUHmr, 1, DestReg).addReg (PtrReg).addSImm(0);
341 BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
344 BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0);
347 std::cerr << "Load instruction not handled: " << I;
353 void V8ISel::visitStoreInst(StoreInst &I) {
354 unsigned SrcReg = getReg (I.getOperand (0));
355 unsigned PtrReg = getReg (I.getOperand (1));
356 std::cerr << "Store instruction not handled: " << I;
360 void V8ISel::visitCallInst(CallInst &I) {
361 assert (I.getNumOperands () < 8
362 && "Can't handle pushing excess call args on the stack yet");
363 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
365 for (unsigned i = 1; i < 7; ++i)
366 if (i < I.getNumOperands ()) {
367 unsigned ArgReg = getReg (I.getOperand (i));
368 // Schlep it over into the incoming arg register
369 BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0)
373 unsigned DestReg = getReg (I);
374 BuildMI (BB, V8::CALL, 1).addPCDisp (I.getOperand (0));
375 if (I.getType ()->getPrimitiveID () == Type::VoidTyID)
377 // Deal w/ return value
378 switch (getClass (I.getType ())) {
382 // Schlep it over into the destination register
383 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
386 visitInstruction (I);
391 void V8ISel::visitReturnInst(ReturnInst &I) {
392 if (I.getNumOperands () == 1) {
393 unsigned RetValReg = getReg (I.getOperand (0));
394 switch (getClass (I.getOperand (0)->getType ())) {
398 // Schlep it over into i0 (where it will become o0 after restore).
399 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
402 visitInstruction (I);
407 // Just emit a 'retl' instruction to return.
408 BuildMI(BB, V8::RETL, 0);
412 void V8ISel::visitBinaryOperator (Instruction &I) {
413 unsigned DestReg = getReg (I);
414 unsigned Op0Reg = getReg (I.getOperand (0));
415 unsigned Op1Reg = getReg (I.getOperand (1));
417 unsigned ResultReg = DestReg;
418 if (getClassB(I.getType()) != cInt)
419 ResultReg = makeAnotherReg (I.getType ());
420 unsigned OpCase = ~0;
422 // FIXME: support long, ulong, fp.
423 switch (I.getOpcode ()) {
424 case Instruction::Add: OpCase = 0; break;
425 case Instruction::Sub: OpCase = 1; break;
426 case Instruction::Mul: OpCase = 2; break;
427 case Instruction::And: OpCase = 3; break;
428 case Instruction::Or: OpCase = 4; break;
429 case Instruction::Xor: OpCase = 5; break;
430 case Instruction::Shl: OpCase = 6; break;
431 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
433 case Instruction::Div:
434 case Instruction::Rem: {
435 unsigned Dest = ResultReg;
436 if (I.getOpcode() == Instruction::Rem)
437 Dest = makeAnotherReg(I.getType());
439 // FIXME: this is probably only right for 32 bit operands.
440 if (I.getType ()->isSigned()) {
441 unsigned Tmp = makeAnotherReg (I.getType ());
442 // Sign extend into the Y register
443 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
444 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
445 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
447 // Zero extend into the Y register, ie, just set it to zero
448 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
449 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
452 if (I.getOpcode() == Instruction::Rem) {
453 unsigned Tmp = makeAnotherReg (I.getType ());
454 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
455 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
460 visitInstruction (I);
465 static const unsigned Opcodes[] = {
466 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
467 V8::SLLrr, V8::SRLrr, V8::SRArr
469 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
472 switch (getClass (I.getType ())) {
474 if (I.getType ()->isSigned ()) { // add byte
475 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
476 } else { // add ubyte
477 unsigned TmpReg = makeAnotherReg (I.getType ());
478 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
479 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
483 if (I.getType ()->isSigned ()) { // add short
484 unsigned TmpReg = makeAnotherReg (I.getType ());
485 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
486 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
487 } else { // add ushort
488 unsigned TmpReg = makeAnotherReg (I.getType ());
489 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
490 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
494 // Nothing todo here.
497 visitInstruction (I);
502 void V8ISel::visitSetCondInst(Instruction &I) {
503 unsigned Op0Reg = getReg (I.getOperand (0));
504 unsigned Op1Reg = getReg (I.getOperand (1));
505 unsigned DestReg = getReg (I);
507 // Compare the two values.
508 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
510 // Put 0 into a register.
511 //unsigned ZeroReg = makeAnotheRReg(Type::IntTy);
512 //BuildMI(BB, V8::ORri, 2, ZeroReg).addReg(V8::G0).addReg(V8::G0);
515 switch (I.getOpcode()) {
516 default: assert(0 && "Unknown setcc instruction!");
517 case Instruction::SetEQ:
518 case Instruction::SetNE:
519 case Instruction::SetLT:
520 case Instruction::SetGT:
521 case Instruction::SetLE:
522 case Instruction::SetGE:
526 // FIXME: We need either conditional moves like the V9 has (e.g. movge), or we
527 // need to be able to turn a single LLVM basic block into multiple machine
528 // code basic blocks. For now, it probably makes sense to emit Sparc V9
529 // instructions until the code generator is upgraded. Note that this should
530 // only happen when the setcc cannot be folded into the branch, but this needs
531 // to be handled correctly!
538 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
539 /// function, lowering any calls to unknown intrinsic functions into the
540 /// equivalent LLVM code.
541 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
542 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
543 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
544 if (CallInst *CI = dyn_cast<CallInst>(I++))
545 if (Function *F = CI->getCalledFunction())
546 switch (F->getIntrinsicID()) {
547 case Intrinsic::not_intrinsic: break;
549 // All other intrinsic calls we must lower.
550 Instruction *Before = CI->getPrev();
551 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
552 if (Before) { // Move iterator to instruction after call
561 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
562 unsigned TmpReg1, TmpReg2;
564 default: assert(0 && "Intrinsic not supported!");