1 //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8TargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
29 //===----------------------------------------------------------------------===//
30 // TargetLowering Implementation
31 //===----------------------------------------------------------------------===//
35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36 CMPICC, // Compare two GPR operands, set icc.
37 CMPFCC, // Compare two FP operands, set fcc.
38 BRICC, // Branch to dest on icc condition
39 BRFCC, // Branch to dest on fcc condition
41 Hi, Lo, // Hi/Lo operations, typically on a global address.
43 FTOI, // FP to Int within a FP register.
44 ITOF, // Int to FP within a FP register.
46 SELECT_ICC, // Select between two values using the current ICC flags.
47 SELECT_FCC, // Select between two values using the current FCC flags.
49 RET_FLAG, // Return with a flag operand.
54 class SparcV8TargetLowering : public TargetLowering {
55 int VarArgsFrameOffset; // Frame offset to start of varargs area.
57 SparcV8TargetLowering(TargetMachine &TM);
58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59 virtual std::vector<SDOperand>
60 LowerArguments(Function &F, SelectionDAG &DAG);
61 virtual std::pair<SDOperand, SDOperand>
62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
64 bool isTailCall, SDOperand Callee, ArgListTy &Args,
67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
70 Value *VAListV, SelectionDAG &DAG);
71 virtual std::pair<SDOperand,SDOperand>
72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
73 const Type *ArgTy, SelectionDAG &DAG);
74 virtual std::pair<SDOperand, SDOperand>
75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
78 MachineBasicBlock *MBB);
82 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
83 : TargetLowering(TM) {
85 // Set up the register classes.
86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
90 // Custom legalize GlobalAddress nodes into LO/HI parts.
91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
94 // Sparc doesn't have sext_inreg, replace them with shl/sra
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
99 // Sparc has no REM operation.
100 setOperationAction(ISD::UREM, MVT::i32, Expand);
101 setOperationAction(ISD::SREM, MVT::i32, Expand);
103 // Custom expand fp<->sint
104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
111 // Turn FP extload into load/fextend
112 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
114 // Sparc has no select or setcc: expand to SELECT_CC.
115 setOperationAction(ISD::SELECT, MVT::i32, Expand);
116 setOperationAction(ISD::SELECT, MVT::f32, Expand);
117 setOperationAction(ISD::SELECT, MVT::f64, Expand);
118 setOperationAction(ISD::SETCC, MVT::i32, Expand);
119 setOperationAction(ISD::SETCC, MVT::f32, Expand);
120 setOperationAction(ISD::SETCC, MVT::f64, Expand);
122 // Sparc doesn't have BRCOND either, it has BR_CC.
123 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
124 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
125 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
126 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
127 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
128 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
130 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
131 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
132 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
134 // V8 has no intrinsics for these particular operations.
135 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
136 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
137 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
139 setOperationAction(ISD::FSIN , MVT::f64, Expand);
140 setOperationAction(ISD::FCOS , MVT::f64, Expand);
141 setOperationAction(ISD::FSIN , MVT::f32, Expand);
142 setOperationAction(ISD::FCOS , MVT::f32, Expand);
143 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
144 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
145 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
147 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
148 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
149 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
150 computeRegisterProperties();
153 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
154 /// either one or two GPRs, including FP values. TODO: we should pass FP values
155 /// in FP registers for fastcc functions.
156 std::vector<SDOperand>
157 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
158 MachineFunction &MF = DAG.getMachineFunction();
159 SSARegMap *RegMap = MF.getSSARegMap();
160 std::vector<SDOperand> ArgValues;
162 static const unsigned ArgRegs[] = {
163 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
166 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
167 unsigned ArgOffset = 68;
169 SDOperand Root = DAG.getRoot();
170 std::vector<SDOperand> OutChains;
172 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
173 MVT::ValueType ObjectVT = getValueType(I->getType());
176 default: assert(0 && "Unhandled argument type!");
181 if (I->use_empty()) { // Argument is dead.
182 if (CurArgReg < ArgRegEnd) ++CurArgReg;
183 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
184 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
185 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
186 MF.addLiveIn(*CurArgReg++, VReg);
187 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
188 if (ObjectVT != MVT::i32) {
189 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
191 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
192 DAG.getValueType(ObjectVT));
193 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
195 ArgValues.push_back(Arg);
197 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
198 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
200 if (ObjectVT == MVT::i32) {
201 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
204 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
206 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
207 DAG.getSrcValue(0), ObjectVT);
209 ArgValues.push_back(Load);
215 if (I->use_empty()) { // Argument is dead.
216 if (CurArgReg < ArgRegEnd) ++CurArgReg;
217 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
218 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
219 // FP value is passed in an integer register.
220 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
221 MF.addLiveIn(*CurArgReg++, VReg);
222 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
224 // We use the stack space that is already reserved for this reg.
225 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
226 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
228 SDOperand SV = DAG.getSrcValue(0);
229 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
231 ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV));
238 if (I->use_empty()) { // Argument is dead.
239 if (CurArgReg < ArgRegEnd) ++CurArgReg;
240 if (CurArgReg < ArgRegEnd) ++CurArgReg;
241 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
242 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
243 ((CurArgReg-ArgRegs) & 1) == 0) {
244 // If this is a double argument and the whole thing lives on the stack,
245 // and the argument is aligned, load the double straight from the stack.
246 // We can't do a load in cases like void foo([6ints], int,double),
247 // because the double wouldn't be aligned!
248 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
249 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
250 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
251 DAG.getSrcValue(0)));
254 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
255 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
256 MF.addLiveIn(*CurArgReg++, VRegHi);
257 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
259 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
260 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
261 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
265 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
266 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
267 MF.addLiveIn(*CurArgReg++, VRegLo);
268 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
270 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
271 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
272 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
275 // Compose the two halves together into an i64 unit.
276 SDOperand WholeValue =
277 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
279 if (ObjectVT == MVT::i64) {
280 // If we are emitting an i64, this is what we want.
281 ArgValues.push_back(WholeValue);
283 assert(ObjectVT == MVT::f64);
284 // Otherwise, emit a store to the stack and reload into FPR.
285 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
286 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
287 SDOperand SV = DAG.getSrcValue(0);
288 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
289 WholeValue, FIPtr, SV);
290 ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV));
298 // Store remaining ArgRegs to the stack if this is a varargs function.
299 if (F.getFunctionType()->isVarArg()) {
300 // Remember the vararg offset for the va_start implementation.
301 VarArgsFrameOffset = ArgOffset;
303 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
304 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
305 MF.addLiveIn(*CurArgReg, VReg);
306 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
308 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
309 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
311 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
312 Arg, FIPtr, DAG.getSrcValue(0)));
317 if (!OutChains.empty())
318 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
320 // Finally, inform the code generator which regs we return values in.
321 switch (getValueType(F.getReturnType())) {
322 default: assert(0 && "Unknown type!");
323 case MVT::isVoid: break;
328 MF.addLiveOut(V8::I0);
331 MF.addLiveOut(V8::I0);
332 MF.addLiveOut(V8::I1);
335 MF.addLiveOut(V8::F0);
338 MF.addLiveOut(V8::D0);
345 std::pair<SDOperand, SDOperand>
346 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
347 bool isVarArg, unsigned CC,
348 bool isTailCall, SDOperand Callee,
349 ArgListTy &Args, SelectionDAG &DAG) {
350 MachineFunction &MF = DAG.getMachineFunction();
351 // Count the size of the outgoing arguments.
352 unsigned ArgsSize = 0;
353 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
354 switch (getValueType(Args[i].second)) {
355 default: assert(0 && "Unknown value type!");
370 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
374 // Keep stack frames 8-byte aligned.
375 ArgsSize = (ArgsSize+7) & ~7;
377 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
378 DAG.getConstant(ArgsSize, getPointerTy()));
380 SDOperand StackPtr, NullSV;
381 std::vector<SDOperand> Stores;
382 std::vector<SDOperand> RegValuesToPass;
383 unsigned ArgOffset = 68;
384 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
385 SDOperand Val = Args[i].first;
386 MVT::ValueType ObjectVT = Val.getValueType();
387 SDOperand ValToStore;
390 default: assert(0 && "Unhandled argument type!");
394 // Promote the integer to 32-bits. If the input type is signed, use a
395 // sign extend, otherwise use a zero extend.
396 if (Args[i].second->isSigned())
397 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
399 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
404 if (RegValuesToPass.size() >= 6) {
407 RegValuesToPass.push_back(Val);
412 if (RegValuesToPass.size() >= 6) {
415 // Convert this to a FP value in an int reg.
416 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
417 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
418 SDOperand SV = DAG.getSrcValue(0);
419 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
421 Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV);
422 RegValuesToPass.push_back(Val);
427 // If we can store this directly into the outgoing slot, do so. We can
428 // do this when all ArgRegs are used and if the outgoing slot is aligned.
429 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
434 // Otherwise, convert this to a FP value in int regs.
435 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
436 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
437 SDOperand SV = DAG.getSrcValue(0);
438 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
440 Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV);
445 if (RegValuesToPass.size() >= 6) {
446 ValToStore = Val; // Whole thing is passed in memory.
450 // Split the value into top and bottom part. Top part goes in a reg.
451 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
452 DAG.getConstant(1, MVT::i32));
453 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
454 DAG.getConstant(0, MVT::i32));
455 RegValuesToPass.push_back(Hi);
457 if (RegValuesToPass.size() >= 6) {
460 RegValuesToPass.push_back(Lo);
465 if (ValToStore.Val) {
467 StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
468 NullSV = DAG.getSrcValue(NULL);
470 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
471 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
472 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
473 ValToStore, PtrOff, NullSV));
475 ArgOffset += ObjSize;
478 // Emit all stores, make sure the occur before any copies into physregs.
480 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
482 static const unsigned ArgRegs[] = {
483 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
486 // Build a sequence of copy-to-reg nodes chained together with token chain
487 // and flag operands which copy the outgoing args into O[0-5].
489 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
490 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
491 InFlag = Chain.getValue(1);
494 std::vector<MVT::ValueType> RetVals;
495 RetVals.push_back(MVT::Other);
496 RetVals.push_back(MVT::Flag);
498 // If the callee is a GlobalAddress node (quite common, every direct call is)
499 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
500 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
501 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
503 std::vector<MVT::ValueType> NodeTys;
504 NodeTys.push_back(MVT::Other); // Returns a chain
505 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
507 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
509 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
510 InFlag = Chain.getValue(1);
512 MVT::ValueType RetTyVT = getValueType(RetTy);
514 if (RetTyVT != MVT::isVoid) {
516 default: assert(0 && "Unknown value type to return!");
520 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
521 Chain = RetVal.getValue(1);
523 // Add a note to keep track of whether it is sign or zero extended.
524 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
525 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
526 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
529 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
530 Chain = RetVal.getValue(1);
533 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
534 Chain = RetVal.getValue(1);
537 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
538 Chain = RetVal.getValue(1);
541 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
542 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
544 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
545 Chain = Hi.getValue(1);
550 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
551 DAG.getConstant(ArgsSize, getPointerTy()));
553 MVT::ValueType ActualRetTyVT = RetTyVT;
554 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
555 ActualRetTyVT = MVT::i32; // Promote result to i32.
557 return std::make_pair(RetVal, Chain);
560 SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
563 switch (Op.getValueType()) {
564 default: assert(0 && "Unknown type to return!");
566 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
569 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
572 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
575 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
576 DAG.getConstant(1, MVT::i32));
577 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
578 DAG.getConstant(0, MVT::i32));
579 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
580 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
583 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
586 SDOperand SparcV8TargetLowering::
587 LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
590 assert(0 && "Unimp");
594 std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
595 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
596 const Type *ArgTy, SelectionDAG &DAG) {
597 assert(0 && "Unimp");
601 std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
602 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
604 assert(0 && "Unimp");
608 SDOperand SparcV8TargetLowering::
609 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
610 switch (Op.getOpcode()) {
611 default: assert(0 && "Should not custom lower this!");
612 case ISD::GlobalAddress: {
613 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
614 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
615 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
616 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
617 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
619 case ISD::ConstantPool: {
620 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
621 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
622 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
623 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
624 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
626 case ISD::FP_TO_SINT: {
627 // Convert the fp value to integer in an FP register.
628 Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(),
630 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
632 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
633 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
634 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
635 Op, FI, DAG.getSrcValue(0));
636 return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
638 case ISD::SINT_TO_FP: {
639 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
641 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
642 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
643 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
644 Op.getOperand(0), FI, DAG.getSrcValue(0));
646 Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0));
648 // Convert the int value to FP in an FP register.
649 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
652 SDOperand Chain = Op.getOperand(0);
653 SDOperand CC = Op.getOperand(1);
654 SDOperand LHS = Op.getOperand(2);
655 SDOperand RHS = Op.getOperand(3);
656 SDOperand Dest = Op.getOperand(4);
658 // Get the condition flag.
659 if (LHS.getValueType() == MVT::i32) {
660 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
661 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
663 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
664 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
667 case ISD::SELECT_CC: {
668 SDOperand LHS = Op.getOperand(0);
669 SDOperand RHS = Op.getOperand(1);
670 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
671 SDOperand TrueVal = Op.getOperand(2);
672 SDOperand FalseVal = Op.getOperand(3);
675 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
676 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS);
678 Opc = LHS.getValueType() == MVT::i32 ?
679 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
680 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
681 DAG.getConstant(CC, MVT::i32), CompareFlag);
687 SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
688 MachineBasicBlock *BB) {
690 // Figure out the conditional branch opcode to use for this select_cc.
691 switch (MI->getOpcode()) {
692 default: assert(0 && "Unknown SELECT_CC!");
693 case V8::SELECT_CC_Int_ICC:
694 case V8::SELECT_CC_FP_ICC:
695 case V8::SELECT_CC_DFP_ICC:
697 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
698 default: assert(0 && "Unknown integer condition code!");
699 case ISD::SETEQ: BROpcode = V8::BE; break;
700 case ISD::SETNE: BROpcode = V8::BNE; break;
701 case ISD::SETLT: BROpcode = V8::BL; break;
702 case ISD::SETGT: BROpcode = V8::BG; break;
703 case ISD::SETLE: BROpcode = V8::BLE; break;
704 case ISD::SETGE: BROpcode = V8::BGE; break;
705 case ISD::SETULT: BROpcode = V8::BCS; break;
706 case ISD::SETULE: BROpcode = V8::BLEU; break;
707 case ISD::SETUGT: BROpcode = V8::BGU; break;
708 case ISD::SETUGE: BROpcode = V8::BCC; break;
711 case V8::SELECT_CC_Int_FCC:
712 case V8::SELECT_CC_FP_FCC:
713 case V8::SELECT_CC_DFP_FCC:
715 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
716 default: assert(0 && "Unknown fp condition code!");
717 case ISD::SETEQ: BROpcode = V8::FBE; break;
718 case ISD::SETNE: BROpcode = V8::FBNE; break;
719 case ISD::SETLT: BROpcode = V8::FBL; break;
720 case ISD::SETGT: BROpcode = V8::FBG; break;
721 case ISD::SETLE: BROpcode = V8::FBLE; break;
722 case ISD::SETGE: BROpcode = V8::FBGE; break;
723 case ISD::SETULT: BROpcode = V8::FBUL; break;
724 case ISD::SETULE: BROpcode = V8::FBULE; break;
725 case ISD::SETUGT: BROpcode = V8::FBUG; break;
726 case ISD::SETUGE: BROpcode = V8::FBUGE; break;
727 case ISD::SETUO: BROpcode = V8::FBU; break;
728 case ISD::SETO: BROpcode = V8::FBO; break;
729 case ISD::SETONE: BROpcode = V8::FBLG; break;
730 case ISD::SETUEQ: BROpcode = V8::FBUE; break;
735 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
736 // control-flow pattern. The incoming instruction knows the destination vreg
737 // to set, the condition code register to branch on, the true/false values to
738 // select between, and a branch opcode to use.
739 const BasicBlock *LLVM_BB = BB->getBasicBlock();
740 ilist<MachineBasicBlock>::iterator It = BB;
747 // fallthrough --> copy0MBB
748 MachineBasicBlock *thisMBB = BB;
749 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
750 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
751 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
752 MachineFunction *F = BB->getParent();
753 F->getBasicBlockList().insert(It, copy0MBB);
754 F->getBasicBlockList().insert(It, sinkMBB);
755 // Update machine-CFG edges
756 BB->addSuccessor(copy0MBB);
757 BB->addSuccessor(sinkMBB);
761 // # fallthrough to sinkMBB
764 // Update machine-CFG edges
765 BB->addSuccessor(sinkMBB);
768 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
771 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
772 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
773 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
775 delete MI; // The pseudo instruction is gone now.
779 //===----------------------------------------------------------------------===//
780 // Instruction Selector Implementation
781 //===----------------------------------------------------------------------===//
783 //===--------------------------------------------------------------------===//
784 /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
785 /// instructions for SelectionDAG operations.
788 class SparcV8DAGToDAGISel : public SelectionDAGISel {
789 SparcV8TargetLowering V8Lowering;
791 SparcV8DAGToDAGISel(TargetMachine &TM)
792 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
794 SDOperand Select(SDOperand Op);
796 // Complex Pattern Selectors.
797 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
798 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
800 /// InstructionSelectBasicBlock - This callback is invoked by
801 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
802 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
804 virtual const char *getPassName() const {
805 return "PowerPC DAG->DAG Pattern Instruction Selection";
808 // Include the pieces autogenerated from the target description.
809 #include "SparcV8GenDAGISel.inc"
811 } // end anonymous namespace
813 /// InstructionSelectBasicBlock - This callback is invoked by
814 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
815 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
818 // Select target instructions for the DAG.
819 DAG.setRoot(Select(DAG.getRoot()));
821 DAG.RemoveDeadNodes();
823 // Emit machine code to BB.
824 ScheduleAndEmitDAG(DAG);
827 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
829 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
830 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
831 Offset = CurDAG->getTargetConstant(0, MVT::i32);
835 if (Addr.getOpcode() == ISD::ADD) {
836 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
837 if (Predicate_simm13(CN)) {
838 if (FrameIndexSDNode *FIN =
839 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
840 // Constant offset from frame ref.
841 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
843 Base = Select(Addr.getOperand(0));
845 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
849 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
850 Base = Select(Addr.getOperand(1));
851 Offset = Addr.getOperand(0).getOperand(0);
854 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
855 Base = Select(Addr.getOperand(0));
856 Offset = Addr.getOperand(1).getOperand(0);
861 Offset = CurDAG->getTargetConstant(0, MVT::i32);
865 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
867 if (Addr.getOpcode() == ISD::FrameIndex) return false;
868 if (Addr.getOpcode() == ISD::ADD) {
869 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
870 Predicate_simm13(Addr.getOperand(1).Val))
871 return false; // Let the reg+imm pattern catch this!
872 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
873 Addr.getOperand(1).getOpcode() == V8ISD::Lo)
874 return false; // Let the reg+imm pattern catch this!
875 R1 = Select(Addr.getOperand(0));
876 R2 = Select(Addr.getOperand(1));
881 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
885 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
887 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
888 N->getOpcode() < V8ISD::FIRST_NUMBER)
889 return Op; // Already selected.
890 // If this has already been converted, use it.
891 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
892 if (CGMI != CodeGenMap.end()) return CGMI->second;
894 switch (N->getOpcode()) {
896 case ISD::FrameIndex: {
897 int FI = cast<FrameIndexSDNode>(N)->getIndex();
899 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
900 CurDAG->getTargetFrameIndex(FI, MVT::i32),
901 CurDAG->getTargetConstant(0, MVT::i32));
902 return CodeGenMap[Op] =
903 CurDAG->getTargetNode(V8::ADDri, MVT::i32,
904 CurDAG->getTargetFrameIndex(FI, MVT::i32),
905 CurDAG->getTargetConstant(0, MVT::i32));
907 case V8ISD::CMPICC: {
908 // FIXME: Handle compare with immediate.
909 SDOperand LHS = Select(N->getOperand(0));
910 SDOperand RHS = Select(N->getOperand(1));
911 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
913 return CodeGenMap[Op] = Result.getValue(1);
915 case ISD::ADD_PARTS: {
916 SDOperand LHSL = Select(N->getOperand(0));
917 SDOperand LHSH = Select(N->getOperand(1));
918 SDOperand RHSL = Select(N->getOperand(2));
919 SDOperand RHSH = Select(N->getOperand(3));
920 // FIXME, handle immediate RHS.
921 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
923 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
925 CodeGenMap[SDOperand(N, 0)] = Low;
926 CodeGenMap[SDOperand(N, 1)] = Hi;
927 return Op.ResNo ? Hi : Low;
929 case ISD::SUB_PARTS: {
930 SDOperand LHSL = Select(N->getOperand(0));
931 SDOperand LHSH = Select(N->getOperand(1));
932 SDOperand RHSL = Select(N->getOperand(2));
933 SDOperand RHSH = Select(N->getOperand(3));
934 // FIXME, handle immediate RHS.
935 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
937 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
939 CodeGenMap[SDOperand(N, 0)] = Low;
940 CodeGenMap[SDOperand(N, 1)] = Hi;
941 return Op.ResNo ? Hi : Low;
945 // FIXME: should use a custom expander to expose the SRA to the dag.
946 SDOperand DivLHS = Select(N->getOperand(0));
947 SDOperand DivRHS = Select(N->getOperand(1));
949 // Set the Y register to the high-part.
951 if (N->getOpcode() == ISD::SDIV) {
952 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
953 CurDAG->getTargetConstant(31, MVT::i32));
955 TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
957 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
958 CurDAG->getRegister(V8::G0, MVT::i32));
960 // FIXME: Handle div by immediate.
961 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
962 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
966 // FIXME: Handle mul by immediate.
967 SDOperand MulLHS = Select(N->getOperand(0));
968 SDOperand MulRHS = Select(N->getOperand(1));
969 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
970 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
972 // The high part is in the Y register.
973 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
976 // FIXME: This is a workaround for a bug in tblgen.
977 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
978 // Emits: (CALL:void (tglobaladdr:i32):$dst)
979 // Pattern complexity = 2 cost = 1
980 SDOperand N1 = N->getOperand(1);
981 if (N1.getOpcode() != ISD::TargetGlobalAddress &&
982 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
983 SDOperand InFlag = SDOperand(0, 0);
984 SDOperand Chain = N->getOperand(0);
986 Chain = Select(Chain);
988 if (N->getNumOperands() == 3) {
989 InFlag = Select(N->getOperand(2));
990 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
993 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
996 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
997 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
998 return Result.getValue(Op.ResNo);
1004 return SelectCode(Op);
1008 /// createPPCISelDag - This pass converts a legalized DAG into a
1009 /// PowerPC-specific DAG, ready for instruction scheduling.
1011 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1012 return new SparcV8DAGToDAGISel(TM);