1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Instructions.h"
17 #include "llvm/IntrinsicLowering.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Support/GetElementPtrTypeIterator.h"
25 #include "llvm/Support/InstVisitor.h"
26 #include "llvm/Support/CFG.h"
30 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
32 MachineFunction *F; // The function we are compiling into
33 MachineBasicBlock *BB; // The current MBB we are compiling
35 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
37 // MBBMap - Mapping between LLVM BB -> Machine BB
38 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
40 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
42 /// runOnFunction - Top level implementation of instruction selection for
43 /// the entire function.
45 bool runOnFunction(Function &Fn);
47 virtual const char *getPassName() const {
48 return "SparcV8 Simple Instruction Selection";
51 /// visitBasicBlock - This method is called when we are visiting a new basic
52 /// block. This simply creates a new MachineBasicBlock to emit code into
53 /// and adds it to the current MachineFunction. Subsequent visit* for
54 /// instructions will be invoked for all instructions in the basic block.
56 void visitBasicBlock(BasicBlock &LLVM_BB) {
57 BB = MBBMap[&LLVM_BB];
60 void visitBinaryOperator(BinaryOperator &I);
61 void visitReturnInst(ReturnInst &RI);
63 void visitInstruction(Instruction &I) {
64 std::cerr << "Unhandled instruction: " << I;
68 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
69 /// function, lowering any calls to unknown intrinsic functions into the
70 /// equivalent LLVM code.
71 void LowerUnknownIntrinsicFunctionCalls(Function &F);
72 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
74 /// copyConstantToRegister - Output the instructions required to put the
75 /// specified constant into the specified register.
77 void copyConstantToRegister(MachineBasicBlock *MBB,
78 MachineBasicBlock::iterator IP,
79 Constant *C, unsigned R);
81 /// makeAnotherReg - This method returns the next register number we haven't
84 /// Long values are handled somewhat specially. They are always allocated
85 /// as pairs of 32 bit integer values. The register number returned is the
86 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
87 /// of the long value.
89 unsigned makeAnotherReg(const Type *Ty) {
90 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
91 "Current target doesn't have SparcV8 reg info??");
92 const SparcV8RegisterInfo *MRI =
93 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
94 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
95 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
96 // Create the lower part
97 F->getSSARegMap()->createVirtualRegister(RC);
98 // Create the upper part.
99 return F->getSSARegMap()->createVirtualRegister(RC)-1;
102 // Add the mapping of regnumber => reg class to MachineFunction
103 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
104 return F->getSSARegMap()->createVirtualRegister(RC);
107 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
108 unsigned getReg(Value *V) {
109 // Just append to the end of the current bb.
110 MachineBasicBlock::iterator It = BB->end();
111 return getReg(V, BB, It);
113 unsigned getReg(Value *V, MachineBasicBlock *MBB,
114 MachineBasicBlock::iterator IPt) {
115 unsigned &Reg = RegMap[V];
117 Reg = makeAnotherReg(V->getType());
120 // If this operand is a constant, emit the code to copy the constant into
121 // the register here...
123 if (Constant *C = dyn_cast<Constant>(V)) {
124 copyConstantToRegister(MBB, IPt, C, Reg);
125 RegMap.erase(V); // Assign a new name to this constant if ref'd again
126 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
127 // Move the address of the global into the register
129 // BuildMI(*MBB, IPt, V8::ORrr, 2, Reg).addReg(G0).addGlobalAddress(GV);
130 // We need to use SETHI and OR.
131 assert (0 && "Can't move address of global yet");
132 RegMap.erase(V); // Assign a new name to this address if ref'd again
141 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
142 return new V8ISel(TM);
146 cByte, cShort, cInt, cFloat, cDouble
149 static TypeClass getClass (const Type *T) {
150 switch (T->getPrimitiveID ()) {
151 case Type::UByteTyID: case Type::SByteTyID: return cByte;
152 case Type::UShortTyID: case Type::ShortTyID: return cShort;
153 case Type::UIntTyID: case Type::IntTyID: return cInt;
154 case Type::FloatTyID: return cFloat;
155 case Type::DoubleTyID: return cDouble;
157 assert (0 && "Type of unknown class passed to getClass?");
162 /// copyConstantToRegister - Output the instructions required to put the
163 /// specified constant into the specified register.
165 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
166 MachineBasicBlock::iterator IP,
167 Constant *C, unsigned R) {
168 if (ConstantInt *CI = dyn_cast<ConstantInt> (C)) {
169 unsigned Class = getClass(C->getType());
172 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm ((uint8_t) CI->getRawValue ());
175 unsigned TmpReg = makeAnotherReg (C->getType ());
176 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint16_t) CI->getRawValue ()) >> 10);
177 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint16_t) CI->getRawValue ()) & 0x03ff);
181 unsigned TmpReg = makeAnotherReg (C->getType ());
182 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (((uint32_t) CI->getRawValue ()) >> 10);
183 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
187 assert (0 && "Can't copy this kind of constant into register yet");
192 assert (0 && "Can't copy this kind of constant into register yet");
195 bool V8ISel::runOnFunction(Function &Fn) {
196 // First pass over the function, lower any unknown intrinsic functions
197 // with the IntrinsicLowering class.
198 LowerUnknownIntrinsicFunctionCalls(Fn);
200 F = &MachineFunction::construct(&Fn, TM);
202 // Create all of the machine basic blocks for the function...
203 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
204 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
208 // Set up a frame object for the return address. This is used by the
209 // llvm.returnaddress & llvm.frameaddress intrinisics.
210 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
212 // Copy incoming arguments off of the stack and out of fixed registers.
213 //LoadArgumentsToVirtualRegs(Fn);
215 // Instruction select everything except PHI nodes
218 // Select the PHI nodes
224 // We always build a machine code representation for the function
229 void V8ISel::visitReturnInst(ReturnInst &I) {
230 if (I.getNumOperands() == 0) {
231 // Just emit a 'jmpl' instruction to return.
232 BuildMI(BB, V8::JMPLi, 2, V8::G0).addZImm(8).addReg(V8::I7);
238 void V8ISel::visitBinaryOperator (BinaryOperator &I) {
239 unsigned DestReg = getReg (I);
240 unsigned Op0Reg = getReg (I.getOperand (0));
241 unsigned Op1Reg = getReg (I.getOperand (1));
243 unsigned ResultReg = makeAnotherReg (I.getType ());
244 switch (I.getOpcode ()) {
245 case Instruction::Add:
246 BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
248 case Instruction::Sub:
249 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
252 visitInstruction (I);
256 switch (getClass (I.getType ())) {
258 if (I.getType ()->isSigned ()) { // add byte
259 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
260 } else { // add ubyte
261 unsigned TmpReg = makeAnotherReg (I.getType ());
262 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
263 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
267 if (I.getType ()->isSigned ()) { // add short
268 unsigned TmpReg = makeAnotherReg (I.getType ());
269 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
270 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
271 } else { // add ushort
272 unsigned TmpReg = makeAnotherReg (I.getType ());
273 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
274 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (24);
278 BuildMI (BB, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (ResultReg);
281 visitInstruction (I);
287 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
288 /// function, lowering any calls to unknown intrinsic functions into the
289 /// equivalent LLVM code.
290 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
291 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
292 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
293 if (CallInst *CI = dyn_cast<CallInst>(I++))
294 if (Function *F = CI->getCalledFunction())
295 switch (F->getIntrinsicID()) {
296 case Intrinsic::not_intrinsic: break;
298 // All other intrinsic calls we must lower.
299 Instruction *Before = CI->getPrev();
300 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
301 if (Before) { // Move iterator to instruction after call
310 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
311 unsigned TmpReg1, TmpReg2;
313 default: assert(0 && "Intrinsic not supported!");