1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
33 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
35 MachineFunction *F; // The function we are compiling into
36 MachineBasicBlock *BB; // The current MBB we are compiling
38 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
40 // MBBMap - Mapping between LLVM BB -> Machine BB
41 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
43 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
45 /// runOnFunction - Top level implementation of instruction selection for
46 /// the entire function.
48 bool runOnFunction(Function &Fn);
50 virtual const char *getPassName() const {
51 return "SparcV8 Simple Instruction Selection";
54 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
55 /// constant expression GEP support.
57 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
58 Value *Src, User::op_iterator IdxBegin,
59 User::op_iterator IdxEnd, unsigned TargetReg);
61 /// emitCastOperation - Common code shared between visitCastInst and
62 /// constant expression cast support.
64 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
65 Value *Src, const Type *DestTy, unsigned TargetReg);
67 /// visitBasicBlock - This method is called when we are visiting a new basic
68 /// block. This simply creates a new MachineBasicBlock to emit code into
69 /// and adds it to the current MachineFunction. Subsequent visit* for
70 /// instructions will be invoked for all instructions in the basic block.
72 void visitBasicBlock(BasicBlock &LLVM_BB) {
73 BB = MBBMap[&LLVM_BB];
76 void visitBinaryOperator(Instruction &I);
77 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
78 void visitSetCondInst(SetCondInst &I);
79 void visitCallInst(CallInst &I);
80 void visitReturnInst(ReturnInst &I);
81 void visitBranchInst(BranchInst &I);
82 void visitCastInst(CastInst &I);
83 void visitLoadInst(LoadInst &I);
84 void visitStoreInst(StoreInst &I);
85 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
86 void visitGetElementPtrInst(GetElementPtrInst &I);
87 void visitAllocaInst(AllocaInst &I);
89 void visitInstruction(Instruction &I) {
90 std::cerr << "Unhandled instruction: " << I;
94 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
95 /// function, lowering any calls to unknown intrinsic functions into the
96 /// equivalent LLVM code.
97 void LowerUnknownIntrinsicFunctionCalls(Function &F);
98 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
100 void LoadArgumentsToVirtualRegs(Function *F);
102 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
103 /// because we have to generate our sources into the source basic blocks,
104 /// not the current one.
106 void SelectPHINodes();
108 /// copyConstantToRegister - Output the instructions required to put the
109 /// specified constant into the specified register.
111 void copyConstantToRegister(MachineBasicBlock *MBB,
112 MachineBasicBlock::iterator IP,
113 Constant *C, unsigned R);
115 /// makeAnotherReg - This method returns the next register number we haven't
118 /// Long values are handled somewhat specially. They are always allocated
119 /// as pairs of 32 bit integer values. The register number returned is the
120 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
121 /// of the long value.
123 unsigned makeAnotherReg(const Type *Ty) {
124 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
125 "Current target doesn't have SparcV8 reg info??");
126 const SparcV8RegisterInfo *MRI =
127 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
128 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
129 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
130 // Create the lower part
131 F->getSSARegMap()->createVirtualRegister(RC);
132 // Create the upper part.
133 return F->getSSARegMap()->createVirtualRegister(RC)-1;
136 // Add the mapping of regnumber => reg class to MachineFunction
137 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
138 return F->getSSARegMap()->createVirtualRegister(RC);
141 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
142 unsigned getReg(Value *V) {
143 // Just append to the end of the current bb.
144 MachineBasicBlock::iterator It = BB->end();
145 return getReg(V, BB, It);
147 unsigned getReg(Value *V, MachineBasicBlock *MBB,
148 MachineBasicBlock::iterator IPt) {
149 unsigned &Reg = RegMap[V];
151 Reg = makeAnotherReg(V->getType());
154 // If this operand is a constant, emit the code to copy the constant into
155 // the register here...
157 if (Constant *C = dyn_cast<Constant>(V)) {
158 copyConstantToRegister(MBB, IPt, C, Reg);
159 RegMap.erase(V); // Assign a new name to this constant if ref'd again
160 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
161 // Move the address of the global into the register
162 unsigned TmpReg = makeAnotherReg(V->getType());
163 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
164 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
165 .addGlobalAddress (GV);
166 RegMap.erase(V); // Assign a new name to this address if ref'd again
175 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
176 return new V8ISel(TM);
180 cByte, cShort, cInt, cLong, cFloat, cDouble
183 static TypeClass getClass (const Type *T) {
184 switch (T->getTypeID()) {
185 case Type::UByteTyID: case Type::SByteTyID: return cByte;
186 case Type::UShortTyID: case Type::ShortTyID: return cShort;
187 case Type::PointerTyID:
188 case Type::UIntTyID: case Type::IntTyID: return cInt;
189 case Type::ULongTyID: case Type::LongTyID: return cLong;
190 case Type::FloatTyID: return cFloat;
191 case Type::DoubleTyID: return cDouble;
193 assert (0 && "Type of unknown class passed to getClass?");
198 static TypeClass getClassB(const Type *T) {
199 if (T == Type::BoolTy) return cByte;
203 /// copyConstantToRegister - Output the instructions required to put the
204 /// specified constant into the specified register.
206 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
207 MachineBasicBlock::iterator IP,
208 Constant *C, unsigned R) {
209 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
210 switch (CE->getOpcode()) {
211 case Instruction::GetElementPtr:
212 emitGEPOperation(MBB, IP, CE->getOperand(0),
213 CE->op_begin()+1, CE->op_end(), R);
215 case Instruction::Cast:
216 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
219 std::cerr << "Copying this constant expr not yet handled: " << *CE;
224 if (C->getType()->isIntegral ()) {
226 unsigned Class = getClassB (C->getType ());
227 if (Class == cLong) {
228 unsigned TmpReg = makeAnotherReg (Type::IntTy);
229 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
230 // Copy the value into the register pair.
231 // R = top(more-significant) half, R+1 = bottom(less-significant) half
232 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
233 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
235 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
236 Val & 0xffffffffU), R+1);
240 assert(Class <= cInt && "Type not handled yet!");
242 if (C->getType() == Type::BoolTy) {
243 Val = (C == ConstantBool::True);
245 ConstantInt *CI = cast<ConstantInt> (C);
246 Val = CI->getRawValue ();
249 case cByte: Val = (int8_t) Val; break;
250 case cShort: Val = (int16_t) Val; break;
251 case cInt: Val = (int32_t) Val; break;
253 std::cerr << "Offending constant: " << *C << "\n";
254 assert (0 && "Can't copy this kind of constant into register yet");
258 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
259 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
260 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
262 unsigned TmpReg = makeAnotherReg (C->getType ());
263 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
264 .addSImm (((uint32_t) Val) >> 10);
265 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
266 .addSImm (((uint32_t) Val) & 0x03ff);
269 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
270 // We need to spill the constant to memory...
271 MachineConstantPool *CP = F->getConstantPool();
272 unsigned CPI = CP->getConstantPoolIndex(CFP);
273 const Type *Ty = CFP->getType();
274 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
275 unsigned AddrReg = makeAnotherReg (Type::UIntTy);
277 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
278 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
279 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
280 BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
281 .addConstantPoolIndex (CPI);
282 BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
283 } else if (isa<ConstantPointerNull>(C)) {
284 // Copy zero (null pointer) to the register.
285 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
286 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
287 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
288 // that SETHI %reg,global == SETHI %reg,%hi(global) and
289 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
290 unsigned TmpReg = makeAnotherReg (C->getType ());
291 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
292 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
294 std::cerr << "Offending constant: " << *C << "\n";
295 assert (0 && "Can't copy this kind of constant into register yet");
299 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
301 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
302 V8::I3, V8::I4, V8::I5 };
303 // Add IMPLICIT_DEFs of input regs.
305 for (Function::aiterator I = LF->abegin(), E = LF->aend();
306 I != E && ArgOffset < 6; ++I, ++ArgOffset) {
307 unsigned Reg = getReg(*I);
308 switch (getClassB(I->getType())) {
313 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
317 // Double and Long use register pairs.
318 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
321 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
324 assert (0 && "type not handled");
330 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E;
332 unsigned Reg = getReg(*I);
335 switch (getClassB(I->getType())) {
339 BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
340 .addReg (IncomingArgRegs[ArgOffset]);
343 // Single-fp args are passed in integer registers; go through
344 // memory to get them into FP registers. (Bleh!)
345 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
346 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
347 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
348 .addReg (IncomingArgRegs[ArgOffset]);
349 BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
353 // Double-fp args are passed in pairs of integer registers; go through
354 // memory to get them into FP registers. (Double bleh!)
355 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
356 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
357 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
358 .addReg (IncomingArgRegs[ArgOffset]);
360 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4)
361 .addReg (IncomingArgRegs[ArgOffset]);
362 BuildMI (BB, V8::LDDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
366 // FIXME: handle cLong
367 assert (0 && "64-bit int (long/ulong) function args not handled");
373 switch (getClassB(I->getType())) {
377 int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
378 BuildMI (BB, V8::LD, 2, Reg).addFrameIndex (FI).addSImm(0);
382 int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
383 BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
387 int FI = F->getFrameInfo()->CreateFixedObject(8, 68 + (4 * ArgOffset));
388 BuildMI (BB, V8::LDDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
392 // FIXME: handle cLong
393 assert (0 && "64-bit integer (long/ulong) function args not handled");
401 void V8ISel::SelectPHINodes() {
402 const TargetInstrInfo &TII = *TM.getInstrInfo();
403 const Function &LF = *F->getFunction(); // The LLVM function...
404 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
405 const BasicBlock *BB = I;
406 MachineBasicBlock &MBB = *MBBMap[I];
408 // Loop over all of the PHI nodes in the LLVM basic block...
409 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
410 for (BasicBlock::const_iterator I = BB->begin();
411 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
413 // Create a new machine instr PHI node, and insert it.
414 unsigned PHIReg = getReg(*PN);
415 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
416 V8::PHI, PN->getNumOperands(), PHIReg);
418 MachineInstr *LongPhiMI = 0;
419 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
420 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
421 V8::PHI, PN->getNumOperands(), PHIReg+1);
423 // PHIValues - Map of blocks to incoming virtual registers. We use this
424 // so that we only initialize one incoming value for a particular block,
425 // even if the block has multiple entries in the PHI node.
427 std::map<MachineBasicBlock*, unsigned> PHIValues;
429 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
430 MachineBasicBlock *PredMBB = 0;
431 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
432 PE = MBB.pred_end (); PI != PE; ++PI)
433 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
437 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
440 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
441 PHIValues.lower_bound(PredMBB);
443 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
444 // We already inserted an initialization of the register for this
445 // predecessor. Recycle it.
446 ValReg = EntryIt->second;
449 // Get the incoming value into a virtual register.
451 Value *Val = PN->getIncomingValue(i);
453 // If this is a constant or GlobalValue, we may have to insert code
454 // into the basic block to compute it into a virtual register.
455 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
456 isa<GlobalValue>(Val)) {
457 // Simple constants get emitted at the end of the basic block,
458 // before any terminator instructions. We "know" that the code to
459 // move a constant into a register will never clobber any flags.
460 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
462 // Because we don't want to clobber any values which might be in
463 // physical registers with the computation of this constant (which
464 // might be arbitrarily complex if it is a constant expression),
465 // just insert the computation at the top of the basic block.
466 MachineBasicBlock::iterator PI = PredMBB->begin();
468 // Skip over any PHI nodes though!
469 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
472 ValReg = getReg(Val, PredMBB, PI);
475 // Remember that we inserted a value for this PHI for this predecessor
476 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
479 PhiMI->addRegOperand(ValReg);
480 PhiMI->addMachineBasicBlockOperand(PredMBB);
482 LongPhiMI->addRegOperand(ValReg+1);
483 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
487 // Now that we emitted all of the incoming values for the PHI node, make
488 // sure to reposition the InsertPoint after the PHI that we just added.
489 // This is needed because we might have inserted a constant into this
490 // block, right after the PHI's which is before the old insert point!
491 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
497 bool V8ISel::runOnFunction(Function &Fn) {
498 // First pass over the function, lower any unknown intrinsic functions
499 // with the IntrinsicLowering class.
500 LowerUnknownIntrinsicFunctionCalls(Fn);
502 F = &MachineFunction::construct(&Fn, TM);
504 // Create all of the machine basic blocks for the function...
505 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
506 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
510 // Set up a frame object for the return address. This is used by the
511 // llvm.returnaddress & llvm.frameaddress intrinisics.
512 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
514 // Copy incoming arguments off of the stack and out of fixed registers.
515 LoadArgumentsToVirtualRegs(&Fn);
517 // Instruction select everything except PHI nodes
520 // Select the PHI nodes
526 // We always build a machine code representation for the function
530 void V8ISel::visitCastInst(CastInst &I) {
531 Value *Op = I.getOperand(0);
532 unsigned DestReg = getReg(I);
533 MachineBasicBlock::iterator MI = BB->end();
534 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
537 /// emitCastOperation - Common code shared between visitCastInst and constant
538 /// expression cast support.
540 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
541 MachineBasicBlock::iterator IP,
542 Value *Src, const Type *DestTy,
544 const Type *SrcTy = Src->getType();
545 unsigned SrcClass = getClassB(SrcTy);
546 unsigned DestClass = getClassB(DestTy);
547 unsigned SrcReg = getReg(Src, BB, IP);
549 const Type *oldTy = SrcTy;
550 const Type *newTy = DestTy;
551 unsigned oldTyClass = SrcClass;
552 unsigned newTyClass = DestClass;
554 if (oldTyClass < cLong && newTyClass < cLong) {
555 if (oldTyClass >= newTyClass) {
556 // Emit a reg->reg copy to do a equal-size or narrowing cast,
557 // and do sign/zero extension (necessary if we change signedness).
558 unsigned TmpReg1 = makeAnotherReg (newTy);
559 unsigned TmpReg2 = makeAnotherReg (newTy);
560 BuildMI (*BB, IP, V8::ORrr, 2, TmpReg1).addReg (V8::G0).addReg (SrcReg);
561 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
562 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
563 if (newTy->isSigned ()) { // sign-extend with SRA
564 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
565 } else { // zero-extend with SRL
566 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
569 unsigned TmpReg1 = makeAnotherReg (oldTy);
570 unsigned TmpReg2 = makeAnotherReg (newTy);
571 unsigned TmpReg3 = makeAnotherReg (newTy);
572 // Widening integer cast. Make sure it's fully sign/zero-extended
573 // wrt the input type, then make sure it's fully sign/zero-extended wrt
574 // the output type. Kind of stupid, but simple...
575 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (oldTy));
576 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg1).addZImm (shiftWidth).addReg(SrcReg);
577 if (oldTy->isSigned ()) { // sign-extend with SRA
578 BuildMI(*BB, IP, V8::SRAri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
579 } else { // zero-extend with SRL
580 BuildMI(*BB, IP, V8::SRLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
582 shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
583 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg3).addZImm (shiftWidth).addReg(TmpReg2);
584 if (newTy->isSigned ()) { // sign-extend with SRA
585 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
586 } else { // zero-extend with SRL
587 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
591 if (newTyClass == cFloat) {
592 assert (oldTyClass != cLong && "cast long to float not implemented yet");
593 switch (oldTyClass) {
595 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
598 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
601 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
602 // cast int to float. Store it to a stack slot and then load
603 // it using ldf into a floating point register. then do fitos.
604 unsigned TmpReg = makeAnotherReg (newTy);
605 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
606 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
608 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
609 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
613 } else if (newTyClass == cDouble) {
614 assert (oldTyClass != cLong && "cast long to double not implemented yet");
615 switch (oldTyClass) {
617 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
619 case cDouble: // use double move pseudo-instr
620 BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
623 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
624 unsigned TmpReg = makeAnotherReg (newTy);
625 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
626 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
628 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
629 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
633 } else if (newTyClass == cLong) {
634 if (oldTyClass == cLong) {
636 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
637 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
640 std::cerr << "Cast still unsupported: SrcTy = "
641 << *SrcTy << ", DestTy = " << *DestTy << "\n";
645 std::cerr << "Cast still unsupported: SrcTy = "
646 << *SrcTy << ", DestTy = " << *DestTy << "\n";
652 void V8ISel::visitLoadInst(LoadInst &I) {
653 unsigned DestReg = getReg (I);
654 unsigned PtrReg = getReg (I.getOperand (0));
655 switch (getClassB (I.getType ())) {
657 if (I.getType ()->isSigned ())
658 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
660 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
663 if (I.getType ()->isSigned ())
664 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
666 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
669 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
672 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
673 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
676 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
679 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
682 std::cerr << "Load instruction not handled: " << I;
688 void V8ISel::visitStoreInst(StoreInst &I) {
689 Value *SrcVal = I.getOperand (0);
690 unsigned SrcReg = getReg (SrcVal);
691 unsigned PtrReg = getReg (I.getOperand (1));
692 switch (getClassB (SrcVal->getType ())) {
694 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
697 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
700 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
703 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
704 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
707 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
710 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
713 std::cerr << "Store instruction not handled: " << I;
719 void V8ISel::visitCallInst(CallInst &I) {
720 MachineInstr *TheCall;
721 // Is it an intrinsic function call?
722 if (Function *F = I.getCalledFunction()) {
723 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
724 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
729 unsigned extraStack = 0;
730 // How much extra call stack will we need?
731 for (unsigned i = 7; i < I.getNumOperands (); ++i) {
732 switch (getClassB (I.getOperand (i)->getType ())) {
733 case cLong: extraStack += 8; break;
734 case cFloat: extraStack += 4; break;
735 case cDouble: extraStack += 8; break;
736 default: extraStack += 4; break;
741 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
743 for (unsigned i = 1; i < I.getNumOperands (); ++i) {
744 unsigned ArgReg = getReg (I.getOperand (i));
746 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
747 // Schlep it over into the incoming arg register
748 BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0)
750 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
751 // Single-fp args are passed in integer registers; go through
752 // memory to get them out of FP registers. (Bleh!)
753 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
754 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
755 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0)
757 BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
759 } else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
760 // Double-fp args are passed in pairs of integer registers; go through
761 // memory to get them out of FP registers. (Bleh!)
762 assert (i <= 5 && "Can't deal with double-fp args past #5 yet");
763 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
764 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
765 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
767 BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
769 BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i]).addFrameIndex (FI)
772 assert (0 && "64-bit (double, long, etc.) 'call' opnds not handled");
775 if (i == 7 && extraStack)
776 BuildMI (BB, V8::ADJCALLSTACKDOWN, 1).addImm (extraStack);
777 // Store arg into designated outgoing-arg stack slot
778 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
779 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (64+4*i)
782 assert (0 && "can't push this kind of excess arg on stack yet");
787 // Emit call instruction
788 if (Function *F = I.getCalledFunction ()) {
789 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
790 } else { // Emit an indirect call...
791 unsigned Reg = getReg (I.getCalledValue ());
792 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
795 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKUP, 1).addImm (extraStack);
797 // Deal w/ return value: schlep it over into the destination register
798 if (I.getType () == Type::VoidTy)
800 unsigned DestReg = getReg (I);
801 switch (getClassB (I.getType ())) {
805 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
808 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
811 BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
814 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
815 BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
818 std::cerr << "Return type of call instruction not handled: " << I;
823 void V8ISel::visitReturnInst(ReturnInst &I) {
824 if (I.getNumOperands () == 1) {
825 unsigned RetValReg = getReg (I.getOperand (0));
826 switch (getClassB (I.getOperand (0)->getType ())) {
830 // Schlep it over into i0 (where it will become o0 after restore).
831 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
834 BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
837 BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
840 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
841 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
844 std::cerr << "Return instruction of this type not handled: " << I;
849 // Just emit a 'retl' instruction to return.
850 BuildMI(BB, V8::RETL, 0);
854 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
855 Function::iterator I = BB; ++I; // Get iterator to next block
856 return I != BB->getParent()->end() ? &*I : 0;
859 /// visitBranchInst - Handles conditional and unconditional branches.
861 void V8ISel::visitBranchInst(BranchInst &I) {
862 BasicBlock *takenSucc = I.getSuccessor (0);
863 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
864 BB->addSuccessor (takenSuccMBB);
865 if (I.isConditional()) { // conditional branch
866 BasicBlock *notTakenSucc = I.getSuccessor (1);
867 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
868 BB->addSuccessor (notTakenSuccMBB);
870 // CondReg=(<condition>);
871 // If (CondReg==0) goto notTakenSuccMBB;
872 unsigned CondReg = getReg (I.getCondition ());
873 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
874 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
876 // goto takenSuccMBB;
877 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
880 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
881 /// constant expression GEP support.
883 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
884 MachineBasicBlock::iterator IP,
885 Value *Src, User::op_iterator IdxBegin,
886 User::op_iterator IdxEnd, unsigned TargetReg) {
887 const TargetData &TD = TM.getTargetData ();
888 const Type *Ty = Src->getType ();
889 unsigned basePtrReg = getReg (Src, MBB, IP);
891 // GEPs have zero or more indices; we must perform a struct access
892 // or array access for each one.
893 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
896 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
897 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
898 // It's a struct access. idx is the index into the structure,
899 // which names the field. Use the TargetData structure to
900 // pick out what the layout of the structure is in memory.
901 // Use the (constant) structure index's value to find the
902 // right byte offset from the StructLayout class's list of
903 // structure member offsets.
904 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
905 unsigned memberOffset =
906 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
907 // Emit an ADD to add memberOffset to the basePtr.
908 BuildMI (*MBB, IP, V8::ADDri, 2,
909 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
910 // The next type is the member of the structure selected by the
912 Ty = StTy->getElementType (fieldIndex);
913 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
914 // It's an array or pointer access: [ArraySize x ElementType].
915 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
916 // must find the size of the pointed-to type (Not coincidentally, the next
917 // type is the type of the elements in the array).
918 Ty = SqTy->getElementType ();
919 unsigned elementSize = TD.getTypeSize (Ty);
920 unsigned idxReg = getReg (idx, MBB, IP);
921 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
922 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
923 copyConstantToRegister (MBB, IP,
924 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
925 // Emit a SMUL to multiply the register holding the index by
926 // elementSize, putting the result in OffsetReg.
927 BuildMI (*MBB, IP, V8::SMULrr, 2,
928 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
929 // Emit an ADD to add OffsetReg to the basePtr.
930 BuildMI (*MBB, IP, V8::ADDrr, 2,
931 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
933 basePtrReg = nextBasePtrReg;
935 // After we have processed all the indices, the result is left in
936 // basePtrReg. Move it to the register where we were expected to
938 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
941 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
942 unsigned outputReg = getReg (I);
943 emitGEPOperation (BB, BB->end (), I.getOperand (0),
944 I.op_begin ()+1, I.op_end (), outputReg);
948 void V8ISel::visitBinaryOperator (Instruction &I) {
949 unsigned DestReg = getReg (I);
950 unsigned Op0Reg = getReg (I.getOperand (0));
951 unsigned Op1Reg = getReg (I.getOperand (1));
953 unsigned Class = getClassB (I.getType());
954 unsigned OpCase = ~0;
957 switch (I.getOpcode ()) {
958 case Instruction::Add: OpCase = 0; break;
959 case Instruction::Sub: OpCase = 1; break;
960 case Instruction::Mul: OpCase = 2; break;
961 case Instruction::Div: OpCase = 3; break;
962 default: visitInstruction (I); return;
964 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
965 V8::FSUBS, V8::FSUBD,
966 V8::FMULS, V8::FMULD,
967 V8::FDIVS, V8::FDIVD };
968 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
969 .addReg (Op0Reg).addReg (Op1Reg);
973 unsigned ResultReg = DestReg;
974 if (Class != cInt && Class != cLong)
975 ResultReg = makeAnotherReg (I.getType ());
977 if (Class == cLong) {
978 DEBUG (std::cerr << "Class = cLong\n");
979 DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
980 DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
981 DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
982 DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
985 // FIXME: support long, ulong.
986 switch (I.getOpcode ()) {
987 case Instruction::Add: OpCase = 0; break;
988 case Instruction::Sub: OpCase = 1; break;
989 case Instruction::Mul: OpCase = 2; break;
990 case Instruction::And: OpCase = 3; break;
991 case Instruction::Or: OpCase = 4; break;
992 case Instruction::Xor: OpCase = 5; break;
993 case Instruction::Shl: OpCase = 6; break;
994 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
996 case Instruction::Div:
997 case Instruction::Rem: {
998 unsigned Dest = ResultReg;
999 if (I.getOpcode() == Instruction::Rem)
1000 Dest = makeAnotherReg(I.getType());
1002 // FIXME: this is probably only right for 32 bit operands.
1003 if (I.getType ()->isSigned()) {
1004 unsigned Tmp = makeAnotherReg (I.getType ());
1005 // Sign extend into the Y register
1006 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
1007 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
1008 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1010 // Zero extend into the Y register, ie, just set it to zero
1011 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
1012 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1015 if (I.getOpcode() == Instruction::Rem) {
1016 unsigned Tmp = makeAnotherReg (I.getType ());
1017 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
1018 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
1023 visitInstruction (I);
1027 static const unsigned Opcodes[] = {
1028 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
1029 V8::SLLrr, V8::SRLrr, V8::SRArr
1031 if (OpCase != ~0U) {
1032 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1035 switch (getClassB (I.getType ())) {
1037 if (I.getType ()->isSigned ()) { // add byte
1038 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
1039 } else { // add ubyte
1040 unsigned TmpReg = makeAnotherReg (I.getType ());
1041 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
1042 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
1046 if (I.getType ()->isSigned ()) { // add short
1047 unsigned TmpReg = makeAnotherReg (I.getType ());
1048 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1049 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
1050 } else { // add ushort
1051 unsigned TmpReg = makeAnotherReg (I.getType ());
1052 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1053 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
1057 // Nothing to do here.
1060 // Only support and, or, xor.
1061 if (OpCase < 3 || OpCase > 5) {
1062 visitInstruction (I);
1065 // Do the other half of the value:
1066 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
1070 visitInstruction (I);
1074 void V8ISel::visitSetCondInst(SetCondInst &I) {
1075 unsigned Op0Reg = getReg (I.getOperand (0));
1076 unsigned Op1Reg = getReg (I.getOperand (1));
1077 unsigned DestReg = getReg (I);
1078 const Type *Ty = I.getOperand (0)->getType ();
1080 // Compare the two values.
1081 assert (getClass (Ty) != cLong && "can't setcc on longs yet");
1082 if (getClass (Ty) < cLong) {
1083 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1084 } else if (getClass (Ty) == cFloat) {
1085 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1086 } else if (getClass (Ty) == cDouble) {
1087 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1091 switch (I.getOpcode()) {
1092 default: assert(0 && "Unknown setcc instruction!");
1093 case Instruction::SetEQ: BranchIdx = 0; break;
1094 case Instruction::SetNE: BranchIdx = 1; break;
1095 case Instruction::SetLT: BranchIdx = 2; break;
1096 case Instruction::SetGT: BranchIdx = 3; break;
1097 case Instruction::SetLE: BranchIdx = 4; break;
1098 case Instruction::SetGE: BranchIdx = 5; break;
1100 unsigned Column = 0;
1101 if (Ty->isSigned()) ++Column;
1102 if (Ty->isFloatingPoint()) ++Column;
1103 static unsigned OpcodeTab[3*6] = {
1105 // unsigned signed fp
1106 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1107 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1108 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1109 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1110 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1111 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1113 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1115 MachineBasicBlock *thisMBB = BB;
1116 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1119 // subcc %reg0, %reg1, %g0
1123 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1124 // if we could insert other, non-terminator instructions after the
1125 // bCC. But MBB->getFirstTerminator() can't understand this.
1126 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
1127 F->getBasicBlockList ().push_back (copy1MBB);
1128 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
1129 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1130 F->getBasicBlockList ().push_back (copy0MBB);
1131 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
1132 // Update machine-CFG edges
1133 BB->addSuccessor (copy1MBB);
1134 BB->addSuccessor (copy0MBB);
1137 // %FalseValue = or %G0, 0
1140 unsigned FalseValue = makeAnotherReg (I.getType ());
1141 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
1142 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1143 F->getBasicBlockList ().push_back (sinkMBB);
1144 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1145 // Update machine-CFG edges
1146 BB->addSuccessor (sinkMBB);
1148 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1149 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
1150 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1151 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1154 // %TrueValue = or %G0, 1
1157 unsigned TrueValue = makeAnotherReg (I.getType ());
1158 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1159 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1160 // Update machine-CFG edges
1161 BB->addSuccessor (sinkMBB);
1164 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1167 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1168 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1171 void V8ISel::visitAllocaInst(AllocaInst &I) {
1172 // Find the data size of the alloca inst's getAllocatedType.
1173 const Type *Ty = I.getAllocatedType();
1174 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1176 unsigned ArraySizeReg = getReg (I.getArraySize ());
1177 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1178 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1179 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1180 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1182 // StackAdjReg = (ArraySize * TySize) rounded up to nearest doubleword boundary
1183 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1185 // Round up TmpReg1 to nearest doubleword boundary:
1186 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1187 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1189 // Subtract size from stack pointer, thereby allocating some space.
1190 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1192 // Put a pointer to the space into the result register, by copying
1193 // the stack pointer.
1194 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1196 // Inform the Frame Information that we have just allocated a variable-sized
1198 F->getFrameInfo()->CreateVariableSizedObject();
1201 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1202 /// function, lowering any calls to unknown intrinsic functions into the
1203 /// equivalent LLVM code.
1204 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1205 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1206 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1207 if (CallInst *CI = dyn_cast<CallInst>(I++))
1208 if (Function *F = CI->getCalledFunction())
1209 switch (F->getIntrinsicID()) {
1210 case Intrinsic::not_intrinsic: break;
1212 // All other intrinsic calls we must lower.
1213 Instruction *Before = CI->getPrev();
1214 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1215 if (Before) { // Move iterator to instruction after call
1224 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1225 unsigned TmpReg1, TmpReg2;
1227 default: assert(0 && "Intrinsic not supported!");