1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
33 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
35 MachineFunction *F; // The function we are compiling into
36 MachineBasicBlock *BB; // The current MBB we are compiling
37 int VarArgsOffset; // Offset from fp for start of varargs area
39 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
41 // MBBMap - Mapping between LLVM BB -> Machine BB
42 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
44 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
46 /// runOnFunction - Top level implementation of instruction selection for
47 /// the entire function.
49 bool runOnFunction(Function &Fn);
51 virtual const char *getPassName() const {
52 return "SparcV8 Simple Instruction Selection";
55 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
56 /// constant expression GEP support.
58 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
59 Value *Src, User::op_iterator IdxBegin,
60 User::op_iterator IdxEnd, unsigned TargetReg);
62 /// emitCastOperation - Common code shared between visitCastInst and
63 /// constant expression cast support.
65 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
66 Value *Src, const Type *DestTy, unsigned TargetReg);
68 /// emitIntegerCast, emitFPToIntegerCast - Helper methods for
69 /// emitCastOperation.
71 unsigned emitIntegerCast (MachineBasicBlock *BB,
72 MachineBasicBlock::iterator IP,
73 const Type *oldTy, unsigned SrcReg,
74 const Type *newTy, unsigned DestReg);
75 void emitFPToIntegerCast (MachineBasicBlock *BB,
76 MachineBasicBlock::iterator IP, const Type *oldTy,
77 unsigned SrcReg, const Type *newTy,
80 /// visitBasicBlock - This method is called when we are visiting a new basic
81 /// block. This simply creates a new MachineBasicBlock to emit code into
82 /// and adds it to the current MachineFunction. Subsequent visit* for
83 /// instructions will be invoked for all instructions in the basic block.
85 void visitBasicBlock(BasicBlock &LLVM_BB) {
86 BB = MBBMap[&LLVM_BB];
89 void emitOp64LibraryCall (MachineBasicBlock *MBB,
90 MachineBasicBlock::iterator IP,
91 unsigned DestReg, const char *FuncName,
92 unsigned Op0Reg, unsigned Op1Reg);
93 void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
94 Instruction &I, unsigned DestReg, unsigned Op0Reg,
96 void visitBinaryOperator(Instruction &I);
97 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
98 void visitSetCondInst(SetCondInst &I);
99 void visitCallInst(CallInst &I);
100 void visitReturnInst(ReturnInst &I);
101 void visitBranchInst(BranchInst &I);
102 void visitUnreachableInst(UnreachableInst &I) {}
103 void visitCastInst(CastInst &I);
104 void visitVANextInst(VANextInst &I);
105 void visitVAArgInst(VAArgInst &I);
106 void visitLoadInst(LoadInst &I);
107 void visitStoreInst(StoreInst &I);
108 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
109 void visitGetElementPtrInst(GetElementPtrInst &I);
110 void visitAllocaInst(AllocaInst &I);
112 void visitInstruction(Instruction &I) {
113 std::cerr << "Unhandled instruction: " << I;
117 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
118 /// function, lowering any calls to unknown intrinsic functions into the
119 /// equivalent LLVM code.
120 void LowerUnknownIntrinsicFunctionCalls(Function &F);
121 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
123 void LoadArgumentsToVirtualRegs(Function *F);
125 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
126 /// because we have to generate our sources into the source basic blocks,
127 /// not the current one.
129 void SelectPHINodes();
131 /// copyConstantToRegister - Output the instructions required to put the
132 /// specified constant into the specified register.
134 void copyConstantToRegister(MachineBasicBlock *MBB,
135 MachineBasicBlock::iterator IP,
136 Constant *C, unsigned R);
138 /// makeAnotherReg - This method returns the next register number we haven't
141 /// Long values are handled somewhat specially. They are always allocated
142 /// as pairs of 32 bit integer values. The register number returned is the
143 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
144 /// of the long value.
146 unsigned makeAnotherReg(const Type *Ty) {
147 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
148 "Current target doesn't have SparcV8 reg info??");
149 const SparcV8RegisterInfo *MRI =
150 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
151 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
152 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
153 // Create the lower part
154 F->getSSARegMap()->createVirtualRegister(RC);
155 // Create the upper part.
156 return F->getSSARegMap()->createVirtualRegister(RC)-1;
159 // Add the mapping of regnumber => reg class to MachineFunction
160 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
161 return F->getSSARegMap()->createVirtualRegister(RC);
164 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
165 unsigned getReg(Value *V) {
166 // Just append to the end of the current bb.
167 MachineBasicBlock::iterator It = BB->end();
168 return getReg(V, BB, It);
170 unsigned getReg(Value *V, MachineBasicBlock *MBB,
171 MachineBasicBlock::iterator IPt) {
172 unsigned &Reg = RegMap[V];
174 Reg = makeAnotherReg(V->getType());
177 // If this operand is a constant, emit the code to copy the constant into
178 // the register here...
180 if (Constant *C = dyn_cast<Constant>(V)) {
181 copyConstantToRegister(MBB, IPt, C, Reg);
182 RegMap.erase(V); // Assign a new name to this constant if ref'd again
183 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
184 // Move the address of the global into the register
185 unsigned TmpReg = makeAnotherReg(V->getType());
186 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
187 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
188 .addGlobalAddress (GV);
189 RegMap.erase(V); // Assign a new name to this address if ref'd again
198 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
199 return new V8ISel(TM);
203 cByte, cShort, cInt, cLong, cFloat, cDouble
206 static TypeClass getClass (const Type *T) {
207 switch (T->getTypeID()) {
208 case Type::UByteTyID: case Type::SByteTyID: return cByte;
209 case Type::UShortTyID: case Type::ShortTyID: return cShort;
210 case Type::PointerTyID:
211 case Type::UIntTyID: case Type::IntTyID: return cInt;
212 case Type::ULongTyID: case Type::LongTyID: return cLong;
213 case Type::FloatTyID: return cFloat;
214 case Type::DoubleTyID: return cDouble;
216 assert (0 && "Type of unknown class passed to getClass?");
221 static TypeClass getClassB(const Type *T) {
222 if (T == Type::BoolTy) return cByte;
226 /// copyConstantToRegister - Output the instructions required to put the
227 /// specified constant into the specified register.
229 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
230 MachineBasicBlock::iterator IP,
231 Constant *C, unsigned R) {
232 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
233 switch (CE->getOpcode()) {
234 case Instruction::GetElementPtr:
235 emitGEPOperation(MBB, IP, CE->getOperand(0),
236 CE->op_begin()+1, CE->op_end(), R);
238 case Instruction::Cast:
239 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
242 std::cerr << "Copying this constant expr not yet handled: " << *CE;
245 } else if (isa<UndefValue>(C)) {
246 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
247 if (getClassB (C->getType ()) == cLong)
248 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
252 if (C->getType()->isIntegral ()) {
254 unsigned Class = getClassB (C->getType ());
255 if (Class == cLong) {
256 unsigned TmpReg = makeAnotherReg (Type::IntTy);
257 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
258 // Copy the value into the register pair.
259 // R = top(more-significant) half, R+1 = bottom(less-significant) half
260 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
261 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
263 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
264 Val & 0xffffffffU), R+1);
268 assert(Class <= cInt && "Type not handled yet!");
270 if (C->getType() == Type::BoolTy) {
271 Val = (C == ConstantBool::True);
273 ConstantInt *CI = cast<ConstantInt> (C);
274 Val = CI->getRawValue ();
277 case cByte: Val = (int8_t) Val; break;
278 case cShort: Val = (int16_t) Val; break;
279 case cInt: Val = (int32_t) Val; break;
281 std::cerr << "Offending constant: " << *C << "\n";
282 assert (0 && "Can't copy this kind of constant into register yet");
286 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
287 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
288 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
290 unsigned TmpReg = makeAnotherReg (C->getType ());
291 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
292 .addSImm (((uint32_t) Val) >> 10);
293 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
294 .addSImm (((uint32_t) Val) & 0x03ff);
297 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
298 // We need to spill the constant to memory...
299 MachineConstantPool *CP = F->getConstantPool();
300 unsigned CPI = CP->getConstantPoolIndex(CFP);
301 const Type *Ty = CFP->getType();
302 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
303 unsigned AddrReg = makeAnotherReg (Type::UIntTy);
305 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
306 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
307 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
308 BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
309 .addConstantPoolIndex (CPI);
310 BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
311 } else if (isa<ConstantPointerNull>(C)) {
312 // Copy zero (null pointer) to the register.
313 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
314 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
315 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
316 // that SETHI %reg,global == SETHI %reg,%hi(global) and
317 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
318 unsigned TmpReg = makeAnotherReg (C->getType ());
319 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
320 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
322 std::cerr << "Offending constant: " << *C << "\n";
323 assert (0 && "Can't copy this kind of constant into register yet");
327 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
328 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
329 V8::I3, V8::I4, V8::I5 };
331 // Add IMPLICIT_DEFs of input regs.
333 for (Function::aiterator I = LF->abegin(), E = LF->aend();
334 I != E && ArgNo < 6; ++I, ++ArgNo) {
335 switch (getClassB(I->getType())) {
340 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
344 // Double and Long use register pairs.
345 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
348 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
351 assert (0 && "type not handled");
356 const unsigned *IAREnd = &IncomingArgRegs[6];
357 const unsigned *IAR = &IncomingArgRegs[0];
358 unsigned ArgOffset = 68;
360 // Store registers onto stack if this is a varargs function.
361 // FIXME: This doesn't really pertain to "loading arguments into
362 // virtual registers", so it's not clear that it really belongs here.
363 // FIXME: We could avoid storing any args onto the stack that don't
364 // need to be in memory, because they come before the ellipsis in the
365 // parameter list (and thus could never be accessed through va_arg).
366 if (LF->getFunctionType ()->isVarArg ()) {
367 for (unsigned i = 0; i < 6; ++i) {
368 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
369 assert (IAR != IAREnd
370 && "About to dereference past end of IncomingArgRegs");
371 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
374 // Reset the pointers now that we're done.
376 IAR = &IncomingArgRegs[0];
379 // Copy args out of their incoming hard regs or stack slots into virtual regs.
380 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
382 unsigned ArgReg = getReg (A);
383 if (getClassB (A.getType ()) < cLong) {
384 // Get it out of the incoming arg register
385 if (ArgOffset < 92) {
386 assert (IAR != IAREnd
387 && "About to dereference past end of IncomingArgRegs");
388 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
390 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
391 BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
394 } else if (getClassB (A.getType ()) == cFloat) {
395 if (ArgOffset < 92) {
396 // Single-fp args are passed in integer registers; go through
397 // memory to get them out of integer registers and back into fp. (Bleh!)
398 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
399 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
400 assert (IAR != IAREnd
401 && "About to dereference past end of IncomingArgRegs");
402 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
403 BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
405 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
406 BuildMI (BB, V8::LDFri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
409 } else if (getClassB (A.getType ()) == cDouble) {
410 // Double-fp args are passed in pairs of integer registers; go through
411 // memory to get them out of integer registers and back into fp. (Bleh!)
412 // We'd like to 'ldd' these right out of the incoming-args area,
413 // but it might not be 8-byte aligned (e.g., call x(int x, double d)).
414 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
415 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
416 if (ArgOffset < 92 && IAR != IAREnd) {
417 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
419 unsigned TempReg = makeAnotherReg (Type::IntTy);
420 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
421 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
424 if (ArgOffset < 92 && IAR != IAREnd) {
425 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
427 unsigned TempReg = makeAnotherReg (Type::IntTy);
428 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
429 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
432 BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
433 } else if (getClassB (A.getType ()) == cLong) {
434 // do the first half...
435 if (ArgOffset < 92) {
436 assert (IAR != IAREnd
437 && "About to dereference past end of IncomingArgRegs");
438 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
440 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
441 BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
444 // ...then do the second half
445 if (ArgOffset < 92) {
446 assert (IAR != IAREnd
447 && "About to dereference past end of IncomingArgRegs");
448 BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
450 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
451 BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
455 assert (0 && "Unknown class?!");
459 // If the function takes variable number of arguments, remember the fp
460 // offset for the start of the first vararg value... this is used to expand
462 if (LF->getFunctionType ()->isVarArg ())
463 VarArgsOffset = ArgOffset;
466 void V8ISel::SelectPHINodes() {
467 const TargetInstrInfo &TII = *TM.getInstrInfo();
468 const Function &LF = *F->getFunction(); // The LLVM function...
469 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
470 const BasicBlock *BB = I;
471 MachineBasicBlock &MBB = *MBBMap[I];
473 // Loop over all of the PHI nodes in the LLVM basic block...
474 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
475 for (BasicBlock::const_iterator I = BB->begin();
476 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
478 // Create a new machine instr PHI node, and insert it.
479 unsigned PHIReg = getReg(*PN);
480 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
481 V8::PHI, PN->getNumOperands(), PHIReg);
483 MachineInstr *LongPhiMI = 0;
484 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
485 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
486 V8::PHI, PN->getNumOperands(), PHIReg+1);
488 // PHIValues - Map of blocks to incoming virtual registers. We use this
489 // so that we only initialize one incoming value for a particular block,
490 // even if the block has multiple entries in the PHI node.
492 std::map<MachineBasicBlock*, unsigned> PHIValues;
494 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
495 MachineBasicBlock *PredMBB = 0;
496 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
497 PE = MBB.pred_end (); PI != PE; ++PI)
498 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
502 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
505 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
506 PHIValues.lower_bound(PredMBB);
508 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
509 // We already inserted an initialization of the register for this
510 // predecessor. Recycle it.
511 ValReg = EntryIt->second;
514 // Get the incoming value into a virtual register.
516 Value *Val = PN->getIncomingValue(i);
518 // If this is a constant or GlobalValue, we may have to insert code
519 // into the basic block to compute it into a virtual register.
520 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
521 isa<GlobalValue>(Val)) {
522 // Simple constants get emitted at the end of the basic block,
523 // before any terminator instructions. We "know" that the code to
524 // move a constant into a register will never clobber any flags.
525 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
527 // Because we don't want to clobber any values which might be in
528 // physical registers with the computation of this constant (which
529 // might be arbitrarily complex if it is a constant expression),
530 // just insert the computation at the top of the basic block.
531 MachineBasicBlock::iterator PI = PredMBB->begin();
533 // Skip over any PHI nodes though!
534 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
537 ValReg = getReg(Val, PredMBB, PI);
540 // Remember that we inserted a value for this PHI for this predecessor
541 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
544 PhiMI->addRegOperand(ValReg);
545 PhiMI->addMachineBasicBlockOperand(PredMBB);
547 LongPhiMI->addRegOperand(ValReg+1);
548 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
552 // Now that we emitted all of the incoming values for the PHI node, make
553 // sure to reposition the InsertPoint after the PHI that we just added.
554 // This is needed because we might have inserted a constant into this
555 // block, right after the PHI's which is before the old insert point!
556 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
562 bool V8ISel::runOnFunction(Function &Fn) {
563 // First pass over the function, lower any unknown intrinsic functions
564 // with the IntrinsicLowering class.
565 LowerUnknownIntrinsicFunctionCalls(Fn);
567 F = &MachineFunction::construct(&Fn, TM);
569 // Create all of the machine basic blocks for the function...
570 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
571 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
575 // Set up a frame object for the return address. This is used by the
576 // llvm.returnaddress & llvm.frameaddress intrinisics.
577 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
579 // Copy incoming arguments off of the stack and out of fixed registers.
580 LoadArgumentsToVirtualRegs(&Fn);
582 // Instruction select everything except PHI nodes
585 // Select the PHI nodes
591 // We always build a machine code representation for the function
595 void V8ISel::visitCastInst(CastInst &I) {
596 Value *Op = I.getOperand(0);
597 unsigned DestReg = getReg(I);
598 MachineBasicBlock::iterator MI = BB->end();
599 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
602 unsigned V8ISel::emitIntegerCast (MachineBasicBlock *BB,
603 MachineBasicBlock::iterator IP, const Type *oldTy,
604 unsigned SrcReg, const Type *newTy,
606 if (oldTy == newTy) {
607 // No-op cast - just emit a copy; assume the reg. allocator will zap it.
608 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg(SrcReg);
611 // Emit left-shift, then right-shift to sign- or zero-extend.
612 unsigned TmpReg = makeAnotherReg (newTy);
613 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
614 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg).addZImm (shiftWidth).addReg(SrcReg);
615 if (newTy->isSigned ()) { // sign-extend with SRA
616 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
617 } else { // zero-extend with SRL
618 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
620 // Return the temp reg. in case this is one half of a cast to long.
624 void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
625 MachineBasicBlock::iterator IP,
626 const Type *oldTy, unsigned SrcReg,
627 const Type *newTy, unsigned DestReg) {
628 unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
629 unsigned oldTyClass = getClassB(oldTy);
630 if (oldTyClass == cFloat) {
631 FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
632 FPAlign = TM.getTargetData().getFloatAlignment();
633 } else { // it's a double
634 FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
635 FPAlign = TM.getTargetData().getDoubleAlignment();
637 unsigned TempReg = makeAnotherReg (oldTy);
638 BuildMI (*BB, IP, FPCastOpcode, 1, TempReg).addReg (SrcReg);
639 int FI = F->getFrameInfo()->CreateStackObject(FPSize, FPAlign);
640 BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
642 unsigned TempReg2 = makeAnotherReg (newTy);
643 BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
644 emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
647 /// emitCastOperation - Common code shared between visitCastInst and constant
648 /// expression cast support.
650 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
651 MachineBasicBlock::iterator IP, Value *Src,
652 const Type *DestTy, unsigned DestReg) {
653 const Type *SrcTy = Src->getType();
654 unsigned SrcClass = getClassB(SrcTy);
655 unsigned DestClass = getClassB(DestTy);
656 unsigned SrcReg = getReg(Src, BB, IP);
658 const Type *oldTy = SrcTy;
659 const Type *newTy = DestTy;
660 unsigned oldTyClass = SrcClass;
661 unsigned newTyClass = DestClass;
663 if (oldTyClass < cLong && newTyClass < cLong) {
664 emitIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
665 } else switch (newTyClass) {
669 switch (oldTyClass) {
671 // Treat it like a cast from the lower half of the value.
672 emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
676 emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
678 default: goto not_yet;
683 switch (oldTyClass) {
684 case cLong: goto not_yet;
686 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
689 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
692 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
693 // cast integer type to float. Store it to a stack slot and then load
694 // it using ldf into a floating point register. then do fitos.
695 unsigned TmpReg = makeAnotherReg (newTy);
696 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
697 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
699 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
700 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
707 switch (oldTyClass) {
708 case cLong: goto not_yet;
710 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
712 case cDouble: // use double move pseudo-instr
713 BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
716 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
717 unsigned TmpReg = makeAnotherReg (newTy);
718 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
719 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
721 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
722 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
729 switch (oldTyClass) {
733 // Cast to (u)int in the bottom half, and sign(zero) extend in the top
735 const Type *OldHalfTy = oldTy->isSigned() ? Type::IntTy : Type::UIntTy;
736 const Type *NewHalfTy = newTy->isSigned() ? Type::IntTy : Type::UIntTy;
737 unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
738 NewHalfTy, DestReg+1);
739 if (newTy->isSigned ()) {
740 BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
743 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
749 // Just copy both halves.
750 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
751 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
754 default: goto not_yet;
758 default: goto not_yet;
762 std::cerr << "Sorry, cast still unsupported: SrcTy = " << *SrcTy
763 << ", DestTy = " << *DestTy << "\n";
767 void V8ISel::visitLoadInst(LoadInst &I) {
768 unsigned DestReg = getReg (I);
769 unsigned PtrReg = getReg (I.getOperand (0));
770 switch (getClassB (I.getType ())) {
772 if (I.getType ()->isSigned ())
773 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
775 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
778 if (I.getType ()->isSigned ())
779 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
781 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
784 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
787 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
788 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
791 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
794 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
797 std::cerr << "Load instruction not handled: " << I;
803 void V8ISel::visitStoreInst(StoreInst &I) {
804 Value *SrcVal = I.getOperand (0);
805 unsigned SrcReg = getReg (SrcVal);
806 unsigned PtrReg = getReg (I.getOperand (1));
807 switch (getClassB (SrcVal->getType ())) {
809 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
812 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
815 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
818 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
819 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
822 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
825 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
828 std::cerr << "Store instruction not handled: " << I;
834 void V8ISel::visitCallInst(CallInst &I) {
835 MachineInstr *TheCall;
836 // Is it an intrinsic function call?
837 if (Function *F = I.getCalledFunction()) {
838 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
839 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
844 // How much extra call stack will we need?
846 for (unsigned i = 0; i < I.getNumOperands (); ++i) {
847 switch (getClassB (I.getOperand (i)->getType ())) {
848 case cLong: extraStack += 8; break;
849 case cFloat: extraStack += 4; break;
850 case cDouble: extraStack += 8; break;
851 default: extraStack += 4; break;
855 if (extraStack < 0) {
858 // Round up extra stack size to the nearest doubleword.
859 extraStack = (extraStack + 7) & ~7;
863 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
865 const unsigned *OAREnd = &OutgoingArgRegs[6];
866 const unsigned *OAR = &OutgoingArgRegs[0];
867 unsigned ArgOffset = 68;
868 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKDOWN, 1).addImm (extraStack);
869 for (unsigned i = 1; i < I.getNumOperands (); ++i) {
870 unsigned ArgReg = getReg (I.getOperand (i));
871 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
872 // Schlep it over into the incoming arg register
873 if (ArgOffset < 92) {
874 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
875 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
877 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
880 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
881 if (ArgOffset < 92) {
882 // Single-fp args are passed in integer registers; go through
883 // memory to get them out of FP registers. (Bleh!)
884 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
885 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
886 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
887 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
888 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
890 BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
893 } else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
894 // Double-fp args are passed in pairs of integer registers; go through
895 // memory to get them out of FP registers. (Bleh!)
896 // We'd like to 'std' these right onto the outgoing-args area, but it might
897 // not be 8-byte aligned (e.g., call x(int x, double d)). sigh.
898 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
899 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
900 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
901 if (ArgOffset < 92 && OAR != OAREnd) {
902 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
903 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
905 unsigned TempReg = makeAnotherReg (Type::IntTy);
906 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
907 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
910 if (ArgOffset < 92 && OAR != OAREnd) {
911 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
912 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
914 unsigned TempReg = makeAnotherReg (Type::IntTy);
915 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
916 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
919 } else if (getClassB (I.getOperand (i)->getType ()) == cLong) {
920 // do the first half...
921 if (ArgOffset < 92) {
922 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
923 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
925 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
928 // ...then do the second half
929 if (ArgOffset < 92) {
930 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
931 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
933 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg+1);
937 assert (0 && "Unknown class?!");
941 // Emit call instruction
942 if (Function *F = I.getCalledFunction ()) {
943 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
944 } else { // Emit an indirect call...
945 unsigned Reg = getReg (I.getCalledValue ());
946 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
949 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKUP, 1).addImm (extraStack);
951 // Deal w/ return value: schlep it over into the destination register
952 if (I.getType () == Type::VoidTy)
954 unsigned DestReg = getReg (I);
955 switch (getClassB (I.getType ())) {
959 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
962 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
965 BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
968 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
969 BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
972 std::cerr << "Return type of call instruction not handled: " << I;
977 void V8ISel::visitReturnInst(ReturnInst &I) {
978 if (I.getNumOperands () == 1) {
979 unsigned RetValReg = getReg (I.getOperand (0));
980 switch (getClassB (I.getOperand (0)->getType ())) {
984 // Schlep it over into i0 (where it will become o0 after restore).
985 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
988 BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
991 BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
994 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
995 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
998 std::cerr << "Return instruction of this type not handled: " << I;
1003 // Just emit a 'retl' instruction to return.
1004 BuildMI(BB, V8::RETL, 0);
1008 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1009 Function::iterator I = BB; ++I; // Get iterator to next block
1010 return I != BB->getParent()->end() ? &*I : 0;
1013 /// visitBranchInst - Handles conditional and unconditional branches.
1015 void V8ISel::visitBranchInst(BranchInst &I) {
1016 BasicBlock *takenSucc = I.getSuccessor (0);
1017 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
1018 BB->addSuccessor (takenSuccMBB);
1019 if (I.isConditional()) { // conditional branch
1020 BasicBlock *notTakenSucc = I.getSuccessor (1);
1021 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
1022 BB->addSuccessor (notTakenSuccMBB);
1024 // CondReg=(<condition>);
1025 // If (CondReg==0) goto notTakenSuccMBB;
1026 unsigned CondReg = getReg (I.getCondition ());
1027 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
1028 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
1030 // goto takenSuccMBB;
1031 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
1034 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
1035 /// constant expression GEP support.
1037 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
1038 MachineBasicBlock::iterator IP,
1039 Value *Src, User::op_iterator IdxBegin,
1040 User::op_iterator IdxEnd, unsigned TargetReg) {
1041 const TargetData &TD = TM.getTargetData ();
1042 const Type *Ty = Src->getType ();
1043 unsigned basePtrReg = getReg (Src, MBB, IP);
1045 // GEPs have zero or more indices; we must perform a struct access
1046 // or array access for each one.
1047 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
1050 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
1051 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
1052 // It's a struct access. idx is the index into the structure,
1053 // which names the field. Use the TargetData structure to
1054 // pick out what the layout of the structure is in memory.
1055 // Use the (constant) structure index's value to find the
1056 // right byte offset from the StructLayout class's list of
1057 // structure member offsets.
1058 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
1059 unsigned memberOffset =
1060 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
1061 // Emit an ADD to add memberOffset to the basePtr.
1062 // We might have to copy memberOffset into a register first, if
1064 if (memberOffset + 4096 < 8191) {
1065 BuildMI (*MBB, IP, V8::ADDri, 2,
1066 nextBasePtrReg).addReg (basePtrReg).addSImm (memberOffset);
1068 unsigned offsetReg = makeAnotherReg (Type::IntTy);
1069 copyConstantToRegister (MBB, IP,
1070 ConstantSInt::get(Type::IntTy, memberOffset), offsetReg);
1071 BuildMI (*MBB, IP, V8::ADDrr, 2,
1072 nextBasePtrReg).addReg (basePtrReg).addReg (offsetReg);
1074 // The next type is the member of the structure selected by the
1076 Ty = StTy->getElementType (fieldIndex);
1077 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
1078 // It's an array or pointer access: [ArraySize x ElementType].
1079 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
1080 // must find the size of the pointed-to type (Not coincidentally, the next
1081 // type is the type of the elements in the array).
1082 Ty = SqTy->getElementType ();
1083 unsigned elementSize = TD.getTypeSize (Ty);
1084 unsigned OffsetReg = ~0U;
1085 int64_t Offset = -1;
1086 bool addImmed = false;
1087 if (isa<ConstantIntegral> (idx)) {
1088 // If idx is a constant, we don't have to emit the multiply.
1089 int64_t Val = cast<ConstantIntegral> (idx)->getRawValue ();
1090 if ((Val * elementSize) + 4096 < 8191) {
1091 // (Val * elementSize) is constant and fits in an immediate field.
1092 // emit: nextBasePtrReg = ADDri basePtrReg, (Val * elementSize)
1094 Offset = Val * elementSize;
1096 // (Val * elementSize) is constant, but doesn't fit in an immediate
1097 // field. emit: OffsetReg = (Val * elementSize)
1098 // nextBasePtrReg = ADDrr OffsetReg, basePtrReg
1099 OffsetReg = makeAnotherReg (Type::IntTy);
1100 copyConstantToRegister (MBB, IP,
1101 ConstantSInt::get(Type::IntTy, Val * elementSize), OffsetReg);
1104 // idx is not constant, we have to shift or multiply.
1105 OffsetReg = makeAnotherReg (Type::IntTy);
1106 unsigned idxReg = getReg (idx, MBB, IP);
1107 switch (elementSize) {
1109 BuildMI (*MBB, IP, V8::ORrr, 2, OffsetReg).addReg (V8::G0).addReg (idxReg);
1112 BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (1);
1115 BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (2);
1118 BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (3);
1121 if (elementSize + 4096 < 8191) {
1122 // Emit a SMUL to multiply the register holding the index by
1123 // elementSize, putting the result in OffsetReg.
1124 BuildMI (*MBB, IP, V8::SMULri, 2,
1125 OffsetReg).addReg (idxReg).addSImm (elementSize);
1127 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
1128 copyConstantToRegister (MBB, IP,
1129 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
1130 // Emit a SMUL to multiply the register holding the index by
1131 // the register w/ elementSize, putting the result in OffsetReg.
1132 BuildMI (*MBB, IP, V8::SMULrr, 2,
1133 OffsetReg).addReg (idxReg).addReg (elementSizeReg);
1140 // Emit an ADD to add the constant immediate Offset to the basePtr.
1141 BuildMI (*MBB, IP, V8::ADDri, 2,
1142 nextBasePtrReg).addReg (basePtrReg).addSImm (Offset);
1144 // Emit an ADD to add OffsetReg to the basePtr.
1145 BuildMI (*MBB, IP, V8::ADDrr, 2,
1146 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
1149 basePtrReg = nextBasePtrReg;
1151 // After we have processed all the indices, the result is left in
1152 // basePtrReg. Move it to the register where we were expected to
1154 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
1157 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
1158 unsigned outputReg = getReg (I);
1159 emitGEPOperation (BB, BB->end (), I.getOperand (0),
1160 I.op_begin ()+1, I.op_end (), outputReg);
1163 void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB,
1164 MachineBasicBlock::iterator IP,
1166 const char *FuncName,
1167 unsigned Op0Reg, unsigned Op1Reg) {
1168 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O0).addReg (V8::G0).addReg (Op0Reg);
1169 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O1).addReg (V8::G0).addReg (Op0Reg+1);
1170 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O2).addReg (V8::G0).addReg (Op1Reg);
1171 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O3).addReg (V8::G0).addReg (Op1Reg+1);
1172 BuildMI (*MBB, IP, V8::CALL, 1).addExternalSymbol (FuncName, true);
1173 BuildMI (*MBB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (V8::O0);
1174 BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1);
1177 void V8ISel::emitShift64 (MachineBasicBlock *MBB,
1178 MachineBasicBlock::iterator IP, Instruction &I,
1179 unsigned DestReg, unsigned SrcReg,
1180 unsigned ShiftAmtReg) {
1181 bool isSigned = I.getType()->isSigned();
1183 switch (I.getOpcode ()) {
1184 case Instruction::Shr: {
1185 unsigned CarryReg = makeAnotherReg (Type::IntTy),
1186 ThirtyTwo = makeAnotherReg (Type::IntTy),
1187 HalfShiftReg = makeAnotherReg (Type::IntTy),
1188 NegHalfShiftReg = makeAnotherReg (Type::IntTy),
1189 TempReg = makeAnotherReg (Type::IntTy);
1190 unsigned OneShiftOutReg = makeAnotherReg (Type::ULongTy),
1191 TwoShiftsOutReg = makeAnotherReg (Type::ULongTy);
1193 MachineBasicBlock *thisMBB = BB;
1194 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1195 MachineBasicBlock *shiftMBB = new MachineBasicBlock (LLVM_BB);
1196 F->getBasicBlockList ().push_back (shiftMBB);
1197 MachineBasicBlock *oneShiftMBB = new MachineBasicBlock (LLVM_BB);
1198 F->getBasicBlockList ().push_back (oneShiftMBB);
1199 MachineBasicBlock *twoShiftsMBB = new MachineBasicBlock (LLVM_BB);
1200 F->getBasicBlockList ().push_back (twoShiftsMBB);
1201 MachineBasicBlock *continueMBB = new MachineBasicBlock (LLVM_BB);
1202 F->getBasicBlockList ().push_back (continueMBB);
1206 // subcc %g0, ShiftAmtReg, %g0 ! Is ShAmt == 0?
1207 // be .lshr_continue ! Then don't shift.
1208 // ba .lshr_shift ! else shift.
1210 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (V8::G0)
1211 .addReg (ShiftAmtReg);
1212 BuildMI (BB, V8::BE, 1).addMBB (continueMBB);
1213 BuildMI (BB, V8::BA, 1).addMBB (shiftMBB);
1215 // Update machine-CFG edges
1216 BB->addSuccessor (continueMBB);
1217 BB->addSuccessor (shiftMBB);
1219 // .lshr_shift: ! [preds: begin]
1220 // or %g0, 32, ThirtyTwo
1221 // subcc ThirtyTwo, ShiftAmtReg, HalfShiftReg ! Calculate 32 - shamt
1222 // bg .lshr_two_shifts ! If >0, b two_shifts
1223 // ba .lshr_one_shift ! else one_shift.
1227 BuildMI (BB, V8::ORri, 2, ThirtyTwo).addReg (V8::G0).addSImm (32);
1228 BuildMI (BB, V8::SUBCCrr, 2, HalfShiftReg).addReg (ThirtyTwo)
1229 .addReg (ShiftAmtReg);
1230 BuildMI (BB, V8::BG, 1).addMBB (twoShiftsMBB);
1231 BuildMI (BB, V8::BA, 1).addMBB (oneShiftMBB);
1233 // Update machine-CFG edges
1234 BB->addSuccessor (twoShiftsMBB);
1235 BB->addSuccessor (oneShiftMBB);
1237 // .lshr_two_shifts: ! [preds: shift]
1238 // sll SrcReg, HalfShiftReg, CarryReg ! Save the borrows
1239 // ! <SHIFT> in following is sra if signed, srl if unsigned
1240 // <SHIFT> SrcReg, ShiftAmtReg, TwoShiftsOutReg ! Shift top half
1241 // srl SrcReg+1, ShiftAmtReg, TempReg ! Shift bottom half
1242 // or TempReg, CarryReg, TwoShiftsOutReg+1 ! Restore the borrows
1243 // ba .lshr_continue
1244 unsigned ShiftOpcode = (isSigned ? V8::SRArr : V8::SRLrr);
1248 BuildMI (BB, V8::SLLrr, 2, CarryReg).addReg (SrcReg)
1249 .addReg (HalfShiftReg);
1250 BuildMI (BB, ShiftOpcode, 2, TwoShiftsOutReg).addReg (SrcReg)
1251 .addReg (ShiftAmtReg);
1252 BuildMI (BB, V8::SRLrr, 2, TempReg).addReg (SrcReg+1)
1253 .addReg (ShiftAmtReg);
1254 BuildMI (BB, V8::ORrr, 2, TwoShiftsOutReg+1).addReg (TempReg)
1256 BuildMI (BB, V8::BA, 1).addMBB (continueMBB);
1258 // Update machine-CFG edges
1259 BB->addSuccessor (continueMBB);
1261 // .lshr_one_shift: ! [preds: shift]
1263 // or %g0, %g0, OneShiftOutReg ! Zero top half
1265 // sra SrcReg, 31, OneShiftOutReg ! Sign-ext top half
1266 // sub %g0, HalfShiftReg, NegHalfShiftReg ! Make ShiftAmt >0
1267 // <SHIFT> SrcReg, NegHalfShiftReg, OneShiftOutReg+1 ! Shift bottom half
1268 // ba .lshr_continue
1273 BuildMI (BB, V8::SRAri, 2, OneShiftOutReg).addReg (SrcReg).addZImm (31);
1275 BuildMI (BB, V8::ORrr, 2, OneShiftOutReg).addReg (V8::G0)
1277 BuildMI (BB, V8::SUBrr, 2, NegHalfShiftReg).addReg (V8::G0)
1278 .addReg (HalfShiftReg);
1279 BuildMI (BB, ShiftOpcode, 2, OneShiftOutReg+1).addReg (SrcReg)
1280 .addReg (NegHalfShiftReg);
1281 BuildMI (BB, V8::BA, 1).addMBB (continueMBB);
1283 // Update machine-CFG edges
1284 BB->addSuccessor (continueMBB);
1286 // .lshr_continue: ! [preds: begin, do_one_shift, do_two_shifts]
1287 // phi (SrcReg, begin), (TwoShiftsOutReg, two_shifts),
1288 // (OneShiftOutReg, one_shift), DestReg ! Phi top half...
1289 // phi (SrcReg+1, begin), (TwoShiftsOutReg+1, two_shifts),
1290 // (OneShiftOutReg+1, one_shift), DestReg+1 ! And phi bottom half.
1293 BuildMI (BB, V8::PHI, 6, DestReg).addReg (SrcReg).addMBB (thisMBB)
1294 .addReg (TwoShiftsOutReg).addMBB (twoShiftsMBB)
1295 .addReg (OneShiftOutReg).addMBB (oneShiftMBB);
1296 BuildMI (BB, V8::PHI, 6, DestReg+1).addReg (SrcReg+1).addMBB (thisMBB)
1297 .addReg (TwoShiftsOutReg+1).addMBB (twoShiftsMBB)
1298 .addReg (OneShiftOutReg+1).addMBB (oneShiftMBB);
1301 case Instruction::Shl:
1303 std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I;
1308 void V8ISel::visitBinaryOperator (Instruction &I) {
1309 unsigned DestReg = getReg (I);
1310 unsigned Op0Reg = getReg (I.getOperand (0));
1312 unsigned Class = getClassB (I.getType());
1313 unsigned OpCase = ~0;
1315 if (Class > cLong) {
1316 unsigned Op1Reg = getReg (I.getOperand (1));
1317 switch (I.getOpcode ()) {
1318 case Instruction::Add: OpCase = 0; break;
1319 case Instruction::Sub: OpCase = 1; break;
1320 case Instruction::Mul: OpCase = 2; break;
1321 case Instruction::Div: OpCase = 3; break;
1322 default: visitInstruction (I); return;
1324 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
1325 V8::FSUBS, V8::FSUBD,
1326 V8::FMULS, V8::FMULD,
1327 V8::FDIVS, V8::FDIVD };
1328 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
1329 .addReg (Op0Reg).addReg (Op1Reg);
1333 unsigned ResultReg = DestReg;
1334 if (Class != cInt && Class != cLong)
1335 ResultReg = makeAnotherReg (I.getType ());
1337 if (Class == cLong) {
1338 const char *FuncName;
1339 unsigned Op1Reg = getReg (I.getOperand (1));
1340 DEBUG (std::cerr << "Class = cLong\n");
1341 DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
1342 DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
1343 DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
1344 DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
1345 switch (I.getOpcode ()) {
1346 case Instruction::Add:
1347 BuildMI (BB, V8::ADDCCrr, 2, ResultReg+1).addReg (Op0Reg+1)
1349 BuildMI (BB, V8::ADDXrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1351 case Instruction::Sub:
1352 BuildMI (BB, V8::SUBCCrr, 2, ResultReg+1).addReg (Op0Reg+1)
1354 BuildMI (BB, V8::SUBXrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1356 case Instruction::Mul:
1357 FuncName = I.getType ()->isSigned () ? "__mul64" : "__umul64";
1358 emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
1360 case Instruction::Div:
1361 FuncName = I.getType ()->isSigned () ? "__div64" : "__udiv64";
1362 emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
1364 case Instruction::Rem:
1365 FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64";
1366 emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
1368 case Instruction::Shl:
1369 case Instruction::Shr:
1370 emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg);
1375 switch (I.getOpcode ()) {
1376 case Instruction::Add: OpCase = 0; break;
1377 case Instruction::Sub: OpCase = 1; break;
1378 case Instruction::Mul: OpCase = 2; break;
1379 case Instruction::And: OpCase = 3; break;
1380 case Instruction::Or: OpCase = 4; break;
1381 case Instruction::Xor: OpCase = 5; break;
1382 case Instruction::Shl: OpCase = 6; break;
1383 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
1385 case Instruction::Div:
1386 case Instruction::Rem: {
1387 unsigned Dest = ResultReg;
1388 unsigned Op1Reg = getReg (I.getOperand (1));
1389 if (I.getOpcode() == Instruction::Rem)
1390 Dest = makeAnotherReg(I.getType());
1392 // FIXME: this is probably only right for 32 bit operands.
1393 if (I.getType ()->isSigned()) {
1394 unsigned Tmp = makeAnotherReg (I.getType ());
1395 // Sign extend into the Y register
1396 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
1397 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
1398 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1400 // Zero extend into the Y register, ie, just set it to zero
1401 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
1402 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1405 if (I.getOpcode() == Instruction::Rem) {
1406 unsigned Tmp = makeAnotherReg (I.getType ());
1407 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
1408 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
1413 visitInstruction (I);
1417 static const unsigned Opcodes[] = {
1418 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
1419 V8::SLLrr, V8::SRLrr, V8::SRArr
1421 static const unsigned OpcodesRI[] = {
1422 V8::ADDri, V8::SUBri, V8::SMULri, V8::ANDri, V8::ORri, V8::XORri,
1423 V8::SLLri, V8::SRLri, V8::SRAri
1425 unsigned Op1Reg = ~0U;
1426 if (OpCase != ~0U) {
1427 Value *Arg1 = I.getOperand (1);
1428 bool useImmed = false;
1430 if ((getClassB (I.getType ()) <= cInt) && (isa<ConstantIntegral> (Arg1))) {
1431 Val = cast<ConstantIntegral> (Arg1)->getRawValue ();
1432 useImmed = (Val > -4096 && Val < 4095);
1435 BuildMI (BB, OpcodesRI[OpCase], 2, ResultReg).addReg (Op0Reg).addSImm (Val);
1437 Op1Reg = getReg (I.getOperand (1));
1438 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1442 switch (getClassB (I.getType ())) {
1444 if (I.getType ()->isSigned ()) { // add byte
1445 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
1446 } else { // add ubyte
1447 unsigned TmpReg = makeAnotherReg (I.getType ());
1448 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
1449 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
1453 if (I.getType ()->isSigned ()) { // add short
1454 unsigned TmpReg = makeAnotherReg (I.getType ());
1455 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1456 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
1457 } else { // add ushort
1458 unsigned TmpReg = makeAnotherReg (I.getType ());
1459 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1460 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
1464 // Nothing to do here.
1467 // Only support and, or, xor here - others taken care of above.
1468 if (OpCase < 3 || OpCase > 5) {
1469 visitInstruction (I);
1472 // Do the other half of the value:
1473 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
1478 visitInstruction (I);
1482 void V8ISel::visitSetCondInst(SetCondInst &I) {
1483 unsigned Op0Reg = getReg (I.getOperand (0));
1484 unsigned Op1Reg = getReg (I.getOperand (1));
1485 unsigned DestReg = getReg (I);
1486 const Type *Ty = I.getOperand (0)->getType ();
1488 // Compare the two values.
1489 if (getClass (Ty) < cLong) {
1490 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1491 } else if (getClass (Ty) == cLong) {
1492 switch (I.getOpcode()) {
1493 default: assert(0 && "Unknown setcc instruction!");
1494 case Instruction::SetEQ:
1495 case Instruction::SetNE: {
1496 unsigned TempReg0 = makeAnotherReg (Type::IntTy),
1497 TempReg1 = makeAnotherReg (Type::IntTy),
1498 TempReg2 = makeAnotherReg (Type::IntTy),
1499 TempReg3 = makeAnotherReg (Type::IntTy);
1500 MachineOpCode Opcode;
1502 // These guys are special - no branches needed!
1503 BuildMI (BB, V8::XORrr, 2, TempReg0).addReg (Op0Reg+1).addReg (Op1Reg+1);
1504 BuildMI (BB, V8::XORrr, 2, TempReg1).addReg (Op0Reg).addReg (Op1Reg);
1505 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (V8::G0).addReg (TempReg1);
1506 Opcode = I.getOpcode() == Instruction::SetEQ ? V8::SUBXri : V8::ADDXri;
1507 Immed = I.getOpcode() == Instruction::SetEQ ? -1 : 0;
1508 BuildMI (BB, Opcode, 2, TempReg2).addReg (V8::G0).addSImm (Immed);
1509 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (V8::G0).addReg (TempReg0);
1510 BuildMI (BB, Opcode, 2, TempReg3).addReg (V8::G0).addSImm (Immed);
1511 Opcode = I.getOpcode() == Instruction::SetEQ ? V8::ANDrr : V8::ORrr;
1512 BuildMI (BB, Opcode, 2, DestReg).addReg (TempReg2).addReg (TempReg3);
1515 case Instruction::SetLT:
1516 case Instruction::SetGE:
1517 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (Op0Reg+1).addReg (Op1Reg+1);
1518 BuildMI (BB, V8::SUBXCCrr, 2, V8::G0).addReg (Op0Reg).addReg (Op1Reg);
1520 case Instruction::SetGT:
1521 case Instruction::SetLE:
1522 BuildMI (BB, V8::SUBCCri, 2, V8::G0).addReg (V8::G0).addSImm (1);
1523 BuildMI (BB, V8::SUBXCCrr, 2, V8::G0).addReg (Op0Reg+1).addReg (Op1Reg+1);
1524 BuildMI (BB, V8::SUBXCCrr, 2, V8::G0).addReg (Op0Reg).addReg (Op1Reg);
1527 } else if (getClass (Ty) == cFloat) {
1528 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1529 } else if (getClass (Ty) == cDouble) {
1530 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1534 switch (I.getOpcode()) {
1535 default: assert(0 && "Unknown setcc instruction!");
1536 case Instruction::SetEQ: BranchIdx = 0; break;
1537 case Instruction::SetNE: BranchIdx = 1; break;
1538 case Instruction::SetLT: BranchIdx = 2; break;
1539 case Instruction::SetGT: BranchIdx = 3; break;
1540 case Instruction::SetLE: BranchIdx = 4; break;
1541 case Instruction::SetGE: BranchIdx = 5; break;
1544 unsigned Column = 0;
1545 if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
1546 if (Ty->isFloatingPoint()) Column = 2;
1547 static unsigned OpcodeTab[3*6] = {
1549 // unsigned signed fp
1550 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1551 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1552 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1553 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1554 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1555 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1557 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1559 MachineBasicBlock *thisMBB = BB;
1560 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1563 // subcc %reg0, %reg1, %g0
1567 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1568 // if we could insert other, non-terminator instructions after the
1569 // bCC. But MBB->getFirstTerminator() can't understand this.
1570 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
1571 F->getBasicBlockList ().push_back (copy1MBB);
1572 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
1573 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1574 F->getBasicBlockList ().push_back (copy0MBB);
1575 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
1576 // Update machine-CFG edges
1577 BB->addSuccessor (copy1MBB);
1578 BB->addSuccessor (copy0MBB);
1581 // %FalseValue = or %G0, 0
1584 unsigned FalseValue = makeAnotherReg (I.getType ());
1585 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
1586 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1587 F->getBasicBlockList ().push_back (sinkMBB);
1588 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1589 // Update machine-CFG edges
1590 BB->addSuccessor (sinkMBB);
1592 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1593 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
1594 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1595 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1598 // %TrueValue = or %G0, 1
1601 unsigned TrueValue = makeAnotherReg (I.getType ());
1602 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1603 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1604 // Update machine-CFG edges
1605 BB->addSuccessor (sinkMBB);
1608 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1611 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1612 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1615 void V8ISel::visitAllocaInst(AllocaInst &I) {
1616 // Find the data size of the alloca inst's getAllocatedType.
1617 const Type *Ty = I.getAllocatedType();
1618 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1620 unsigned ArraySizeReg = getReg (I.getArraySize ());
1621 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1622 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1623 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1624 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1626 // StackAdjReg = (ArraySize * TySize) rounded up to nearest
1627 // doubleword boundary.
1628 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1630 // Round up TmpReg1 to nearest doubleword boundary:
1631 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1632 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1634 // Subtract size from stack pointer, thereby allocating some space.
1635 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1637 // Put a pointer to the space into the result register, by copying
1638 // the stack pointer.
1639 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1641 // Inform the Frame Information that we have just allocated a variable-sized
1643 F->getFrameInfo()->CreateVariableSizedObject();
1646 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1647 /// function, lowering any calls to unknown intrinsic functions into the
1648 /// equivalent LLVM code.
1649 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1650 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1651 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1652 if (CallInst *CI = dyn_cast<CallInst>(I++))
1653 if (Function *F = CI->getCalledFunction())
1654 switch (F->getIntrinsicID()) {
1655 case Intrinsic::vastart:
1656 case Intrinsic::vacopy:
1657 case Intrinsic::vaend:
1658 // We directly implement these intrinsics
1659 case Intrinsic::not_intrinsic: break;
1661 // All other intrinsic calls we must lower.
1662 Instruction *Before = CI->getPrev();
1663 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1664 if (Before) { // Move iterator to instruction after call
1673 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1676 std::cerr << "Sorry, unknown intrinsic function call:\n" << CI; abort ();
1678 case Intrinsic::vastart: {
1679 // Add the VarArgsOffset to the frame pointer, and copy it to the result.
1680 unsigned DestReg = getReg (CI);
1681 BuildMI (BB, V8::ADDri, 2, DestReg).addReg (V8::FP).addSImm (VarArgsOffset);
1685 case Intrinsic::vaend:
1686 // va_end is a no-op on SparcV8.
1689 case Intrinsic::vacopy: {
1690 // Copy the va_list ptr (arg1) to the result.
1691 unsigned DestReg = getReg (CI), SrcReg = getReg (CI.getOperand (1));
1692 BuildMI (BB, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
1698 void V8ISel::visitVANextInst (VANextInst &I) {
1699 // Add the type size to the vararg pointer (arg0).
1700 unsigned DestReg = getReg (I);
1701 unsigned SrcReg = getReg (I.getOperand (0));
1702 unsigned TySize = TM.getTargetData ().getTypeSize (I.getArgType ());
1703 BuildMI (BB, V8::ADDri, 2, DestReg).addReg (SrcReg).addSImm (TySize);
1706 void V8ISel::visitVAArgInst (VAArgInst &I) {
1707 unsigned VAList = getReg (I.getOperand (0));
1708 unsigned DestReg = getReg (I);
1710 switch (I.getType ()->getTypeID ()) {
1711 case Type::PointerTyID:
1712 case Type::UIntTyID:
1714 BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
1717 case Type::ULongTyID:
1718 case Type::LongTyID:
1719 BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
1720 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
1723 case Type::DoubleTyID: {
1724 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
1725 unsigned TempReg = makeAnotherReg (Type::IntTy);
1726 unsigned TempReg2 = makeAnotherReg (Type::IntTy);
1727 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
1728 BuildMI (BB, V8::LD, 2, TempReg).addReg (VAList).addSImm (0);
1729 BuildMI (BB, V8::LD, 2, TempReg2).addReg (VAList).addSImm (4);
1730 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
1731 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
1732 BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
1737 std::cerr << "Sorry, vaarg instruction of this type still unsupported:\n"