1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
33 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
35 MachineFunction *F; // The function we are compiling into
36 MachineBasicBlock *BB; // The current MBB we are compiling
37 int VarArgsOffset; // Offset from fp for start of varargs area
39 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
41 // MBBMap - Mapping between LLVM BB -> Machine BB
42 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
44 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
46 /// runOnFunction - Top level implementation of instruction selection for
47 /// the entire function.
49 bool runOnFunction(Function &Fn);
51 virtual const char *getPassName() const {
52 return "SparcV8 Simple Instruction Selection";
55 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
56 /// constant expression GEP support.
58 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
59 Value *Src, User::op_iterator IdxBegin,
60 User::op_iterator IdxEnd, unsigned TargetReg);
62 /// emitCastOperation - Common code shared between visitCastInst and
63 /// constant expression cast support.
65 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
66 Value *Src, const Type *DestTy, unsigned TargetReg);
68 /// emitIntegerCast, emitFPToIntegerCast - Helper methods for
69 /// emitCastOperation.
71 unsigned emitIntegerCast (MachineBasicBlock *BB,
72 MachineBasicBlock::iterator IP,
73 const Type *oldTy, unsigned SrcReg,
74 const Type *newTy, unsigned DestReg);
75 void emitFPToIntegerCast (MachineBasicBlock *BB,
76 MachineBasicBlock::iterator IP, const Type *oldTy,
77 unsigned SrcReg, const Type *newTy,
80 /// visitBasicBlock - This method is called when we are visiting a new basic
81 /// block. This simply creates a new MachineBasicBlock to emit code into
82 /// and adds it to the current MachineFunction. Subsequent visit* for
83 /// instructions will be invoked for all instructions in the basic block.
85 void visitBasicBlock(BasicBlock &LLVM_BB) {
86 BB = MBBMap[&LLVM_BB];
89 void visitBinaryOperator(Instruction &I);
90 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
91 void visitSetCondInst(SetCondInst &I);
92 void visitCallInst(CallInst &I);
93 void visitReturnInst(ReturnInst &I);
94 void visitBranchInst(BranchInst &I);
95 void visitUnreachableInst(UnreachableInst &I) {}
96 void visitCastInst(CastInst &I);
97 void visitVANextInst(VANextInst &I);
98 void visitVAArgInst(VAArgInst &I);
99 void visitLoadInst(LoadInst &I);
100 void visitStoreInst(StoreInst &I);
101 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
102 void visitGetElementPtrInst(GetElementPtrInst &I);
103 void visitAllocaInst(AllocaInst &I);
105 void visitInstruction(Instruction &I) {
106 std::cerr << "Unhandled instruction: " << I;
110 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
111 /// function, lowering any calls to unknown intrinsic functions into the
112 /// equivalent LLVM code.
113 void LowerUnknownIntrinsicFunctionCalls(Function &F);
114 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
116 void LoadArgumentsToVirtualRegs(Function *F);
118 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
119 /// because we have to generate our sources into the source basic blocks,
120 /// not the current one.
122 void SelectPHINodes();
124 /// copyConstantToRegister - Output the instructions required to put the
125 /// specified constant into the specified register.
127 void copyConstantToRegister(MachineBasicBlock *MBB,
128 MachineBasicBlock::iterator IP,
129 Constant *C, unsigned R);
131 /// makeAnotherReg - This method returns the next register number we haven't
134 /// Long values are handled somewhat specially. They are always allocated
135 /// as pairs of 32 bit integer values. The register number returned is the
136 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
137 /// of the long value.
139 unsigned makeAnotherReg(const Type *Ty) {
140 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
141 "Current target doesn't have SparcV8 reg info??");
142 const SparcV8RegisterInfo *MRI =
143 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
144 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
145 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
146 // Create the lower part
147 F->getSSARegMap()->createVirtualRegister(RC);
148 // Create the upper part.
149 return F->getSSARegMap()->createVirtualRegister(RC)-1;
152 // Add the mapping of regnumber => reg class to MachineFunction
153 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
154 return F->getSSARegMap()->createVirtualRegister(RC);
157 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
158 unsigned getReg(Value *V) {
159 // Just append to the end of the current bb.
160 MachineBasicBlock::iterator It = BB->end();
161 return getReg(V, BB, It);
163 unsigned getReg(Value *V, MachineBasicBlock *MBB,
164 MachineBasicBlock::iterator IPt) {
165 unsigned &Reg = RegMap[V];
167 Reg = makeAnotherReg(V->getType());
170 // If this operand is a constant, emit the code to copy the constant into
171 // the register here...
173 if (Constant *C = dyn_cast<Constant>(V)) {
174 copyConstantToRegister(MBB, IPt, C, Reg);
175 RegMap.erase(V); // Assign a new name to this constant if ref'd again
176 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
177 // Move the address of the global into the register
178 unsigned TmpReg = makeAnotherReg(V->getType());
179 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
180 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
181 .addGlobalAddress (GV);
182 RegMap.erase(V); // Assign a new name to this address if ref'd again
191 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
192 return new V8ISel(TM);
196 cByte, cShort, cInt, cLong, cFloat, cDouble
199 static TypeClass getClass (const Type *T) {
200 switch (T->getTypeID()) {
201 case Type::UByteTyID: case Type::SByteTyID: return cByte;
202 case Type::UShortTyID: case Type::ShortTyID: return cShort;
203 case Type::PointerTyID:
204 case Type::UIntTyID: case Type::IntTyID: return cInt;
205 case Type::ULongTyID: case Type::LongTyID: return cLong;
206 case Type::FloatTyID: return cFloat;
207 case Type::DoubleTyID: return cDouble;
209 assert (0 && "Type of unknown class passed to getClass?");
214 static TypeClass getClassB(const Type *T) {
215 if (T == Type::BoolTy) return cByte;
219 /// copyConstantToRegister - Output the instructions required to put the
220 /// specified constant into the specified register.
222 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
223 MachineBasicBlock::iterator IP,
224 Constant *C, unsigned R) {
225 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
226 switch (CE->getOpcode()) {
227 case Instruction::GetElementPtr:
228 emitGEPOperation(MBB, IP, CE->getOperand(0),
229 CE->op_begin()+1, CE->op_end(), R);
231 case Instruction::Cast:
232 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
235 std::cerr << "Copying this constant expr not yet handled: " << *CE;
238 } else if (isa<UndefValue>(C)) {
239 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
240 if (getClassB (C->getType ()) == cLong)
241 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
245 if (C->getType()->isIntegral ()) {
247 unsigned Class = getClassB (C->getType ());
248 if (Class == cLong) {
249 unsigned TmpReg = makeAnotherReg (Type::IntTy);
250 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
251 // Copy the value into the register pair.
252 // R = top(more-significant) half, R+1 = bottom(less-significant) half
253 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
254 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
256 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
257 Val & 0xffffffffU), R+1);
261 assert(Class <= cInt && "Type not handled yet!");
263 if (C->getType() == Type::BoolTy) {
264 Val = (C == ConstantBool::True);
266 ConstantInt *CI = cast<ConstantInt> (C);
267 Val = CI->getRawValue ();
270 case cByte: Val = (int8_t) Val; break;
271 case cShort: Val = (int16_t) Val; break;
272 case cInt: Val = (int32_t) Val; break;
274 std::cerr << "Offending constant: " << *C << "\n";
275 assert (0 && "Can't copy this kind of constant into register yet");
279 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
280 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
281 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
283 unsigned TmpReg = makeAnotherReg (C->getType ());
284 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
285 .addSImm (((uint32_t) Val) >> 10);
286 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
287 .addSImm (((uint32_t) Val) & 0x03ff);
290 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
291 // We need to spill the constant to memory...
292 MachineConstantPool *CP = F->getConstantPool();
293 unsigned CPI = CP->getConstantPoolIndex(CFP);
294 const Type *Ty = CFP->getType();
295 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
296 unsigned AddrReg = makeAnotherReg (Type::UIntTy);
298 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
299 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
300 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
301 BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
302 .addConstantPoolIndex (CPI);
303 BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
304 } else if (isa<ConstantPointerNull>(C)) {
305 // Copy zero (null pointer) to the register.
306 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
307 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
308 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
309 // that SETHI %reg,global == SETHI %reg,%hi(global) and
310 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
311 unsigned TmpReg = makeAnotherReg (C->getType ());
312 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
313 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
315 std::cerr << "Offending constant: " << *C << "\n";
316 assert (0 && "Can't copy this kind of constant into register yet");
320 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
321 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
322 V8::I3, V8::I4, V8::I5 };
324 // Add IMPLICIT_DEFs of input regs.
326 for (Function::aiterator I = LF->abegin(), E = LF->aend();
327 I != E && ArgNo < 6; ++I, ++ArgNo) {
328 switch (getClassB(I->getType())) {
333 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
337 // Double and Long use register pairs.
338 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
341 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
344 assert (0 && "type not handled");
349 const unsigned *IAREnd = &IncomingArgRegs[6];
350 const unsigned *IAR = &IncomingArgRegs[0];
351 unsigned ArgOffset = 68;
353 // Store registers onto stack if this is a varargs function.
354 // FIXME: This doesn't really pertain to "loading arguments into
355 // virtual registers", so it's not clear that it really belongs here.
356 // FIXME: We could avoid storing any args onto the stack that don't
357 // need to be in memory, because they come before the ellipsis in the
358 // parameter list (and thus could never be accessed through va_arg).
359 if (LF->getFunctionType ()->isVarArg ()) {
360 for (unsigned i = 0; i < 6; ++i) {
361 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
362 assert (IAR != IAREnd
363 && "About to dereference past end of IncomingArgRegs");
364 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
367 // Reset the pointers now that we're done.
369 IAR = &IncomingArgRegs[0];
372 // Copy args out of their incoming hard regs or stack slots into virtual regs.
373 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
375 unsigned ArgReg = getReg (A);
376 if (getClassB (A.getType ()) < cLong) {
377 // Get it out of the incoming arg register
378 if (ArgOffset < 92) {
379 assert (IAR != IAREnd
380 && "About to dereference past end of IncomingArgRegs");
381 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
383 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
384 BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
387 } else if (getClassB (A.getType ()) == cFloat) {
388 if (ArgOffset < 92) {
389 // Single-fp args are passed in integer registers; go through
390 // memory to get them out of integer registers and back into fp. (Bleh!)
391 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
392 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
393 assert (IAR != IAREnd
394 && "About to dereference past end of IncomingArgRegs");
395 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
396 BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
398 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
399 BuildMI (BB, V8::LDFri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
402 } else if (getClassB (A.getType ()) == cDouble) {
403 // Double-fp args are passed in pairs of integer registers; go through
404 // memory to get them out of integer registers and back into fp. (Bleh!)
405 // We'd like to 'ldd' these right out of the incoming-args area,
406 // but it might not be 8-byte aligned (e.g., call x(int x, double d)).
407 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
408 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
409 if (ArgOffset < 92 && IAR != IAREnd) {
410 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
412 unsigned TempReg = makeAnotherReg (Type::IntTy);
413 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
414 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
417 if (ArgOffset < 92 && IAR != IAREnd) {
418 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
420 unsigned TempReg = makeAnotherReg (Type::IntTy);
421 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
422 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
425 BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
426 } else if (getClassB (A.getType ()) == cLong) {
427 // do the first half...
428 if (ArgOffset < 92) {
429 assert (IAR != IAREnd
430 && "About to dereference past end of IncomingArgRegs");
431 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
433 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
434 BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
437 // ...then do the second half
438 if (ArgOffset < 92) {
439 assert (IAR != IAREnd
440 && "About to dereference past end of IncomingArgRegs");
441 BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
443 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
444 BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
448 assert (0 && "Unknown class?!");
452 // If the function takes variable number of arguments, remember the fp
453 // offset for the start of the first vararg value... this is used to expand
455 if (LF->getFunctionType ()->isVarArg ())
456 VarArgsOffset = ArgOffset;
459 void V8ISel::SelectPHINodes() {
460 const TargetInstrInfo &TII = *TM.getInstrInfo();
461 const Function &LF = *F->getFunction(); // The LLVM function...
462 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
463 const BasicBlock *BB = I;
464 MachineBasicBlock &MBB = *MBBMap[I];
466 // Loop over all of the PHI nodes in the LLVM basic block...
467 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
468 for (BasicBlock::const_iterator I = BB->begin();
469 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
471 // Create a new machine instr PHI node, and insert it.
472 unsigned PHIReg = getReg(*PN);
473 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
474 V8::PHI, PN->getNumOperands(), PHIReg);
476 MachineInstr *LongPhiMI = 0;
477 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
478 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
479 V8::PHI, PN->getNumOperands(), PHIReg+1);
481 // PHIValues - Map of blocks to incoming virtual registers. We use this
482 // so that we only initialize one incoming value for a particular block,
483 // even if the block has multiple entries in the PHI node.
485 std::map<MachineBasicBlock*, unsigned> PHIValues;
487 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
488 MachineBasicBlock *PredMBB = 0;
489 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
490 PE = MBB.pred_end (); PI != PE; ++PI)
491 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
495 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
498 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
499 PHIValues.lower_bound(PredMBB);
501 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
502 // We already inserted an initialization of the register for this
503 // predecessor. Recycle it.
504 ValReg = EntryIt->second;
507 // Get the incoming value into a virtual register.
509 Value *Val = PN->getIncomingValue(i);
511 // If this is a constant or GlobalValue, we may have to insert code
512 // into the basic block to compute it into a virtual register.
513 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
514 isa<GlobalValue>(Val)) {
515 // Simple constants get emitted at the end of the basic block,
516 // before any terminator instructions. We "know" that the code to
517 // move a constant into a register will never clobber any flags.
518 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
520 // Because we don't want to clobber any values which might be in
521 // physical registers with the computation of this constant (which
522 // might be arbitrarily complex if it is a constant expression),
523 // just insert the computation at the top of the basic block.
524 MachineBasicBlock::iterator PI = PredMBB->begin();
526 // Skip over any PHI nodes though!
527 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
530 ValReg = getReg(Val, PredMBB, PI);
533 // Remember that we inserted a value for this PHI for this predecessor
534 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
537 PhiMI->addRegOperand(ValReg);
538 PhiMI->addMachineBasicBlockOperand(PredMBB);
540 LongPhiMI->addRegOperand(ValReg+1);
541 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
545 // Now that we emitted all of the incoming values for the PHI node, make
546 // sure to reposition the InsertPoint after the PHI that we just added.
547 // This is needed because we might have inserted a constant into this
548 // block, right after the PHI's which is before the old insert point!
549 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
555 bool V8ISel::runOnFunction(Function &Fn) {
556 // First pass over the function, lower any unknown intrinsic functions
557 // with the IntrinsicLowering class.
558 LowerUnknownIntrinsicFunctionCalls(Fn);
560 F = &MachineFunction::construct(&Fn, TM);
562 // Create all of the machine basic blocks for the function...
563 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
564 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
568 // Set up a frame object for the return address. This is used by the
569 // llvm.returnaddress & llvm.frameaddress intrinisics.
570 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
572 // Copy incoming arguments off of the stack and out of fixed registers.
573 LoadArgumentsToVirtualRegs(&Fn);
575 // Instruction select everything except PHI nodes
578 // Select the PHI nodes
584 // We always build a machine code representation for the function
588 void V8ISel::visitCastInst(CastInst &I) {
589 Value *Op = I.getOperand(0);
590 unsigned DestReg = getReg(I);
591 MachineBasicBlock::iterator MI = BB->end();
592 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
595 unsigned V8ISel::emitIntegerCast (MachineBasicBlock *BB,
596 MachineBasicBlock::iterator IP, const Type *oldTy,
597 unsigned SrcReg, const Type *newTy,
599 if (oldTy == newTy) {
600 // No-op cast - just emit a copy; assume the reg. allocator will zap it.
601 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg(SrcReg);
604 // Emit left-shift, then right-shift to sign- or zero-extend.
605 unsigned TmpReg = makeAnotherReg (newTy);
606 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
607 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg).addZImm (shiftWidth).addReg(SrcReg);
608 if (newTy->isSigned ()) { // sign-extend with SRA
609 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
610 } else { // zero-extend with SRL
611 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
613 // Return the temp reg. in case this is one half of a cast to long.
617 void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
618 MachineBasicBlock::iterator IP,
619 const Type *oldTy, unsigned SrcReg,
620 const Type *newTy, unsigned DestReg) {
621 unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
622 unsigned oldTyClass = getClassB(oldTy);
623 if (oldTyClass == cFloat) {
624 FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
625 FPAlign = TM.getTargetData().getFloatAlignment();
626 } else { // it's a double
627 FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
628 FPAlign = TM.getTargetData().getDoubleAlignment();
630 unsigned TempReg = makeAnotherReg (oldTy);
631 BuildMI (*BB, IP, FPCastOpcode, 1, TempReg).addReg (SrcReg);
632 int FI = F->getFrameInfo()->CreateStackObject(FPSize, FPAlign);
633 BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
635 unsigned TempReg2 = makeAnotherReg (newTy);
636 BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
637 emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
640 /// emitCastOperation - Common code shared between visitCastInst and constant
641 /// expression cast support.
643 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
644 MachineBasicBlock::iterator IP, Value *Src,
645 const Type *DestTy, unsigned DestReg) {
646 const Type *SrcTy = Src->getType();
647 unsigned SrcClass = getClassB(SrcTy);
648 unsigned DestClass = getClassB(DestTy);
649 unsigned SrcReg = getReg(Src, BB, IP);
651 const Type *oldTy = SrcTy;
652 const Type *newTy = DestTy;
653 unsigned oldTyClass = SrcClass;
654 unsigned newTyClass = DestClass;
656 if (oldTyClass < cLong && newTyClass < cLong) {
657 emitIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
658 } else switch (newTyClass) {
662 switch (oldTyClass) {
664 // Treat it like a cast from the lower half of the value.
665 emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
669 emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
671 default: goto not_yet;
676 switch (oldTyClass) {
677 case cLong: goto not_yet;
679 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
682 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
685 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
686 // cast integer type to float. Store it to a stack slot and then load
687 // it using ldf into a floating point register. then do fitos.
688 unsigned TmpReg = makeAnotherReg (newTy);
689 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
690 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
692 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
693 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
700 switch (oldTyClass) {
701 case cLong: goto not_yet;
703 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
705 case cDouble: // use double move pseudo-instr
706 BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
709 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
710 unsigned TmpReg = makeAnotherReg (newTy);
711 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
712 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
714 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
715 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
722 switch (oldTyClass) {
726 // Cast to (u)int in the bottom half, and sign(zero) extend in the top
728 const Type *OldHalfTy = oldTy->isSigned() ? Type::IntTy : Type::UIntTy;
729 const Type *NewHalfTy = newTy->isSigned() ? Type::IntTy : Type::UIntTy;
730 unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
731 NewHalfTy, DestReg+1);
732 if (newTy->isSigned ()) {
733 BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
736 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
742 // Just copy both halves.
743 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
744 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
747 default: goto not_yet;
751 default: goto not_yet;
755 std::cerr << "Sorry, cast still unsupported: SrcTy = " << *SrcTy
756 << ", DestTy = " << *DestTy << "\n";
760 void V8ISel::visitLoadInst(LoadInst &I) {
761 unsigned DestReg = getReg (I);
762 unsigned PtrReg = getReg (I.getOperand (0));
763 switch (getClassB (I.getType ())) {
765 if (I.getType ()->isSigned ())
766 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
768 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
771 if (I.getType ()->isSigned ())
772 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
774 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
777 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
780 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
781 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
784 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
787 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
790 std::cerr << "Load instruction not handled: " << I;
796 void V8ISel::visitStoreInst(StoreInst &I) {
797 Value *SrcVal = I.getOperand (0);
798 unsigned SrcReg = getReg (SrcVal);
799 unsigned PtrReg = getReg (I.getOperand (1));
800 switch (getClassB (SrcVal->getType ())) {
802 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
805 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
808 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
811 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
812 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
815 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
818 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
821 std::cerr << "Store instruction not handled: " << I;
827 void V8ISel::visitCallInst(CallInst &I) {
828 MachineInstr *TheCall;
829 // Is it an intrinsic function call?
830 if (Function *F = I.getCalledFunction()) {
831 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
832 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
837 // How much extra call stack will we need?
839 for (unsigned i = 0; i < I.getNumOperands (); ++i) {
840 switch (getClassB (I.getOperand (i)->getType ())) {
841 case cLong: extraStack += 8; break;
842 case cFloat: extraStack += 4; break;
843 case cDouble: extraStack += 8; break;
844 default: extraStack += 4; break;
848 if (extraStack < 0) {
851 // Round up extra stack size to the nearest doubleword.
852 extraStack = (extraStack + 7) & ~7;
856 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
858 const unsigned *OAREnd = &OutgoingArgRegs[6];
859 const unsigned *OAR = &OutgoingArgRegs[0];
860 unsigned ArgOffset = 68;
861 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKDOWN, 1).addImm (extraStack);
862 for (unsigned i = 1; i < I.getNumOperands (); ++i) {
863 unsigned ArgReg = getReg (I.getOperand (i));
864 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
865 // Schlep it over into the incoming arg register
866 if (ArgOffset < 92) {
867 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
868 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
870 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
873 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
874 if (ArgOffset < 92) {
875 // Single-fp args are passed in integer registers; go through
876 // memory to get them out of FP registers. (Bleh!)
877 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
878 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
879 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
880 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
881 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
883 BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
886 } else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
887 // Double-fp args are passed in pairs of integer registers; go through
888 // memory to get them out of FP registers. (Bleh!)
889 // We'd like to 'std' these right onto the outgoing-args area, but it might
890 // not be 8-byte aligned (e.g., call x(int x, double d)). sigh.
891 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
892 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
893 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
894 if (ArgOffset < 92 && OAR != OAREnd) {
895 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
896 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
898 unsigned TempReg = makeAnotherReg (Type::IntTy);
899 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
900 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
903 if (ArgOffset < 92 && OAR != OAREnd) {
904 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
905 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
907 unsigned TempReg = makeAnotherReg (Type::IntTy);
908 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
909 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
912 } else if (getClassB (I.getOperand (i)->getType ()) == cLong) {
913 // do the first half...
914 if (ArgOffset < 92) {
915 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
916 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
918 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
921 // ...then do the second half
922 if (ArgOffset < 92) {
923 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
924 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
926 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg+1);
930 assert (0 && "Unknown class?!");
934 // Emit call instruction
935 if (Function *F = I.getCalledFunction ()) {
936 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
937 } else { // Emit an indirect call...
938 unsigned Reg = getReg (I.getCalledValue ());
939 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
942 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKUP, 1).addImm (extraStack);
944 // Deal w/ return value: schlep it over into the destination register
945 if (I.getType () == Type::VoidTy)
947 unsigned DestReg = getReg (I);
948 switch (getClassB (I.getType ())) {
952 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
955 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
958 BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
961 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
962 BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
965 std::cerr << "Return type of call instruction not handled: " << I;
970 void V8ISel::visitReturnInst(ReturnInst &I) {
971 if (I.getNumOperands () == 1) {
972 unsigned RetValReg = getReg (I.getOperand (0));
973 switch (getClassB (I.getOperand (0)->getType ())) {
977 // Schlep it over into i0 (where it will become o0 after restore).
978 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
981 BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
984 BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
987 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
988 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
991 std::cerr << "Return instruction of this type not handled: " << I;
996 // Just emit a 'retl' instruction to return.
997 BuildMI(BB, V8::RETL, 0);
1001 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1002 Function::iterator I = BB; ++I; // Get iterator to next block
1003 return I != BB->getParent()->end() ? &*I : 0;
1006 /// visitBranchInst - Handles conditional and unconditional branches.
1008 void V8ISel::visitBranchInst(BranchInst &I) {
1009 BasicBlock *takenSucc = I.getSuccessor (0);
1010 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
1011 BB->addSuccessor (takenSuccMBB);
1012 if (I.isConditional()) { // conditional branch
1013 BasicBlock *notTakenSucc = I.getSuccessor (1);
1014 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
1015 BB->addSuccessor (notTakenSuccMBB);
1017 // CondReg=(<condition>);
1018 // If (CondReg==0) goto notTakenSuccMBB;
1019 unsigned CondReg = getReg (I.getCondition ());
1020 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
1021 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
1023 // goto takenSuccMBB;
1024 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
1027 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
1028 /// constant expression GEP support.
1030 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
1031 MachineBasicBlock::iterator IP,
1032 Value *Src, User::op_iterator IdxBegin,
1033 User::op_iterator IdxEnd, unsigned TargetReg) {
1034 const TargetData &TD = TM.getTargetData ();
1035 const Type *Ty = Src->getType ();
1036 unsigned basePtrReg = getReg (Src, MBB, IP);
1038 // GEPs have zero or more indices; we must perform a struct access
1039 // or array access for each one.
1040 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
1043 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
1044 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
1045 // It's a struct access. idx is the index into the structure,
1046 // which names the field. Use the TargetData structure to
1047 // pick out what the layout of the structure is in memory.
1048 // Use the (constant) structure index's value to find the
1049 // right byte offset from the StructLayout class's list of
1050 // structure member offsets.
1051 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
1052 unsigned memberOffset =
1053 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
1054 // Emit an ADD to add memberOffset to the basePtr.
1055 BuildMI (*MBB, IP, V8::ADDri, 2,
1056 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
1057 // The next type is the member of the structure selected by the
1059 Ty = StTy->getElementType (fieldIndex);
1060 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
1061 // It's an array or pointer access: [ArraySize x ElementType].
1062 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
1063 // must find the size of the pointed-to type (Not coincidentally, the next
1064 // type is the type of the elements in the array).
1065 Ty = SqTy->getElementType ();
1066 unsigned elementSize = TD.getTypeSize (Ty);
1067 unsigned idxReg = getReg (idx, MBB, IP);
1068 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
1069 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
1070 copyConstantToRegister (MBB, IP,
1071 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
1072 // Emit a SMUL to multiply the register holding the index by
1073 // elementSize, putting the result in OffsetReg.
1074 BuildMI (*MBB, IP, V8::SMULrr, 2,
1075 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
1076 // Emit an ADD to add OffsetReg to the basePtr.
1077 BuildMI (*MBB, IP, V8::ADDrr, 2,
1078 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
1080 basePtrReg = nextBasePtrReg;
1082 // After we have processed all the indices, the result is left in
1083 // basePtrReg. Move it to the register where we were expected to
1085 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
1088 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
1089 unsigned outputReg = getReg (I);
1090 emitGEPOperation (BB, BB->end (), I.getOperand (0),
1091 I.op_begin ()+1, I.op_end (), outputReg);
1095 void V8ISel::visitBinaryOperator (Instruction &I) {
1096 unsigned DestReg = getReg (I);
1097 unsigned Op0Reg = getReg (I.getOperand (0));
1098 unsigned Op1Reg = getReg (I.getOperand (1));
1100 unsigned Class = getClassB (I.getType());
1101 unsigned OpCase = ~0;
1103 if (Class > cLong) {
1104 switch (I.getOpcode ()) {
1105 case Instruction::Add: OpCase = 0; break;
1106 case Instruction::Sub: OpCase = 1; break;
1107 case Instruction::Mul: OpCase = 2; break;
1108 case Instruction::Div: OpCase = 3; break;
1109 default: visitInstruction (I); return;
1111 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
1112 V8::FSUBS, V8::FSUBD,
1113 V8::FMULS, V8::FMULD,
1114 V8::FDIVS, V8::FDIVD };
1115 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
1116 .addReg (Op0Reg).addReg (Op1Reg);
1120 unsigned ResultReg = DestReg;
1121 if (Class != cInt && Class != cLong)
1122 ResultReg = makeAnotherReg (I.getType ());
1124 if (Class == cLong) {
1125 DEBUG (std::cerr << "Class = cLong\n");
1126 DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
1127 DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
1128 DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
1129 DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
1132 // FIXME: support long, ulong.
1133 switch (I.getOpcode ()) {
1134 case Instruction::Add: OpCase = 0; break;
1135 case Instruction::Sub: OpCase = 1; break;
1136 case Instruction::Mul: OpCase = 2; break;
1137 case Instruction::And: OpCase = 3; break;
1138 case Instruction::Or: OpCase = 4; break;
1139 case Instruction::Xor: OpCase = 5; break;
1140 case Instruction::Shl: OpCase = 6; break;
1141 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
1143 case Instruction::Div:
1144 case Instruction::Rem: {
1145 unsigned Dest = ResultReg;
1146 if (I.getOpcode() == Instruction::Rem)
1147 Dest = makeAnotherReg(I.getType());
1149 // FIXME: this is probably only right for 32 bit operands.
1150 if (I.getType ()->isSigned()) {
1151 unsigned Tmp = makeAnotherReg (I.getType ());
1152 // Sign extend into the Y register
1153 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
1154 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
1155 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1157 // Zero extend into the Y register, ie, just set it to zero
1158 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
1159 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1162 if (I.getOpcode() == Instruction::Rem) {
1163 unsigned Tmp = makeAnotherReg (I.getType ());
1164 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
1165 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
1170 visitInstruction (I);
1174 static const unsigned Opcodes[] = {
1175 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
1176 V8::SLLrr, V8::SRLrr, V8::SRArr
1178 if (OpCase != ~0U) {
1179 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1182 switch (getClassB (I.getType ())) {
1184 if (I.getType ()->isSigned ()) { // add byte
1185 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
1186 } else { // add ubyte
1187 unsigned TmpReg = makeAnotherReg (I.getType ());
1188 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
1189 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
1193 if (I.getType ()->isSigned ()) { // add short
1194 unsigned TmpReg = makeAnotherReg (I.getType ());
1195 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1196 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
1197 } else { // add ushort
1198 unsigned TmpReg = makeAnotherReg (I.getType ());
1199 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1200 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
1204 // Nothing to do here.
1207 // Only support and, or, xor.
1208 if (OpCase < 3 || OpCase > 5) {
1209 visitInstruction (I);
1212 // Do the other half of the value:
1213 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
1217 visitInstruction (I);
1221 void V8ISel::visitSetCondInst(SetCondInst &I) {
1222 unsigned Op0Reg = getReg (I.getOperand (0));
1223 unsigned Op1Reg = getReg (I.getOperand (1));
1224 unsigned DestReg = getReg (I);
1225 const Type *Ty = I.getOperand (0)->getType ();
1227 // Compare the two values.
1228 assert (getClass (Ty) != cLong && "can't setcc on longs yet");
1229 if (getClass (Ty) < cLong) {
1230 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1231 } else if (getClass (Ty) == cFloat) {
1232 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1233 } else if (getClass (Ty) == cDouble) {
1234 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1238 switch (I.getOpcode()) {
1239 default: assert(0 && "Unknown setcc instruction!");
1240 case Instruction::SetEQ: BranchIdx = 0; break;
1241 case Instruction::SetNE: BranchIdx = 1; break;
1242 case Instruction::SetLT: BranchIdx = 2; break;
1243 case Instruction::SetGT: BranchIdx = 3; break;
1244 case Instruction::SetLE: BranchIdx = 4; break;
1245 case Instruction::SetGE: BranchIdx = 5; break;
1247 unsigned Column = 0;
1248 if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
1249 if (Ty->isFloatingPoint()) Column = 2;
1250 static unsigned OpcodeTab[3*6] = {
1252 // unsigned signed fp
1253 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1254 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1255 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1256 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1257 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1258 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1260 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1262 MachineBasicBlock *thisMBB = BB;
1263 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1266 // subcc %reg0, %reg1, %g0
1270 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1271 // if we could insert other, non-terminator instructions after the
1272 // bCC. But MBB->getFirstTerminator() can't understand this.
1273 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
1274 F->getBasicBlockList ().push_back (copy1MBB);
1275 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
1276 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1277 F->getBasicBlockList ().push_back (copy0MBB);
1278 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
1279 // Update machine-CFG edges
1280 BB->addSuccessor (copy1MBB);
1281 BB->addSuccessor (copy0MBB);
1284 // %FalseValue = or %G0, 0
1287 unsigned FalseValue = makeAnotherReg (I.getType ());
1288 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
1289 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1290 F->getBasicBlockList ().push_back (sinkMBB);
1291 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1292 // Update machine-CFG edges
1293 BB->addSuccessor (sinkMBB);
1295 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1296 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
1297 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1298 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1301 // %TrueValue = or %G0, 1
1304 unsigned TrueValue = makeAnotherReg (I.getType ());
1305 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1306 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1307 // Update machine-CFG edges
1308 BB->addSuccessor (sinkMBB);
1311 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1314 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1315 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1318 void V8ISel::visitAllocaInst(AllocaInst &I) {
1319 // Find the data size of the alloca inst's getAllocatedType.
1320 const Type *Ty = I.getAllocatedType();
1321 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1323 unsigned ArraySizeReg = getReg (I.getArraySize ());
1324 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1325 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1326 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1327 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1329 // StackAdjReg = (ArraySize * TySize) rounded up to nearest
1330 // doubleword boundary.
1331 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1333 // Round up TmpReg1 to nearest doubleword boundary:
1334 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1335 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1337 // Subtract size from stack pointer, thereby allocating some space.
1338 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1340 // Put a pointer to the space into the result register, by copying
1341 // the stack pointer.
1342 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1344 // Inform the Frame Information that we have just allocated a variable-sized
1346 F->getFrameInfo()->CreateVariableSizedObject();
1349 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1350 /// function, lowering any calls to unknown intrinsic functions into the
1351 /// equivalent LLVM code.
1352 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1353 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1354 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1355 if (CallInst *CI = dyn_cast<CallInst>(I++))
1356 if (Function *F = CI->getCalledFunction())
1357 switch (F->getIntrinsicID()) {
1358 case Intrinsic::vastart:
1359 case Intrinsic::vacopy:
1360 case Intrinsic::vaend:
1361 // We directly implement these intrinsics
1362 case Intrinsic::not_intrinsic: break;
1364 // All other intrinsic calls we must lower.
1365 Instruction *Before = CI->getPrev();
1366 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1367 if (Before) { // Move iterator to instruction after call
1376 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1379 std::cerr << "Sorry, unknown intrinsic function call:\n" << CI; abort ();
1381 case Intrinsic::vastart: {
1382 // Add the VarArgsOffset to the frame pointer, and copy it to the result.
1383 unsigned DestReg = getReg (CI);
1384 BuildMI (BB, V8::ADDri, 2, DestReg).addReg (V8::FP).addSImm (VarArgsOffset);
1388 case Intrinsic::vaend:
1389 // va_end is a no-op on SparcV8.
1392 case Intrinsic::vacopy: {
1393 // Copy the va_list ptr (arg1) to the result.
1394 unsigned DestReg = getReg (CI), SrcReg = getReg (CI.getOperand (1));
1395 BuildMI (BB, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
1401 void V8ISel::visitVANextInst (VANextInst &I) {
1402 // Add the type size to the vararg pointer (arg0).
1403 unsigned DestReg = getReg (I);
1404 unsigned SrcReg = getReg (I.getOperand (0));
1405 unsigned TySize = TM.getTargetData ().getTypeSize (I.getArgType ());
1406 BuildMI (BB, V8::ADDri, 2, DestReg).addReg (SrcReg).addSImm (TySize);
1409 void V8ISel::visitVAArgInst (VAArgInst &I) {
1410 unsigned VAList = getReg (I.getOperand (0));
1411 unsigned DestReg = getReg (I);
1413 switch (I.getType ()->getTypeID ()) {
1414 case Type::PointerTyID:
1415 case Type::UIntTyID:
1417 BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
1420 case Type::ULongTyID:
1421 case Type::LongTyID:
1422 BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
1423 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
1426 case Type::DoubleTyID: {
1427 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
1428 unsigned TempReg = makeAnotherReg (Type::IntTy);
1429 unsigned TempReg2 = makeAnotherReg (Type::IntTy);
1430 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
1431 BuildMI (BB, V8::LD, 2, TempReg).addReg (VAList).addSImm (0);
1432 BuildMI (BB, V8::LD, 2, TempReg2).addReg (VAList).addSImm (4);
1433 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
1434 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
1435 BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
1440 std::cerr << "Sorry, vaarg instruction of this type still unsupported:\n"