1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
33 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
35 MachineFunction *F; // The function we are compiling into
36 MachineBasicBlock *BB; // The current MBB we are compiling
38 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
40 // MBBMap - Mapping between LLVM BB -> Machine BB
41 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
43 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
45 /// runOnFunction - Top level implementation of instruction selection for
46 /// the entire function.
48 bool runOnFunction(Function &Fn);
50 virtual const char *getPassName() const {
51 return "SparcV8 Simple Instruction Selection";
54 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
55 /// constant expression GEP support.
57 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
58 Value *Src, User::op_iterator IdxBegin,
59 User::op_iterator IdxEnd, unsigned TargetReg);
61 /// emitCastOperation - Common code shared between visitCastInst and
62 /// constant expression cast support.
64 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
65 Value *Src, const Type *DestTy, unsigned TargetReg);
67 /// emitIntegerCast, emitFPToIntegerCast - Helper methods for
68 /// emitCastOperation.
70 void emitIntegerCast (MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
71 const Type *oldTy, unsigned SrcReg, const Type *newTy,
73 void emitFPToIntegerCast (MachineBasicBlock *BB,
74 MachineBasicBlock::iterator IP, const Type *oldTy,
75 unsigned SrcReg, const Type *newTy,
78 /// visitBasicBlock - This method is called when we are visiting a new basic
79 /// block. This simply creates a new MachineBasicBlock to emit code into
80 /// and adds it to the current MachineFunction. Subsequent visit* for
81 /// instructions will be invoked for all instructions in the basic block.
83 void visitBasicBlock(BasicBlock &LLVM_BB) {
84 BB = MBBMap[&LLVM_BB];
87 void visitBinaryOperator(Instruction &I);
88 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
89 void visitSetCondInst(SetCondInst &I);
90 void visitCallInst(CallInst &I);
91 void visitReturnInst(ReturnInst &I);
92 void visitBranchInst(BranchInst &I);
93 void visitUnreachableInst(UnreachableInst &I) {}
94 void visitCastInst(CastInst &I);
95 void visitLoadInst(LoadInst &I);
96 void visitStoreInst(StoreInst &I);
97 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
98 void visitGetElementPtrInst(GetElementPtrInst &I);
99 void visitAllocaInst(AllocaInst &I);
101 void visitInstruction(Instruction &I) {
102 std::cerr << "Unhandled instruction: " << I;
106 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
107 /// function, lowering any calls to unknown intrinsic functions into the
108 /// equivalent LLVM code.
109 void LowerUnknownIntrinsicFunctionCalls(Function &F);
110 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
112 void LoadArgumentsToVirtualRegs(Function *F);
114 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
115 /// because we have to generate our sources into the source basic blocks,
116 /// not the current one.
118 void SelectPHINodes();
120 /// copyConstantToRegister - Output the instructions required to put the
121 /// specified constant into the specified register.
123 void copyConstantToRegister(MachineBasicBlock *MBB,
124 MachineBasicBlock::iterator IP,
125 Constant *C, unsigned R);
127 /// makeAnotherReg - This method returns the next register number we haven't
130 /// Long values are handled somewhat specially. They are always allocated
131 /// as pairs of 32 bit integer values. The register number returned is the
132 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
133 /// of the long value.
135 unsigned makeAnotherReg(const Type *Ty) {
136 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
137 "Current target doesn't have SparcV8 reg info??");
138 const SparcV8RegisterInfo *MRI =
139 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
140 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
141 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
142 // Create the lower part
143 F->getSSARegMap()->createVirtualRegister(RC);
144 // Create the upper part.
145 return F->getSSARegMap()->createVirtualRegister(RC)-1;
148 // Add the mapping of regnumber => reg class to MachineFunction
149 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
150 return F->getSSARegMap()->createVirtualRegister(RC);
153 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
154 unsigned getReg(Value *V) {
155 // Just append to the end of the current bb.
156 MachineBasicBlock::iterator It = BB->end();
157 return getReg(V, BB, It);
159 unsigned getReg(Value *V, MachineBasicBlock *MBB,
160 MachineBasicBlock::iterator IPt) {
161 unsigned &Reg = RegMap[V];
163 Reg = makeAnotherReg(V->getType());
166 // If this operand is a constant, emit the code to copy the constant into
167 // the register here...
169 if (Constant *C = dyn_cast<Constant>(V)) {
170 copyConstantToRegister(MBB, IPt, C, Reg);
171 RegMap.erase(V); // Assign a new name to this constant if ref'd again
172 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
173 // Move the address of the global into the register
174 unsigned TmpReg = makeAnotherReg(V->getType());
175 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
176 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
177 .addGlobalAddress (GV);
178 RegMap.erase(V); // Assign a new name to this address if ref'd again
187 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
188 return new V8ISel(TM);
192 cByte, cShort, cInt, cLong, cFloat, cDouble
195 static TypeClass getClass (const Type *T) {
196 switch (T->getTypeID()) {
197 case Type::UByteTyID: case Type::SByteTyID: return cByte;
198 case Type::UShortTyID: case Type::ShortTyID: return cShort;
199 case Type::PointerTyID:
200 case Type::UIntTyID: case Type::IntTyID: return cInt;
201 case Type::ULongTyID: case Type::LongTyID: return cLong;
202 case Type::FloatTyID: return cFloat;
203 case Type::DoubleTyID: return cDouble;
205 assert (0 && "Type of unknown class passed to getClass?");
210 static TypeClass getClassB(const Type *T) {
211 if (T == Type::BoolTy) return cByte;
215 /// copyConstantToRegister - Output the instructions required to put the
216 /// specified constant into the specified register.
218 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
219 MachineBasicBlock::iterator IP,
220 Constant *C, unsigned R) {
221 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
222 switch (CE->getOpcode()) {
223 case Instruction::GetElementPtr:
224 emitGEPOperation(MBB, IP, CE->getOperand(0),
225 CE->op_begin()+1, CE->op_end(), R);
227 case Instruction::Cast:
228 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
231 std::cerr << "Copying this constant expr not yet handled: " << *CE;
234 } else if (isa<UndefValue>(C)) {
235 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
236 if (getClassB (C->getType ()) == cLong)
237 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
241 if (C->getType()->isIntegral ()) {
243 unsigned Class = getClassB (C->getType ());
244 if (Class == cLong) {
245 unsigned TmpReg = makeAnotherReg (Type::IntTy);
246 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
247 // Copy the value into the register pair.
248 // R = top(more-significant) half, R+1 = bottom(less-significant) half
249 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
250 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
252 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
253 Val & 0xffffffffU), R+1);
257 assert(Class <= cInt && "Type not handled yet!");
259 if (C->getType() == Type::BoolTy) {
260 Val = (C == ConstantBool::True);
262 ConstantInt *CI = cast<ConstantInt> (C);
263 Val = CI->getRawValue ();
266 case cByte: Val = (int8_t) Val; break;
267 case cShort: Val = (int16_t) Val; break;
268 case cInt: Val = (int32_t) Val; break;
270 std::cerr << "Offending constant: " << *C << "\n";
271 assert (0 && "Can't copy this kind of constant into register yet");
275 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
276 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
277 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
279 unsigned TmpReg = makeAnotherReg (C->getType ());
280 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
281 .addSImm (((uint32_t) Val) >> 10);
282 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
283 .addSImm (((uint32_t) Val) & 0x03ff);
286 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
287 // We need to spill the constant to memory...
288 MachineConstantPool *CP = F->getConstantPool();
289 unsigned CPI = CP->getConstantPoolIndex(CFP);
290 const Type *Ty = CFP->getType();
291 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
292 unsigned AddrReg = makeAnotherReg (Type::UIntTy);
294 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
295 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
296 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
297 BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
298 .addConstantPoolIndex (CPI);
299 BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
300 } else if (isa<ConstantPointerNull>(C)) {
301 // Copy zero (null pointer) to the register.
302 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
303 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
304 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
305 // that SETHI %reg,global == SETHI %reg,%hi(global) and
306 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
307 unsigned TmpReg = makeAnotherReg (C->getType ());
308 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
309 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
311 std::cerr << "Offending constant: " << *C << "\n";
312 assert (0 && "Can't copy this kind of constant into register yet");
316 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
317 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
318 V8::I3, V8::I4, V8::I5 };
320 // Add IMPLICIT_DEFs of input regs.
322 for (Function::aiterator I = LF->abegin(), E = LF->aend();
323 I != E && ArgNo < 6; ++I, ++ArgNo) {
324 switch (getClassB(I->getType())) {
329 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
333 // Double and Long use register pairs.
334 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
337 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
340 assert (0 && "type not handled");
345 // Copy args out of their incoming hard regs or stack slots into virtual regs.
346 const unsigned *IAREnd = &IncomingArgRegs[6];
347 const unsigned *IAR = &IncomingArgRegs[0];
348 unsigned ArgOffset = 68;
349 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
351 unsigned ArgReg = getReg (A);
352 if (getClassB (A.getType ()) < cLong) {
353 // Get it out of the incoming arg register
354 if (ArgOffset < 92) {
355 assert (IAR != IAREnd
356 && "About to dereference past end of IncomingArgRegs");
357 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
359 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
360 BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
363 } else if (getClassB (A.getType ()) == cFloat) {
364 if (ArgOffset < 92) {
365 // Single-fp args are passed in integer registers; go through
366 // memory to get them out of integer registers and back into fp. (Bleh!)
367 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
368 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
369 assert (IAR != IAREnd
370 && "About to dereference past end of IncomingArgRegs");
371 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
372 BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
374 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
375 BuildMI (BB, V8::LDFri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
378 } else if (getClassB (A.getType ()) == cDouble) {
379 // Double-fp args are passed in pairs of integer registers; go through
380 // memory to get them out of integer registers and back into fp. (Bleh!)
381 // We'd like to 'ldd' these right out of the incoming-args area,
382 // but it might not be 8-byte aligned (e.g., call x(int x, double d)).
383 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
384 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
385 if (ArgOffset < 92 && IAR != IAREnd) {
386 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
388 unsigned TempReg = makeAnotherReg (Type::IntTy);
389 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
390 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
393 if (ArgOffset < 92 && IAR != IAREnd) {
394 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
396 unsigned TempReg = makeAnotherReg (Type::IntTy);
397 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
398 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
401 BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
402 } else if (getClassB (A.getType ()) == cLong) {
403 // do the first half...
404 if (ArgOffset < 92) {
405 assert (IAR != IAREnd
406 && "About to dereference past end of IncomingArgRegs");
407 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
409 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
410 BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
413 // ...then do the second half
414 if (ArgOffset < 92) {
415 assert (IAR != IAREnd
416 && "About to dereference past end of IncomingArgRegs");
417 BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
419 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
420 BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
424 assert (0 && "Unknown class?!");
429 void V8ISel::SelectPHINodes() {
430 const TargetInstrInfo &TII = *TM.getInstrInfo();
431 const Function &LF = *F->getFunction(); // The LLVM function...
432 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
433 const BasicBlock *BB = I;
434 MachineBasicBlock &MBB = *MBBMap[I];
436 // Loop over all of the PHI nodes in the LLVM basic block...
437 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
438 for (BasicBlock::const_iterator I = BB->begin();
439 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
441 // Create a new machine instr PHI node, and insert it.
442 unsigned PHIReg = getReg(*PN);
443 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
444 V8::PHI, PN->getNumOperands(), PHIReg);
446 MachineInstr *LongPhiMI = 0;
447 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
448 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
449 V8::PHI, PN->getNumOperands(), PHIReg+1);
451 // PHIValues - Map of blocks to incoming virtual registers. We use this
452 // so that we only initialize one incoming value for a particular block,
453 // even if the block has multiple entries in the PHI node.
455 std::map<MachineBasicBlock*, unsigned> PHIValues;
457 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
458 MachineBasicBlock *PredMBB = 0;
459 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
460 PE = MBB.pred_end (); PI != PE; ++PI)
461 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
465 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
468 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
469 PHIValues.lower_bound(PredMBB);
471 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
472 // We already inserted an initialization of the register for this
473 // predecessor. Recycle it.
474 ValReg = EntryIt->second;
477 // Get the incoming value into a virtual register.
479 Value *Val = PN->getIncomingValue(i);
481 // If this is a constant or GlobalValue, we may have to insert code
482 // into the basic block to compute it into a virtual register.
483 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
484 isa<GlobalValue>(Val)) {
485 // Simple constants get emitted at the end of the basic block,
486 // before any terminator instructions. We "know" that the code to
487 // move a constant into a register will never clobber any flags.
488 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
490 // Because we don't want to clobber any values which might be in
491 // physical registers with the computation of this constant (which
492 // might be arbitrarily complex if it is a constant expression),
493 // just insert the computation at the top of the basic block.
494 MachineBasicBlock::iterator PI = PredMBB->begin();
496 // Skip over any PHI nodes though!
497 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
500 ValReg = getReg(Val, PredMBB, PI);
503 // Remember that we inserted a value for this PHI for this predecessor
504 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
507 PhiMI->addRegOperand(ValReg);
508 PhiMI->addMachineBasicBlockOperand(PredMBB);
510 LongPhiMI->addRegOperand(ValReg+1);
511 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
515 // Now that we emitted all of the incoming values for the PHI node, make
516 // sure to reposition the InsertPoint after the PHI that we just added.
517 // This is needed because we might have inserted a constant into this
518 // block, right after the PHI's which is before the old insert point!
519 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
525 bool V8ISel::runOnFunction(Function &Fn) {
526 // First pass over the function, lower any unknown intrinsic functions
527 // with the IntrinsicLowering class.
528 LowerUnknownIntrinsicFunctionCalls(Fn);
530 F = &MachineFunction::construct(&Fn, TM);
532 // Create all of the machine basic blocks for the function...
533 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
534 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
538 // Set up a frame object for the return address. This is used by the
539 // llvm.returnaddress & llvm.frameaddress intrinisics.
540 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
542 // Copy incoming arguments off of the stack and out of fixed registers.
543 LoadArgumentsToVirtualRegs(&Fn);
545 // Instruction select everything except PHI nodes
548 // Select the PHI nodes
554 // We always build a machine code representation for the function
558 void V8ISel::visitCastInst(CastInst &I) {
559 Value *Op = I.getOperand(0);
560 unsigned DestReg = getReg(I);
561 MachineBasicBlock::iterator MI = BB->end();
562 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
566 void V8ISel::emitIntegerCast (MachineBasicBlock *BB,
567 MachineBasicBlock::iterator IP, const Type *oldTy,
568 unsigned SrcReg, const Type *newTy,
570 if (oldTy == newTy) {
571 // No-op cast - just emit a copy; assume the reg. allocator will zap it.
572 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg(SrcReg);
575 // Emit left-shift, then right-shift to sign- or zero-extend.
576 unsigned TmpReg = makeAnotherReg (newTy);
577 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
578 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg).addZImm (shiftWidth).addReg(SrcReg);
579 if (newTy->isSigned ()) { // sign-extend with SRA
580 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
581 } else { // zero-extend with SRL
582 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
586 void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
587 MachineBasicBlock::iterator IP,
588 const Type *oldTy, unsigned SrcReg,
589 const Type *newTy, unsigned DestReg) {
590 unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
591 unsigned oldTyClass = getClassB(oldTy);
592 if (oldTyClass == cFloat) {
593 FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
594 FPAlign = TM.getTargetData().getFloatAlignment();
595 } else { // it's a double
596 FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
597 FPAlign = TM.getTargetData().getDoubleAlignment();
599 unsigned TempReg = makeAnotherReg (oldTy);
600 BuildMI (*BB, IP, FPCastOpcode, 1, TempReg).addReg (SrcReg);
601 int FI = F->getFrameInfo()->CreateStackObject(FPSize, FPAlign);
602 BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
604 unsigned TempReg2 = makeAnotherReg (newTy);
605 BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
606 emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
609 /// emitCastOperation - Common code shared between visitCastInst and constant
610 /// expression cast support.
612 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
613 MachineBasicBlock::iterator IP, Value *Src,
614 const Type *DestTy, unsigned DestReg) {
615 const Type *SrcTy = Src->getType();
616 unsigned SrcClass = getClassB(SrcTy);
617 unsigned DestClass = getClassB(DestTy);
618 unsigned SrcReg = getReg(Src, BB, IP);
620 const Type *oldTy = SrcTy;
621 const Type *newTy = DestTy;
622 unsigned oldTyClass = SrcClass;
623 unsigned newTyClass = DestClass;
625 if (oldTyClass < cLong && newTyClass < cLong) {
626 emitIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
627 } else switch (newTyClass) {
631 switch (oldTyClass) {
634 emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
636 default: goto not_yet;
641 switch (oldTyClass) {
642 case cLong: goto not_yet;
644 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
647 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
650 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
651 // cast integer type to float. Store it to a stack slot and then load
652 // it using ldf into a floating point register. then do fitos.
653 unsigned TmpReg = makeAnotherReg (newTy);
654 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
655 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
657 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
658 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
665 switch (oldTyClass) {
666 case cLong: goto not_yet;
668 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
670 case cDouble: // use double move pseudo-instr
671 BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
674 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
675 unsigned TmpReg = makeAnotherReg (newTy);
676 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
677 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
679 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
680 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
687 switch (oldTyClass) {
691 // Just copy it to the bottom half, and put a zero in the top half.
692 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
694 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
698 // Just copy both halves.
699 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
700 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
703 default: goto not_yet;
707 default: goto not_yet;
711 std::cerr << "Sorry, cast still unsupported: SrcTy = " << *SrcTy
712 << ", DestTy = " << *DestTy << "\n";
716 void V8ISel::visitLoadInst(LoadInst &I) {
717 unsigned DestReg = getReg (I);
718 unsigned PtrReg = getReg (I.getOperand (0));
719 switch (getClassB (I.getType ())) {
721 if (I.getType ()->isSigned ())
722 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
724 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
727 if (I.getType ()->isSigned ())
728 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
730 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
733 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
736 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
737 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
740 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
743 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
746 std::cerr << "Load instruction not handled: " << I;
752 void V8ISel::visitStoreInst(StoreInst &I) {
753 Value *SrcVal = I.getOperand (0);
754 unsigned SrcReg = getReg (SrcVal);
755 unsigned PtrReg = getReg (I.getOperand (1));
756 switch (getClassB (SrcVal->getType ())) {
758 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
761 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
764 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
767 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
768 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
771 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
774 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
777 std::cerr << "Store instruction not handled: " << I;
783 void V8ISel::visitCallInst(CallInst &I) {
784 MachineInstr *TheCall;
785 // Is it an intrinsic function call?
786 if (Function *F = I.getCalledFunction()) {
787 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
788 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
793 unsigned extraStack = 0;
794 // How much extra call stack will we need?
795 for (unsigned i = 7; i < I.getNumOperands (); ++i) {
796 switch (getClassB (I.getOperand (i)->getType ())) {
797 case cLong: extraStack += 8; break;
798 case cFloat: extraStack += 4; break;
799 case cDouble: extraStack += 8; break;
800 default: extraStack += 4; break;
803 // Round up extra stack size to the nearest doubleword.
804 if (extraStack) { extraStack = (extraStack + 7) & ~7; }
807 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
809 const unsigned *OAREnd = &OutgoingArgRegs[6];
810 const unsigned *OAR = &OutgoingArgRegs[0];
811 unsigned ArgOffset = 68;
812 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKDOWN, 1).addImm (extraStack);
813 for (unsigned i = 1; i < I.getNumOperands (); ++i) {
814 unsigned ArgReg = getReg (I.getOperand (i));
815 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
816 // Schlep it over into the incoming arg register
817 if (ArgOffset < 92) {
818 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
819 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
821 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
824 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
825 if (ArgOffset < 92) {
826 // Single-fp args are passed in integer registers; go through
827 // memory to get them out of FP registers. (Bleh!)
828 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
829 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
830 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
831 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
832 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
834 BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
837 } else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
838 // Double-fp args are passed in pairs of integer registers; go through
839 // memory to get them out of FP registers. (Bleh!)
840 // We'd like to 'std' these right onto the outgoing-args area, but it might
841 // not be 8-byte aligned (e.g., call x(int x, double d)). sigh.
842 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
843 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
844 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
845 if (ArgOffset < 92 && OAR != OAREnd) {
846 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
847 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
849 unsigned TempReg = makeAnotherReg (Type::IntTy);
850 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
851 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
854 if (ArgOffset < 92 && OAR != OAREnd) {
855 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
856 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
858 unsigned TempReg = makeAnotherReg (Type::IntTy);
859 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
860 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
863 } else if (getClassB (I.getOperand (i)->getType ()) == cLong) {
864 // do the first half...
865 if (ArgOffset < 92) {
866 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
867 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
869 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
872 // ...then do the second half
873 if (ArgOffset < 92) {
874 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
875 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
877 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg+1);
881 assert (0 && "Unknown class?!");
885 // Emit call instruction
886 if (Function *F = I.getCalledFunction ()) {
887 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
888 } else { // Emit an indirect call...
889 unsigned Reg = getReg (I.getCalledValue ());
890 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
893 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKUP, 1).addImm (extraStack);
895 // Deal w/ return value: schlep it over into the destination register
896 if (I.getType () == Type::VoidTy)
898 unsigned DestReg = getReg (I);
899 switch (getClassB (I.getType ())) {
903 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
906 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
909 BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
912 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
913 BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
916 std::cerr << "Return type of call instruction not handled: " << I;
921 void V8ISel::visitReturnInst(ReturnInst &I) {
922 if (I.getNumOperands () == 1) {
923 unsigned RetValReg = getReg (I.getOperand (0));
924 switch (getClassB (I.getOperand (0)->getType ())) {
928 // Schlep it over into i0 (where it will become o0 after restore).
929 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
932 BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
935 BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
938 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
939 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
942 std::cerr << "Return instruction of this type not handled: " << I;
947 // Just emit a 'retl' instruction to return.
948 BuildMI(BB, V8::RETL, 0);
952 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
953 Function::iterator I = BB; ++I; // Get iterator to next block
954 return I != BB->getParent()->end() ? &*I : 0;
957 /// visitBranchInst - Handles conditional and unconditional branches.
959 void V8ISel::visitBranchInst(BranchInst &I) {
960 BasicBlock *takenSucc = I.getSuccessor (0);
961 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
962 BB->addSuccessor (takenSuccMBB);
963 if (I.isConditional()) { // conditional branch
964 BasicBlock *notTakenSucc = I.getSuccessor (1);
965 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
966 BB->addSuccessor (notTakenSuccMBB);
968 // CondReg=(<condition>);
969 // If (CondReg==0) goto notTakenSuccMBB;
970 unsigned CondReg = getReg (I.getCondition ());
971 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
972 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
974 // goto takenSuccMBB;
975 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
978 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
979 /// constant expression GEP support.
981 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
982 MachineBasicBlock::iterator IP,
983 Value *Src, User::op_iterator IdxBegin,
984 User::op_iterator IdxEnd, unsigned TargetReg) {
985 const TargetData &TD = TM.getTargetData ();
986 const Type *Ty = Src->getType ();
987 unsigned basePtrReg = getReg (Src, MBB, IP);
989 // GEPs have zero or more indices; we must perform a struct access
990 // or array access for each one.
991 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
994 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
995 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
996 // It's a struct access. idx is the index into the structure,
997 // which names the field. Use the TargetData structure to
998 // pick out what the layout of the structure is in memory.
999 // Use the (constant) structure index's value to find the
1000 // right byte offset from the StructLayout class's list of
1001 // structure member offsets.
1002 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
1003 unsigned memberOffset =
1004 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
1005 // Emit an ADD to add memberOffset to the basePtr.
1006 BuildMI (*MBB, IP, V8::ADDri, 2,
1007 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
1008 // The next type is the member of the structure selected by the
1010 Ty = StTy->getElementType (fieldIndex);
1011 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
1012 // It's an array or pointer access: [ArraySize x ElementType].
1013 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
1014 // must find the size of the pointed-to type (Not coincidentally, the next
1015 // type is the type of the elements in the array).
1016 Ty = SqTy->getElementType ();
1017 unsigned elementSize = TD.getTypeSize (Ty);
1018 unsigned idxReg = getReg (idx, MBB, IP);
1019 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
1020 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
1021 copyConstantToRegister (MBB, IP,
1022 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
1023 // Emit a SMUL to multiply the register holding the index by
1024 // elementSize, putting the result in OffsetReg.
1025 BuildMI (*MBB, IP, V8::SMULrr, 2,
1026 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
1027 // Emit an ADD to add OffsetReg to the basePtr.
1028 BuildMI (*MBB, IP, V8::ADDrr, 2,
1029 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
1031 basePtrReg = nextBasePtrReg;
1033 // After we have processed all the indices, the result is left in
1034 // basePtrReg. Move it to the register where we were expected to
1036 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
1039 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
1040 unsigned outputReg = getReg (I);
1041 emitGEPOperation (BB, BB->end (), I.getOperand (0),
1042 I.op_begin ()+1, I.op_end (), outputReg);
1046 void V8ISel::visitBinaryOperator (Instruction &I) {
1047 unsigned DestReg = getReg (I);
1048 unsigned Op0Reg = getReg (I.getOperand (0));
1049 unsigned Op1Reg = getReg (I.getOperand (1));
1051 unsigned Class = getClassB (I.getType());
1052 unsigned OpCase = ~0;
1054 if (Class > cLong) {
1055 switch (I.getOpcode ()) {
1056 case Instruction::Add: OpCase = 0; break;
1057 case Instruction::Sub: OpCase = 1; break;
1058 case Instruction::Mul: OpCase = 2; break;
1059 case Instruction::Div: OpCase = 3; break;
1060 default: visitInstruction (I); return;
1062 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
1063 V8::FSUBS, V8::FSUBD,
1064 V8::FMULS, V8::FMULD,
1065 V8::FDIVS, V8::FDIVD };
1066 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
1067 .addReg (Op0Reg).addReg (Op1Reg);
1071 unsigned ResultReg = DestReg;
1072 if (Class != cInt && Class != cLong)
1073 ResultReg = makeAnotherReg (I.getType ());
1075 if (Class == cLong) {
1076 DEBUG (std::cerr << "Class = cLong\n");
1077 DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
1078 DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
1079 DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
1080 DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
1083 // FIXME: support long, ulong.
1084 switch (I.getOpcode ()) {
1085 case Instruction::Add: OpCase = 0; break;
1086 case Instruction::Sub: OpCase = 1; break;
1087 case Instruction::Mul: OpCase = 2; break;
1088 case Instruction::And: OpCase = 3; break;
1089 case Instruction::Or: OpCase = 4; break;
1090 case Instruction::Xor: OpCase = 5; break;
1091 case Instruction::Shl: OpCase = 6; break;
1092 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
1094 case Instruction::Div:
1095 case Instruction::Rem: {
1096 unsigned Dest = ResultReg;
1097 if (I.getOpcode() == Instruction::Rem)
1098 Dest = makeAnotherReg(I.getType());
1100 // FIXME: this is probably only right for 32 bit operands.
1101 if (I.getType ()->isSigned()) {
1102 unsigned Tmp = makeAnotherReg (I.getType ());
1103 // Sign extend into the Y register
1104 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
1105 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
1106 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1108 // Zero extend into the Y register, ie, just set it to zero
1109 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
1110 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1113 if (I.getOpcode() == Instruction::Rem) {
1114 unsigned Tmp = makeAnotherReg (I.getType ());
1115 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
1116 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
1121 visitInstruction (I);
1125 static const unsigned Opcodes[] = {
1126 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
1127 V8::SLLrr, V8::SRLrr, V8::SRArr
1129 if (OpCase != ~0U) {
1130 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1133 switch (getClassB (I.getType ())) {
1135 if (I.getType ()->isSigned ()) { // add byte
1136 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
1137 } else { // add ubyte
1138 unsigned TmpReg = makeAnotherReg (I.getType ());
1139 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
1140 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
1144 if (I.getType ()->isSigned ()) { // add short
1145 unsigned TmpReg = makeAnotherReg (I.getType ());
1146 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1147 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
1148 } else { // add ushort
1149 unsigned TmpReg = makeAnotherReg (I.getType ());
1150 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1151 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
1155 // Nothing to do here.
1158 // Only support and, or, xor.
1159 if (OpCase < 3 || OpCase > 5) {
1160 visitInstruction (I);
1163 // Do the other half of the value:
1164 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
1168 visitInstruction (I);
1172 void V8ISel::visitSetCondInst(SetCondInst &I) {
1173 unsigned Op0Reg = getReg (I.getOperand (0));
1174 unsigned Op1Reg = getReg (I.getOperand (1));
1175 unsigned DestReg = getReg (I);
1176 const Type *Ty = I.getOperand (0)->getType ();
1178 // Compare the two values.
1179 assert (getClass (Ty) != cLong && "can't setcc on longs yet");
1180 if (getClass (Ty) < cLong) {
1181 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1182 } else if (getClass (Ty) == cFloat) {
1183 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1184 } else if (getClass (Ty) == cDouble) {
1185 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1189 switch (I.getOpcode()) {
1190 default: assert(0 && "Unknown setcc instruction!");
1191 case Instruction::SetEQ: BranchIdx = 0; break;
1192 case Instruction::SetNE: BranchIdx = 1; break;
1193 case Instruction::SetLT: BranchIdx = 2; break;
1194 case Instruction::SetGT: BranchIdx = 3; break;
1195 case Instruction::SetLE: BranchIdx = 4; break;
1196 case Instruction::SetGE: BranchIdx = 5; break;
1198 unsigned Column = 0;
1199 if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
1200 if (Ty->isFloatingPoint()) Column = 2;
1201 static unsigned OpcodeTab[3*6] = {
1203 // unsigned signed fp
1204 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1205 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1206 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1207 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1208 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1209 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1211 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1213 MachineBasicBlock *thisMBB = BB;
1214 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1217 // subcc %reg0, %reg1, %g0
1221 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1222 // if we could insert other, non-terminator instructions after the
1223 // bCC. But MBB->getFirstTerminator() can't understand this.
1224 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
1225 F->getBasicBlockList ().push_back (copy1MBB);
1226 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
1227 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1228 F->getBasicBlockList ().push_back (copy0MBB);
1229 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
1230 // Update machine-CFG edges
1231 BB->addSuccessor (copy1MBB);
1232 BB->addSuccessor (copy0MBB);
1235 // %FalseValue = or %G0, 0
1238 unsigned FalseValue = makeAnotherReg (I.getType ());
1239 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
1240 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1241 F->getBasicBlockList ().push_back (sinkMBB);
1242 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1243 // Update machine-CFG edges
1244 BB->addSuccessor (sinkMBB);
1246 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1247 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
1248 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1249 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1252 // %TrueValue = or %G0, 1
1255 unsigned TrueValue = makeAnotherReg (I.getType ());
1256 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1257 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1258 // Update machine-CFG edges
1259 BB->addSuccessor (sinkMBB);
1262 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1265 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1266 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1269 void V8ISel::visitAllocaInst(AllocaInst &I) {
1270 // Find the data size of the alloca inst's getAllocatedType.
1271 const Type *Ty = I.getAllocatedType();
1272 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1274 unsigned ArraySizeReg = getReg (I.getArraySize ());
1275 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1276 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1277 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1278 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1280 // StackAdjReg = (ArraySize * TySize) rounded up to nearest doubleword boundary
1281 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1283 // Round up TmpReg1 to nearest doubleword boundary:
1284 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1285 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1287 // Subtract size from stack pointer, thereby allocating some space.
1288 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1290 // Put a pointer to the space into the result register, by copying
1291 // the stack pointer.
1292 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1294 // Inform the Frame Information that we have just allocated a variable-sized
1296 F->getFrameInfo()->CreateVariableSizedObject();
1299 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1300 /// function, lowering any calls to unknown intrinsic functions into the
1301 /// equivalent LLVM code.
1302 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1303 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1304 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1305 if (CallInst *CI = dyn_cast<CallInst>(I++))
1306 if (Function *F = CI->getCalledFunction())
1307 switch (F->getIntrinsicID()) {
1308 case Intrinsic::not_intrinsic: break;
1310 // All other intrinsic calls we must lower.
1311 Instruction *Before = CI->getPrev();
1312 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1313 if (Before) { // Move iterator to instruction after call
1322 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1323 unsigned TmpReg1, TmpReg2;
1325 default: assert(0 && "Intrinsic not supported!");