1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
33 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
35 MachineFunction *F; // The function we are compiling into
36 MachineBasicBlock *BB; // The current MBB we are compiling
38 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
40 // MBBMap - Mapping between LLVM BB -> Machine BB
41 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
43 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
45 /// runOnFunction - Top level implementation of instruction selection for
46 /// the entire function.
48 bool runOnFunction(Function &Fn);
50 virtual const char *getPassName() const {
51 return "SparcV8 Simple Instruction Selection";
54 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
55 /// constant expression GEP support.
57 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
58 Value *Src, User::op_iterator IdxBegin,
59 User::op_iterator IdxEnd, unsigned TargetReg);
61 /// emitCastOperation - Common code shared between visitCastInst and
62 /// constant expression cast support.
64 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
65 Value *Src, const Type *DestTy, unsigned TargetReg);
67 /// emitIntegerCast, emitFPToIntegerCast - Helper methods for
68 /// emitCastOperation.
70 unsigned emitIntegerCast (MachineBasicBlock *BB,
71 MachineBasicBlock::iterator IP,
72 const Type *oldTy, unsigned SrcReg,
73 const Type *newTy, unsigned DestReg);
74 void emitFPToIntegerCast (MachineBasicBlock *BB,
75 MachineBasicBlock::iterator IP, const Type *oldTy,
76 unsigned SrcReg, const Type *newTy,
79 /// visitBasicBlock - This method is called when we are visiting a new basic
80 /// block. This simply creates a new MachineBasicBlock to emit code into
81 /// and adds it to the current MachineFunction. Subsequent visit* for
82 /// instructions will be invoked for all instructions in the basic block.
84 void visitBasicBlock(BasicBlock &LLVM_BB) {
85 BB = MBBMap[&LLVM_BB];
88 void visitBinaryOperator(Instruction &I);
89 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
90 void visitSetCondInst(SetCondInst &I);
91 void visitCallInst(CallInst &I);
92 void visitReturnInst(ReturnInst &I);
93 void visitBranchInst(BranchInst &I);
94 void visitUnreachableInst(UnreachableInst &I) {}
95 void visitCastInst(CastInst &I);
96 void visitLoadInst(LoadInst &I);
97 void visitStoreInst(StoreInst &I);
98 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
99 void visitGetElementPtrInst(GetElementPtrInst &I);
100 void visitAllocaInst(AllocaInst &I);
102 void visitInstruction(Instruction &I) {
103 std::cerr << "Unhandled instruction: " << I;
107 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
108 /// function, lowering any calls to unknown intrinsic functions into the
109 /// equivalent LLVM code.
110 void LowerUnknownIntrinsicFunctionCalls(Function &F);
111 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
113 void LoadArgumentsToVirtualRegs(Function *F);
115 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
116 /// because we have to generate our sources into the source basic blocks,
117 /// not the current one.
119 void SelectPHINodes();
121 /// copyConstantToRegister - Output the instructions required to put the
122 /// specified constant into the specified register.
124 void copyConstantToRegister(MachineBasicBlock *MBB,
125 MachineBasicBlock::iterator IP,
126 Constant *C, unsigned R);
128 /// makeAnotherReg - This method returns the next register number we haven't
131 /// Long values are handled somewhat specially. They are always allocated
132 /// as pairs of 32 bit integer values. The register number returned is the
133 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
134 /// of the long value.
136 unsigned makeAnotherReg(const Type *Ty) {
137 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
138 "Current target doesn't have SparcV8 reg info??");
139 const SparcV8RegisterInfo *MRI =
140 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
141 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
142 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
143 // Create the lower part
144 F->getSSARegMap()->createVirtualRegister(RC);
145 // Create the upper part.
146 return F->getSSARegMap()->createVirtualRegister(RC)-1;
149 // Add the mapping of regnumber => reg class to MachineFunction
150 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
151 return F->getSSARegMap()->createVirtualRegister(RC);
154 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
155 unsigned getReg(Value *V) {
156 // Just append to the end of the current bb.
157 MachineBasicBlock::iterator It = BB->end();
158 return getReg(V, BB, It);
160 unsigned getReg(Value *V, MachineBasicBlock *MBB,
161 MachineBasicBlock::iterator IPt) {
162 unsigned &Reg = RegMap[V];
164 Reg = makeAnotherReg(V->getType());
167 // If this operand is a constant, emit the code to copy the constant into
168 // the register here...
170 if (Constant *C = dyn_cast<Constant>(V)) {
171 copyConstantToRegister(MBB, IPt, C, Reg);
172 RegMap.erase(V); // Assign a new name to this constant if ref'd again
173 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
174 // Move the address of the global into the register
175 unsigned TmpReg = makeAnotherReg(V->getType());
176 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
177 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
178 .addGlobalAddress (GV);
179 RegMap.erase(V); // Assign a new name to this address if ref'd again
188 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
189 return new V8ISel(TM);
193 cByte, cShort, cInt, cLong, cFloat, cDouble
196 static TypeClass getClass (const Type *T) {
197 switch (T->getTypeID()) {
198 case Type::UByteTyID: case Type::SByteTyID: return cByte;
199 case Type::UShortTyID: case Type::ShortTyID: return cShort;
200 case Type::PointerTyID:
201 case Type::UIntTyID: case Type::IntTyID: return cInt;
202 case Type::ULongTyID: case Type::LongTyID: return cLong;
203 case Type::FloatTyID: return cFloat;
204 case Type::DoubleTyID: return cDouble;
206 assert (0 && "Type of unknown class passed to getClass?");
211 static TypeClass getClassB(const Type *T) {
212 if (T == Type::BoolTy) return cByte;
216 /// copyConstantToRegister - Output the instructions required to put the
217 /// specified constant into the specified register.
219 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
220 MachineBasicBlock::iterator IP,
221 Constant *C, unsigned R) {
222 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
223 switch (CE->getOpcode()) {
224 case Instruction::GetElementPtr:
225 emitGEPOperation(MBB, IP, CE->getOperand(0),
226 CE->op_begin()+1, CE->op_end(), R);
228 case Instruction::Cast:
229 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
232 std::cerr << "Copying this constant expr not yet handled: " << *CE;
235 } else if (isa<UndefValue>(C)) {
236 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
237 if (getClassB (C->getType ()) == cLong)
238 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
242 if (C->getType()->isIntegral ()) {
244 unsigned Class = getClassB (C->getType ());
245 if (Class == cLong) {
246 unsigned TmpReg = makeAnotherReg (Type::IntTy);
247 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
248 // Copy the value into the register pair.
249 // R = top(more-significant) half, R+1 = bottom(less-significant) half
250 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
251 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
253 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
254 Val & 0xffffffffU), R+1);
258 assert(Class <= cInt && "Type not handled yet!");
260 if (C->getType() == Type::BoolTy) {
261 Val = (C == ConstantBool::True);
263 ConstantInt *CI = cast<ConstantInt> (C);
264 Val = CI->getRawValue ();
267 case cByte: Val = (int8_t) Val; break;
268 case cShort: Val = (int16_t) Val; break;
269 case cInt: Val = (int32_t) Val; break;
271 std::cerr << "Offending constant: " << *C << "\n";
272 assert (0 && "Can't copy this kind of constant into register yet");
276 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
277 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
278 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
280 unsigned TmpReg = makeAnotherReg (C->getType ());
281 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
282 .addSImm (((uint32_t) Val) >> 10);
283 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
284 .addSImm (((uint32_t) Val) & 0x03ff);
287 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
288 // We need to spill the constant to memory...
289 MachineConstantPool *CP = F->getConstantPool();
290 unsigned CPI = CP->getConstantPoolIndex(CFP);
291 const Type *Ty = CFP->getType();
292 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
293 unsigned AddrReg = makeAnotherReg (Type::UIntTy);
295 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
296 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
297 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
298 BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
299 .addConstantPoolIndex (CPI);
300 BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
301 } else if (isa<ConstantPointerNull>(C)) {
302 // Copy zero (null pointer) to the register.
303 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
304 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
305 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
306 // that SETHI %reg,global == SETHI %reg,%hi(global) and
307 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
308 unsigned TmpReg = makeAnotherReg (C->getType ());
309 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
310 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
312 std::cerr << "Offending constant: " << *C << "\n";
313 assert (0 && "Can't copy this kind of constant into register yet");
317 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
318 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
319 V8::I3, V8::I4, V8::I5 };
321 // Add IMPLICIT_DEFs of input regs.
323 for (Function::aiterator I = LF->abegin(), E = LF->aend();
324 I != E && ArgNo < 6; ++I, ++ArgNo) {
325 switch (getClassB(I->getType())) {
330 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
334 // Double and Long use register pairs.
335 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
338 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
341 assert (0 && "type not handled");
346 // Copy args out of their incoming hard regs or stack slots into virtual regs.
347 const unsigned *IAREnd = &IncomingArgRegs[6];
348 const unsigned *IAR = &IncomingArgRegs[0];
349 unsigned ArgOffset = 68;
350 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
352 unsigned ArgReg = getReg (A);
353 if (getClassB (A.getType ()) < cLong) {
354 // Get it out of the incoming arg register
355 if (ArgOffset < 92) {
356 assert (IAR != IAREnd
357 && "About to dereference past end of IncomingArgRegs");
358 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
360 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
361 BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
364 } else if (getClassB (A.getType ()) == cFloat) {
365 if (ArgOffset < 92) {
366 // Single-fp args are passed in integer registers; go through
367 // memory to get them out of integer registers and back into fp. (Bleh!)
368 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
369 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
370 assert (IAR != IAREnd
371 && "About to dereference past end of IncomingArgRegs");
372 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
373 BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
375 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
376 BuildMI (BB, V8::LDFri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
379 } else if (getClassB (A.getType ()) == cDouble) {
380 // Double-fp args are passed in pairs of integer registers; go through
381 // memory to get them out of integer registers and back into fp. (Bleh!)
382 // We'd like to 'ldd' these right out of the incoming-args area,
383 // but it might not be 8-byte aligned (e.g., call x(int x, double d)).
384 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
385 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
386 if (ArgOffset < 92 && IAR != IAREnd) {
387 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
389 unsigned TempReg = makeAnotherReg (Type::IntTy);
390 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
391 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
394 if (ArgOffset < 92 && IAR != IAREnd) {
395 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
397 unsigned TempReg = makeAnotherReg (Type::IntTy);
398 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
399 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
402 BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
403 } else if (getClassB (A.getType ()) == cLong) {
404 // do the first half...
405 if (ArgOffset < 92) {
406 assert (IAR != IAREnd
407 && "About to dereference past end of IncomingArgRegs");
408 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
410 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
411 BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
414 // ...then do the second half
415 if (ArgOffset < 92) {
416 assert (IAR != IAREnd
417 && "About to dereference past end of IncomingArgRegs");
418 BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
420 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
421 BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
425 assert (0 && "Unknown class?!");
430 void V8ISel::SelectPHINodes() {
431 const TargetInstrInfo &TII = *TM.getInstrInfo();
432 const Function &LF = *F->getFunction(); // The LLVM function...
433 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
434 const BasicBlock *BB = I;
435 MachineBasicBlock &MBB = *MBBMap[I];
437 // Loop over all of the PHI nodes in the LLVM basic block...
438 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
439 for (BasicBlock::const_iterator I = BB->begin();
440 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
442 // Create a new machine instr PHI node, and insert it.
443 unsigned PHIReg = getReg(*PN);
444 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
445 V8::PHI, PN->getNumOperands(), PHIReg);
447 MachineInstr *LongPhiMI = 0;
448 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
449 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
450 V8::PHI, PN->getNumOperands(), PHIReg+1);
452 // PHIValues - Map of blocks to incoming virtual registers. We use this
453 // so that we only initialize one incoming value for a particular block,
454 // even if the block has multiple entries in the PHI node.
456 std::map<MachineBasicBlock*, unsigned> PHIValues;
458 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
459 MachineBasicBlock *PredMBB = 0;
460 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
461 PE = MBB.pred_end (); PI != PE; ++PI)
462 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
466 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
469 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
470 PHIValues.lower_bound(PredMBB);
472 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
473 // We already inserted an initialization of the register for this
474 // predecessor. Recycle it.
475 ValReg = EntryIt->second;
478 // Get the incoming value into a virtual register.
480 Value *Val = PN->getIncomingValue(i);
482 // If this is a constant or GlobalValue, we may have to insert code
483 // into the basic block to compute it into a virtual register.
484 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
485 isa<GlobalValue>(Val)) {
486 // Simple constants get emitted at the end of the basic block,
487 // before any terminator instructions. We "know" that the code to
488 // move a constant into a register will never clobber any flags.
489 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
491 // Because we don't want to clobber any values which might be in
492 // physical registers with the computation of this constant (which
493 // might be arbitrarily complex if it is a constant expression),
494 // just insert the computation at the top of the basic block.
495 MachineBasicBlock::iterator PI = PredMBB->begin();
497 // Skip over any PHI nodes though!
498 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
501 ValReg = getReg(Val, PredMBB, PI);
504 // Remember that we inserted a value for this PHI for this predecessor
505 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
508 PhiMI->addRegOperand(ValReg);
509 PhiMI->addMachineBasicBlockOperand(PredMBB);
511 LongPhiMI->addRegOperand(ValReg+1);
512 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
516 // Now that we emitted all of the incoming values for the PHI node, make
517 // sure to reposition the InsertPoint after the PHI that we just added.
518 // This is needed because we might have inserted a constant into this
519 // block, right after the PHI's which is before the old insert point!
520 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
526 bool V8ISel::runOnFunction(Function &Fn) {
527 // First pass over the function, lower any unknown intrinsic functions
528 // with the IntrinsicLowering class.
529 LowerUnknownIntrinsicFunctionCalls(Fn);
531 F = &MachineFunction::construct(&Fn, TM);
533 // Create all of the machine basic blocks for the function...
534 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
535 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
539 // Set up a frame object for the return address. This is used by the
540 // llvm.returnaddress & llvm.frameaddress intrinisics.
541 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
543 // Copy incoming arguments off of the stack and out of fixed registers.
544 LoadArgumentsToVirtualRegs(&Fn);
546 // Instruction select everything except PHI nodes
549 // Select the PHI nodes
555 // We always build a machine code representation for the function
559 void V8ISel::visitCastInst(CastInst &I) {
560 Value *Op = I.getOperand(0);
561 unsigned DestReg = getReg(I);
562 MachineBasicBlock::iterator MI = BB->end();
563 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
567 unsigned V8ISel::emitIntegerCast (MachineBasicBlock *BB,
568 MachineBasicBlock::iterator IP, const Type *oldTy,
569 unsigned SrcReg, const Type *newTy,
571 if (oldTy == newTy) {
572 // No-op cast - just emit a copy; assume the reg. allocator will zap it.
573 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg(SrcReg);
576 // Emit left-shift, then right-shift to sign- or zero-extend.
577 unsigned TmpReg = makeAnotherReg (newTy);
578 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
579 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg).addZImm (shiftWidth).addReg(SrcReg);
580 if (newTy->isSigned ()) { // sign-extend with SRA
581 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
582 } else { // zero-extend with SRL
583 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
585 // Return the temp reg. in case this is one half of a cast to long.
589 void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
590 MachineBasicBlock::iterator IP,
591 const Type *oldTy, unsigned SrcReg,
592 const Type *newTy, unsigned DestReg) {
593 unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
594 unsigned oldTyClass = getClassB(oldTy);
595 if (oldTyClass == cFloat) {
596 FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
597 FPAlign = TM.getTargetData().getFloatAlignment();
598 } else { // it's a double
599 FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
600 FPAlign = TM.getTargetData().getDoubleAlignment();
602 unsigned TempReg = makeAnotherReg (oldTy);
603 BuildMI (*BB, IP, FPCastOpcode, 1, TempReg).addReg (SrcReg);
604 int FI = F->getFrameInfo()->CreateStackObject(FPSize, FPAlign);
605 BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
607 unsigned TempReg2 = makeAnotherReg (newTy);
608 BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
609 emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
612 /// emitCastOperation - Common code shared between visitCastInst and constant
613 /// expression cast support.
615 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
616 MachineBasicBlock::iterator IP, Value *Src,
617 const Type *DestTy, unsigned DestReg) {
618 const Type *SrcTy = Src->getType();
619 unsigned SrcClass = getClassB(SrcTy);
620 unsigned DestClass = getClassB(DestTy);
621 unsigned SrcReg = getReg(Src, BB, IP);
623 const Type *oldTy = SrcTy;
624 const Type *newTy = DestTy;
625 unsigned oldTyClass = SrcClass;
626 unsigned newTyClass = DestClass;
628 if (oldTyClass < cLong && newTyClass < cLong) {
629 emitIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
630 } else switch (newTyClass) {
634 switch (oldTyClass) {
636 // Treat it like a cast from the lower half of the value.
637 emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
641 emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
643 default: goto not_yet;
648 switch (oldTyClass) {
649 case cLong: goto not_yet;
651 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
654 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
657 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
658 // cast integer type to float. Store it to a stack slot and then load
659 // it using ldf into a floating point register. then do fitos.
660 unsigned TmpReg = makeAnotherReg (newTy);
661 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
662 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
664 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
665 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
672 switch (oldTyClass) {
673 case cLong: goto not_yet;
675 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
677 case cDouble: // use double move pseudo-instr
678 BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
681 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
682 unsigned TmpReg = makeAnotherReg (newTy);
683 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
684 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
686 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
687 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
694 switch (oldTyClass) {
698 // Cast to (u)int in the bottom half, and sign(zero) extend in the top
700 const Type *OldHalfTy = oldTy->isSigned() ? Type::IntTy : Type::UIntTy;
701 const Type *NewHalfTy = newTy->isSigned() ? Type::IntTy : Type::UIntTy;
702 unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
703 NewHalfTy, DestReg+1);
704 if (newTy->isSigned ()) {
705 BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
708 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
714 // Just copy both halves.
715 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
716 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
719 default: goto not_yet;
723 default: goto not_yet;
727 std::cerr << "Sorry, cast still unsupported: SrcTy = " << *SrcTy
728 << ", DestTy = " << *DestTy << "\n";
732 void V8ISel::visitLoadInst(LoadInst &I) {
733 unsigned DestReg = getReg (I);
734 unsigned PtrReg = getReg (I.getOperand (0));
735 switch (getClassB (I.getType ())) {
737 if (I.getType ()->isSigned ())
738 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
740 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
743 if (I.getType ()->isSigned ())
744 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
746 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
749 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
752 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
753 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
756 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
759 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
762 std::cerr << "Load instruction not handled: " << I;
768 void V8ISel::visitStoreInst(StoreInst &I) {
769 Value *SrcVal = I.getOperand (0);
770 unsigned SrcReg = getReg (SrcVal);
771 unsigned PtrReg = getReg (I.getOperand (1));
772 switch (getClassB (SrcVal->getType ())) {
774 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
777 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
780 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
783 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
784 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
787 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
790 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
793 std::cerr << "Store instruction not handled: " << I;
799 void V8ISel::visitCallInst(CallInst &I) {
800 MachineInstr *TheCall;
801 // Is it an intrinsic function call?
802 if (Function *F = I.getCalledFunction()) {
803 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
804 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
809 unsigned extraStack = 0;
810 // How much extra call stack will we need?
811 for (unsigned i = 7; i < I.getNumOperands (); ++i) {
812 switch (getClassB (I.getOperand (i)->getType ())) {
813 case cLong: extraStack += 8; break;
814 case cFloat: extraStack += 4; break;
815 case cDouble: extraStack += 8; break;
816 default: extraStack += 4; break;
819 // Round up extra stack size to the nearest doubleword.
820 if (extraStack) { extraStack = (extraStack + 7) & ~7; }
823 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
825 const unsigned *OAREnd = &OutgoingArgRegs[6];
826 const unsigned *OAR = &OutgoingArgRegs[0];
827 unsigned ArgOffset = 68;
828 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKDOWN, 1).addImm (extraStack);
829 for (unsigned i = 1; i < I.getNumOperands (); ++i) {
830 unsigned ArgReg = getReg (I.getOperand (i));
831 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
832 // Schlep it over into the incoming arg register
833 if (ArgOffset < 92) {
834 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
835 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
837 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
840 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
841 if (ArgOffset < 92) {
842 // Single-fp args are passed in integer registers; go through
843 // memory to get them out of FP registers. (Bleh!)
844 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
845 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
846 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
847 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
848 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
850 BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
853 } else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
854 // Double-fp args are passed in pairs of integer registers; go through
855 // memory to get them out of FP registers. (Bleh!)
856 // We'd like to 'std' these right onto the outgoing-args area, but it might
857 // not be 8-byte aligned (e.g., call x(int x, double d)). sigh.
858 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
859 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
860 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
861 if (ArgOffset < 92 && OAR != OAREnd) {
862 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
863 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
865 unsigned TempReg = makeAnotherReg (Type::IntTy);
866 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
867 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
870 if (ArgOffset < 92 && OAR != OAREnd) {
871 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
872 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
874 unsigned TempReg = makeAnotherReg (Type::IntTy);
875 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
876 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
879 } else if (getClassB (I.getOperand (i)->getType ()) == cLong) {
880 // do the first half...
881 if (ArgOffset < 92) {
882 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
883 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
885 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
888 // ...then do the second half
889 if (ArgOffset < 92) {
890 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
891 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
893 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg+1);
897 assert (0 && "Unknown class?!");
901 // Emit call instruction
902 if (Function *F = I.getCalledFunction ()) {
903 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
904 } else { // Emit an indirect call...
905 unsigned Reg = getReg (I.getCalledValue ());
906 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
909 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKUP, 1).addImm (extraStack);
911 // Deal w/ return value: schlep it over into the destination register
912 if (I.getType () == Type::VoidTy)
914 unsigned DestReg = getReg (I);
915 switch (getClassB (I.getType ())) {
919 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
922 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
925 BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
928 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
929 BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
932 std::cerr << "Return type of call instruction not handled: " << I;
937 void V8ISel::visitReturnInst(ReturnInst &I) {
938 if (I.getNumOperands () == 1) {
939 unsigned RetValReg = getReg (I.getOperand (0));
940 switch (getClassB (I.getOperand (0)->getType ())) {
944 // Schlep it over into i0 (where it will become o0 after restore).
945 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
948 BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
951 BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
954 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
955 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
958 std::cerr << "Return instruction of this type not handled: " << I;
963 // Just emit a 'retl' instruction to return.
964 BuildMI(BB, V8::RETL, 0);
968 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
969 Function::iterator I = BB; ++I; // Get iterator to next block
970 return I != BB->getParent()->end() ? &*I : 0;
973 /// visitBranchInst - Handles conditional and unconditional branches.
975 void V8ISel::visitBranchInst(BranchInst &I) {
976 BasicBlock *takenSucc = I.getSuccessor (0);
977 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
978 BB->addSuccessor (takenSuccMBB);
979 if (I.isConditional()) { // conditional branch
980 BasicBlock *notTakenSucc = I.getSuccessor (1);
981 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
982 BB->addSuccessor (notTakenSuccMBB);
984 // CondReg=(<condition>);
985 // If (CondReg==0) goto notTakenSuccMBB;
986 unsigned CondReg = getReg (I.getCondition ());
987 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
988 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
990 // goto takenSuccMBB;
991 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
994 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
995 /// constant expression GEP support.
997 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
998 MachineBasicBlock::iterator IP,
999 Value *Src, User::op_iterator IdxBegin,
1000 User::op_iterator IdxEnd, unsigned TargetReg) {
1001 const TargetData &TD = TM.getTargetData ();
1002 const Type *Ty = Src->getType ();
1003 unsigned basePtrReg = getReg (Src, MBB, IP);
1005 // GEPs have zero or more indices; we must perform a struct access
1006 // or array access for each one.
1007 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
1010 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
1011 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
1012 // It's a struct access. idx is the index into the structure,
1013 // which names the field. Use the TargetData structure to
1014 // pick out what the layout of the structure is in memory.
1015 // Use the (constant) structure index's value to find the
1016 // right byte offset from the StructLayout class's list of
1017 // structure member offsets.
1018 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
1019 unsigned memberOffset =
1020 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
1021 // Emit an ADD to add memberOffset to the basePtr.
1022 BuildMI (*MBB, IP, V8::ADDri, 2,
1023 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
1024 // The next type is the member of the structure selected by the
1026 Ty = StTy->getElementType (fieldIndex);
1027 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
1028 // It's an array or pointer access: [ArraySize x ElementType].
1029 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
1030 // must find the size of the pointed-to type (Not coincidentally, the next
1031 // type is the type of the elements in the array).
1032 Ty = SqTy->getElementType ();
1033 unsigned elementSize = TD.getTypeSize (Ty);
1034 unsigned idxReg = getReg (idx, MBB, IP);
1035 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
1036 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
1037 copyConstantToRegister (MBB, IP,
1038 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
1039 // Emit a SMUL to multiply the register holding the index by
1040 // elementSize, putting the result in OffsetReg.
1041 BuildMI (*MBB, IP, V8::SMULrr, 2,
1042 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
1043 // Emit an ADD to add OffsetReg to the basePtr.
1044 BuildMI (*MBB, IP, V8::ADDrr, 2,
1045 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
1047 basePtrReg = nextBasePtrReg;
1049 // After we have processed all the indices, the result is left in
1050 // basePtrReg. Move it to the register where we were expected to
1052 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
1055 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
1056 unsigned outputReg = getReg (I);
1057 emitGEPOperation (BB, BB->end (), I.getOperand (0),
1058 I.op_begin ()+1, I.op_end (), outputReg);
1062 void V8ISel::visitBinaryOperator (Instruction &I) {
1063 unsigned DestReg = getReg (I);
1064 unsigned Op0Reg = getReg (I.getOperand (0));
1065 unsigned Op1Reg = getReg (I.getOperand (1));
1067 unsigned Class = getClassB (I.getType());
1068 unsigned OpCase = ~0;
1070 if (Class > cLong) {
1071 switch (I.getOpcode ()) {
1072 case Instruction::Add: OpCase = 0; break;
1073 case Instruction::Sub: OpCase = 1; break;
1074 case Instruction::Mul: OpCase = 2; break;
1075 case Instruction::Div: OpCase = 3; break;
1076 default: visitInstruction (I); return;
1078 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
1079 V8::FSUBS, V8::FSUBD,
1080 V8::FMULS, V8::FMULD,
1081 V8::FDIVS, V8::FDIVD };
1082 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
1083 .addReg (Op0Reg).addReg (Op1Reg);
1087 unsigned ResultReg = DestReg;
1088 if (Class != cInt && Class != cLong)
1089 ResultReg = makeAnotherReg (I.getType ());
1091 if (Class == cLong) {
1092 DEBUG (std::cerr << "Class = cLong\n");
1093 DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
1094 DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
1095 DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
1096 DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
1099 // FIXME: support long, ulong.
1100 switch (I.getOpcode ()) {
1101 case Instruction::Add: OpCase = 0; break;
1102 case Instruction::Sub: OpCase = 1; break;
1103 case Instruction::Mul: OpCase = 2; break;
1104 case Instruction::And: OpCase = 3; break;
1105 case Instruction::Or: OpCase = 4; break;
1106 case Instruction::Xor: OpCase = 5; break;
1107 case Instruction::Shl: OpCase = 6; break;
1108 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
1110 case Instruction::Div:
1111 case Instruction::Rem: {
1112 unsigned Dest = ResultReg;
1113 if (I.getOpcode() == Instruction::Rem)
1114 Dest = makeAnotherReg(I.getType());
1116 // FIXME: this is probably only right for 32 bit operands.
1117 if (I.getType ()->isSigned()) {
1118 unsigned Tmp = makeAnotherReg (I.getType ());
1119 // Sign extend into the Y register
1120 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
1121 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
1122 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1124 // Zero extend into the Y register, ie, just set it to zero
1125 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
1126 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1129 if (I.getOpcode() == Instruction::Rem) {
1130 unsigned Tmp = makeAnotherReg (I.getType ());
1131 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
1132 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
1137 visitInstruction (I);
1141 static const unsigned Opcodes[] = {
1142 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
1143 V8::SLLrr, V8::SRLrr, V8::SRArr
1145 if (OpCase != ~0U) {
1146 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1149 switch (getClassB (I.getType ())) {
1151 if (I.getType ()->isSigned ()) { // add byte
1152 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
1153 } else { // add ubyte
1154 unsigned TmpReg = makeAnotherReg (I.getType ());
1155 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
1156 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
1160 if (I.getType ()->isSigned ()) { // add short
1161 unsigned TmpReg = makeAnotherReg (I.getType ());
1162 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1163 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
1164 } else { // add ushort
1165 unsigned TmpReg = makeAnotherReg (I.getType ());
1166 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1167 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
1171 // Nothing to do here.
1174 // Only support and, or, xor.
1175 if (OpCase < 3 || OpCase > 5) {
1176 visitInstruction (I);
1179 // Do the other half of the value:
1180 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
1184 visitInstruction (I);
1188 void V8ISel::visitSetCondInst(SetCondInst &I) {
1189 unsigned Op0Reg = getReg (I.getOperand (0));
1190 unsigned Op1Reg = getReg (I.getOperand (1));
1191 unsigned DestReg = getReg (I);
1192 const Type *Ty = I.getOperand (0)->getType ();
1194 // Compare the two values.
1195 assert (getClass (Ty) != cLong && "can't setcc on longs yet");
1196 if (getClass (Ty) < cLong) {
1197 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1198 } else if (getClass (Ty) == cFloat) {
1199 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1200 } else if (getClass (Ty) == cDouble) {
1201 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1205 switch (I.getOpcode()) {
1206 default: assert(0 && "Unknown setcc instruction!");
1207 case Instruction::SetEQ: BranchIdx = 0; break;
1208 case Instruction::SetNE: BranchIdx = 1; break;
1209 case Instruction::SetLT: BranchIdx = 2; break;
1210 case Instruction::SetGT: BranchIdx = 3; break;
1211 case Instruction::SetLE: BranchIdx = 4; break;
1212 case Instruction::SetGE: BranchIdx = 5; break;
1214 unsigned Column = 0;
1215 if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
1216 if (Ty->isFloatingPoint()) Column = 2;
1217 static unsigned OpcodeTab[3*6] = {
1219 // unsigned signed fp
1220 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1221 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1222 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1223 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1224 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1225 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1227 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1229 MachineBasicBlock *thisMBB = BB;
1230 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1233 // subcc %reg0, %reg1, %g0
1237 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1238 // if we could insert other, non-terminator instructions after the
1239 // bCC. But MBB->getFirstTerminator() can't understand this.
1240 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
1241 F->getBasicBlockList ().push_back (copy1MBB);
1242 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
1243 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1244 F->getBasicBlockList ().push_back (copy0MBB);
1245 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
1246 // Update machine-CFG edges
1247 BB->addSuccessor (copy1MBB);
1248 BB->addSuccessor (copy0MBB);
1251 // %FalseValue = or %G0, 0
1254 unsigned FalseValue = makeAnotherReg (I.getType ());
1255 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
1256 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1257 F->getBasicBlockList ().push_back (sinkMBB);
1258 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1259 // Update machine-CFG edges
1260 BB->addSuccessor (sinkMBB);
1262 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1263 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
1264 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1265 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1268 // %TrueValue = or %G0, 1
1271 unsigned TrueValue = makeAnotherReg (I.getType ());
1272 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1273 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1274 // Update machine-CFG edges
1275 BB->addSuccessor (sinkMBB);
1278 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1281 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1282 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1285 void V8ISel::visitAllocaInst(AllocaInst &I) {
1286 // Find the data size of the alloca inst's getAllocatedType.
1287 const Type *Ty = I.getAllocatedType();
1288 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1290 unsigned ArraySizeReg = getReg (I.getArraySize ());
1291 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1292 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1293 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1294 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1296 // StackAdjReg = (ArraySize * TySize) rounded up to nearest doubleword boundary
1297 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1299 // Round up TmpReg1 to nearest doubleword boundary:
1300 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1301 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1303 // Subtract size from stack pointer, thereby allocating some space.
1304 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1306 // Put a pointer to the space into the result register, by copying
1307 // the stack pointer.
1308 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1310 // Inform the Frame Information that we have just allocated a variable-sized
1312 F->getFrameInfo()->CreateVariableSizedObject();
1315 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1316 /// function, lowering any calls to unknown intrinsic functions into the
1317 /// equivalent LLVM code.
1318 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1319 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1320 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1321 if (CallInst *CI = dyn_cast<CallInst>(I++))
1322 if (Function *F = CI->getCalledFunction())
1323 switch (F->getIntrinsicID()) {
1324 case Intrinsic::not_intrinsic: break;
1326 // All other intrinsic calls we must lower.
1327 Instruction *Before = CI->getPrev();
1328 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1329 if (Before) { // Move iterator to instruction after call
1338 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1341 std::cerr << "Sorry, unknown intrinsic function call:\n" << CI; abort ();
1343 case Intrinsic::vastart:
1344 std::cerr << "Sorry, va_start intrinsic still unsupported:\n" << CI; abort ();
1346 case Intrinsic::vaend:
1347 std::cerr << "Sorry, va_end intrinsic still unsupported:\n" << CI; abort ();
1349 case Intrinsic::vacopy:
1350 std::cerr << "Sorry, va_copy intrinsic still unsupported:\n" << CI; abort ();