1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
33 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
35 MachineFunction *F; // The function we are compiling into
36 MachineBasicBlock *BB; // The current MBB we are compiling
38 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
40 // MBBMap - Mapping between LLVM BB -> Machine BB
41 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
43 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
45 /// runOnFunction - Top level implementation of instruction selection for
46 /// the entire function.
48 bool runOnFunction(Function &Fn);
50 virtual const char *getPassName() const {
51 return "SparcV8 Simple Instruction Selection";
54 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
55 /// constant expression GEP support.
57 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
58 Value *Src, User::op_iterator IdxBegin,
59 User::op_iterator IdxEnd, unsigned TargetReg);
61 /// emitCastOperation - Common code shared between visitCastInst and
62 /// constant expression cast support.
64 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
65 Value *Src, const Type *DestTy, unsigned TargetReg);
67 /// emitIntegerCast, emitFPToIntegerCast - Helper methods for
68 /// emitCastOperation.
70 void emitIntegerCast (MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
71 const Type *oldTy, unsigned SrcReg, const Type *newTy,
73 void emitFPToIntegerCast (MachineBasicBlock *BB,
74 MachineBasicBlock::iterator IP, const Type *oldTy,
75 unsigned SrcReg, const Type *newTy,
78 /// visitBasicBlock - This method is called when we are visiting a new basic
79 /// block. This simply creates a new MachineBasicBlock to emit code into
80 /// and adds it to the current MachineFunction. Subsequent visit* for
81 /// instructions will be invoked for all instructions in the basic block.
83 void visitBasicBlock(BasicBlock &LLVM_BB) {
84 BB = MBBMap[&LLVM_BB];
87 void visitBinaryOperator(Instruction &I);
88 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
89 void visitSetCondInst(SetCondInst &I);
90 void visitCallInst(CallInst &I);
91 void visitReturnInst(ReturnInst &I);
92 void visitBranchInst(BranchInst &I);
93 void visitUnreachableInst(UnreachableInst &I) {}
94 void visitCastInst(CastInst &I);
95 void visitLoadInst(LoadInst &I);
96 void visitStoreInst(StoreInst &I);
97 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
98 void visitGetElementPtrInst(GetElementPtrInst &I);
99 void visitAllocaInst(AllocaInst &I);
101 void visitInstruction(Instruction &I) {
102 std::cerr << "Unhandled instruction: " << I;
106 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
107 /// function, lowering any calls to unknown intrinsic functions into the
108 /// equivalent LLVM code.
109 void LowerUnknownIntrinsicFunctionCalls(Function &F);
110 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
112 void LoadArgumentsToVirtualRegs(Function *F);
114 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
115 /// because we have to generate our sources into the source basic blocks,
116 /// not the current one.
118 void SelectPHINodes();
120 /// copyConstantToRegister - Output the instructions required to put the
121 /// specified constant into the specified register.
123 void copyConstantToRegister(MachineBasicBlock *MBB,
124 MachineBasicBlock::iterator IP,
125 Constant *C, unsigned R);
127 /// makeAnotherReg - This method returns the next register number we haven't
130 /// Long values are handled somewhat specially. They are always allocated
131 /// as pairs of 32 bit integer values. The register number returned is the
132 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
133 /// of the long value.
135 unsigned makeAnotherReg(const Type *Ty) {
136 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
137 "Current target doesn't have SparcV8 reg info??");
138 const SparcV8RegisterInfo *MRI =
139 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
140 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
141 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
142 // Create the lower part
143 F->getSSARegMap()->createVirtualRegister(RC);
144 // Create the upper part.
145 return F->getSSARegMap()->createVirtualRegister(RC)-1;
148 // Add the mapping of regnumber => reg class to MachineFunction
149 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
150 return F->getSSARegMap()->createVirtualRegister(RC);
153 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
154 unsigned getReg(Value *V) {
155 // Just append to the end of the current bb.
156 MachineBasicBlock::iterator It = BB->end();
157 return getReg(V, BB, It);
159 unsigned getReg(Value *V, MachineBasicBlock *MBB,
160 MachineBasicBlock::iterator IPt) {
161 unsigned &Reg = RegMap[V];
163 Reg = makeAnotherReg(V->getType());
166 // If this operand is a constant, emit the code to copy the constant into
167 // the register here...
169 if (Constant *C = dyn_cast<Constant>(V)) {
170 copyConstantToRegister(MBB, IPt, C, Reg);
171 RegMap.erase(V); // Assign a new name to this constant if ref'd again
172 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
173 // Move the address of the global into the register
174 unsigned TmpReg = makeAnotherReg(V->getType());
175 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
176 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
177 .addGlobalAddress (GV);
178 RegMap.erase(V); // Assign a new name to this address if ref'd again
187 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
188 return new V8ISel(TM);
192 cByte, cShort, cInt, cLong, cFloat, cDouble
195 static TypeClass getClass (const Type *T) {
196 switch (T->getTypeID()) {
197 case Type::UByteTyID: case Type::SByteTyID: return cByte;
198 case Type::UShortTyID: case Type::ShortTyID: return cShort;
199 case Type::PointerTyID:
200 case Type::UIntTyID: case Type::IntTyID: return cInt;
201 case Type::ULongTyID: case Type::LongTyID: return cLong;
202 case Type::FloatTyID: return cFloat;
203 case Type::DoubleTyID: return cDouble;
205 assert (0 && "Type of unknown class passed to getClass?");
210 static TypeClass getClassB(const Type *T) {
211 if (T == Type::BoolTy) return cByte;
215 /// copyConstantToRegister - Output the instructions required to put the
216 /// specified constant into the specified register.
218 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
219 MachineBasicBlock::iterator IP,
220 Constant *C, unsigned R) {
221 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
222 switch (CE->getOpcode()) {
223 case Instruction::GetElementPtr:
224 emitGEPOperation(MBB, IP, CE->getOperand(0),
225 CE->op_begin()+1, CE->op_end(), R);
227 case Instruction::Cast:
228 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
231 std::cerr << "Copying this constant expr not yet handled: " << *CE;
234 } else if (isa<UndefValue>(C)) {
235 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
236 if (getClassB (C->getType ()) == cLong)
237 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
241 if (C->getType()->isIntegral ()) {
243 unsigned Class = getClassB (C->getType ());
244 if (Class == cLong) {
245 unsigned TmpReg = makeAnotherReg (Type::IntTy);
246 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
247 // Copy the value into the register pair.
248 // R = top(more-significant) half, R+1 = bottom(less-significant) half
249 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
250 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
252 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
253 Val & 0xffffffffU), R+1);
257 assert(Class <= cInt && "Type not handled yet!");
259 if (C->getType() == Type::BoolTy) {
260 Val = (C == ConstantBool::True);
262 ConstantInt *CI = cast<ConstantInt> (C);
263 Val = CI->getRawValue ();
266 case cByte: Val = (int8_t) Val; break;
267 case cShort: Val = (int16_t) Val; break;
268 case cInt: Val = (int32_t) Val; break;
270 std::cerr << "Offending constant: " << *C << "\n";
271 assert (0 && "Can't copy this kind of constant into register yet");
275 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
276 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
277 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
279 unsigned TmpReg = makeAnotherReg (C->getType ());
280 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
281 .addSImm (((uint32_t) Val) >> 10);
282 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
283 .addSImm (((uint32_t) Val) & 0x03ff);
286 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
287 // We need to spill the constant to memory...
288 MachineConstantPool *CP = F->getConstantPool();
289 unsigned CPI = CP->getConstantPoolIndex(CFP);
290 const Type *Ty = CFP->getType();
291 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
292 unsigned AddrReg = makeAnotherReg (Type::UIntTy);
294 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
295 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
296 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
297 BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
298 .addConstantPoolIndex (CPI);
299 BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
300 } else if (isa<ConstantPointerNull>(C)) {
301 // Copy zero (null pointer) to the register.
302 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
303 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
304 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
305 // that SETHI %reg,global == SETHI %reg,%hi(global) and
306 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
307 unsigned TmpReg = makeAnotherReg (C->getType ());
308 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
309 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
311 std::cerr << "Offending constant: " << *C << "\n";
312 assert (0 && "Can't copy this kind of constant into register yet");
316 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
318 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
319 V8::I3, V8::I4, V8::I5 };
320 // Add IMPLICIT_DEFs of input regs.
322 for (Function::aiterator I = LF->abegin(), E = LF->aend();
323 I != E && ArgOffset < 6; ++I, ++ArgOffset) {
324 unsigned Reg = getReg(*I);
325 switch (getClassB(I->getType())) {
330 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
334 // Double and Long use register pairs.
335 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
338 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
341 assert (0 && "type not handled");
347 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E;
349 unsigned Reg = getReg(*I);
352 switch (getClassB(I->getType())) {
356 BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
357 .addReg (IncomingArgRegs[ArgOffset]);
360 // Single-fp args are passed in integer registers; go through
361 // memory to get them into FP registers. (Bleh!)
362 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
363 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
364 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
365 .addReg (IncomingArgRegs[ArgOffset]);
366 BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
370 // Double-fp args are passed in pairs of integer registers; go through
371 // memory to get them into FP registers. (Double bleh!)
372 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
373 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
374 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
375 .addReg (IncomingArgRegs[ArgOffset]);
377 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4)
378 .addReg (IncomingArgRegs[ArgOffset]);
379 BuildMI (BB, V8::LDDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
383 // FIXME: handle cLong
384 assert (0 && "64-bit int (long/ulong) function args not handled");
390 switch (getClassB(I->getType())) {
394 int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
395 BuildMI (BB, V8::LD, 2, Reg).addFrameIndex (FI).addSImm(0);
399 int FI = F->getFrameInfo()->CreateFixedObject(4, 68 + (4 * ArgOffset));
400 BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
404 int FI = F->getFrameInfo()->CreateFixedObject(8, 68 + (4 * ArgOffset));
405 BuildMI (BB, V8::LDDFri, 2, Reg).addFrameIndex (FI).addSImm(0);
409 // FIXME: handle cLong
410 assert (0 && "64-bit integer (long/ulong) function args not handled");
418 void V8ISel::SelectPHINodes() {
419 const TargetInstrInfo &TII = *TM.getInstrInfo();
420 const Function &LF = *F->getFunction(); // The LLVM function...
421 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
422 const BasicBlock *BB = I;
423 MachineBasicBlock &MBB = *MBBMap[I];
425 // Loop over all of the PHI nodes in the LLVM basic block...
426 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
427 for (BasicBlock::const_iterator I = BB->begin();
428 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
430 // Create a new machine instr PHI node, and insert it.
431 unsigned PHIReg = getReg(*PN);
432 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
433 V8::PHI, PN->getNumOperands(), PHIReg);
435 MachineInstr *LongPhiMI = 0;
436 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
437 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
438 V8::PHI, PN->getNumOperands(), PHIReg+1);
440 // PHIValues - Map of blocks to incoming virtual registers. We use this
441 // so that we only initialize one incoming value for a particular block,
442 // even if the block has multiple entries in the PHI node.
444 std::map<MachineBasicBlock*, unsigned> PHIValues;
446 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
447 MachineBasicBlock *PredMBB = 0;
448 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
449 PE = MBB.pred_end (); PI != PE; ++PI)
450 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
454 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
457 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
458 PHIValues.lower_bound(PredMBB);
460 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
461 // We already inserted an initialization of the register for this
462 // predecessor. Recycle it.
463 ValReg = EntryIt->second;
466 // Get the incoming value into a virtual register.
468 Value *Val = PN->getIncomingValue(i);
470 // If this is a constant or GlobalValue, we may have to insert code
471 // into the basic block to compute it into a virtual register.
472 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
473 isa<GlobalValue>(Val)) {
474 // Simple constants get emitted at the end of the basic block,
475 // before any terminator instructions. We "know" that the code to
476 // move a constant into a register will never clobber any flags.
477 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
479 // Because we don't want to clobber any values which might be in
480 // physical registers with the computation of this constant (which
481 // might be arbitrarily complex if it is a constant expression),
482 // just insert the computation at the top of the basic block.
483 MachineBasicBlock::iterator PI = PredMBB->begin();
485 // Skip over any PHI nodes though!
486 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
489 ValReg = getReg(Val, PredMBB, PI);
492 // Remember that we inserted a value for this PHI for this predecessor
493 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
496 PhiMI->addRegOperand(ValReg);
497 PhiMI->addMachineBasicBlockOperand(PredMBB);
499 LongPhiMI->addRegOperand(ValReg+1);
500 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
504 // Now that we emitted all of the incoming values for the PHI node, make
505 // sure to reposition the InsertPoint after the PHI that we just added.
506 // This is needed because we might have inserted a constant into this
507 // block, right after the PHI's which is before the old insert point!
508 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
514 bool V8ISel::runOnFunction(Function &Fn) {
515 // First pass over the function, lower any unknown intrinsic functions
516 // with the IntrinsicLowering class.
517 LowerUnknownIntrinsicFunctionCalls(Fn);
519 F = &MachineFunction::construct(&Fn, TM);
521 // Create all of the machine basic blocks for the function...
522 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
523 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
527 // Set up a frame object for the return address. This is used by the
528 // llvm.returnaddress & llvm.frameaddress intrinisics.
529 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
531 // Copy incoming arguments off of the stack and out of fixed registers.
532 LoadArgumentsToVirtualRegs(&Fn);
534 // Instruction select everything except PHI nodes
537 // Select the PHI nodes
543 // We always build a machine code representation for the function
547 void V8ISel::visitCastInst(CastInst &I) {
548 Value *Op = I.getOperand(0);
549 unsigned DestReg = getReg(I);
550 MachineBasicBlock::iterator MI = BB->end();
551 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
555 void V8ISel::emitIntegerCast (MachineBasicBlock *BB,
556 MachineBasicBlock::iterator IP, const Type *oldTy,
557 unsigned SrcReg, const Type *newTy,
559 if (oldTy == newTy) {
560 // No-op cast - just emit a copy; assume the reg. allocator will zap it.
561 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg(SrcReg);
564 // Emit left-shift, then right-shift to sign- or zero-extend.
565 unsigned TmpReg = makeAnotherReg (newTy);
566 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
567 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg).addZImm (shiftWidth).addReg(SrcReg);
568 if (newTy->isSigned ()) { // sign-extend with SRA
569 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
570 } else { // zero-extend with SRL
571 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
575 void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
576 MachineBasicBlock::iterator IP,
577 const Type *oldTy, unsigned SrcReg,
578 const Type *newTy, unsigned DestReg) {
579 unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
580 unsigned oldTyClass = getClassB(oldTy);
581 if (oldTyClass == cFloat) {
582 FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
583 FPAlign = TM.getTargetData().getFloatAlignment();
584 } else { // it's a double
585 FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
586 FPAlign = TM.getTargetData().getDoubleAlignment();
588 unsigned TempReg = makeAnotherReg (oldTy);
589 BuildMI (*BB, IP, FPCastOpcode, 1, TempReg).addReg (SrcReg);
590 int FI = F->getFrameInfo()->CreateStackObject(FPSize, FPAlign);
591 BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
593 unsigned TempReg2 = makeAnotherReg (newTy);
594 BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
595 emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
598 /// emitCastOperation - Common code shared between visitCastInst and constant
599 /// expression cast support.
601 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
602 MachineBasicBlock::iterator IP, Value *Src,
603 const Type *DestTy, unsigned DestReg) {
604 const Type *SrcTy = Src->getType();
605 unsigned SrcClass = getClassB(SrcTy);
606 unsigned DestClass = getClassB(DestTy);
607 unsigned SrcReg = getReg(Src, BB, IP);
609 const Type *oldTy = SrcTy;
610 const Type *newTy = DestTy;
611 unsigned oldTyClass = SrcClass;
612 unsigned newTyClass = DestClass;
614 if (oldTyClass < cLong && newTyClass < cLong) {
615 emitIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
616 } else switch (newTyClass) {
620 switch (oldTyClass) {
623 emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
625 default: goto not_yet;
630 switch (oldTyClass) {
631 case cLong: goto not_yet;
633 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
636 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
639 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
640 // cast integer type to float. Store it to a stack slot and then load
641 // it using ldf into a floating point register. then do fitos.
642 unsigned TmpReg = makeAnotherReg (newTy);
643 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
644 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
646 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
647 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
654 switch (oldTyClass) {
655 case cLong: goto not_yet;
657 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
659 case cDouble: // use double move pseudo-instr
660 BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
663 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
664 unsigned TmpReg = makeAnotherReg (newTy);
665 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
666 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
668 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
669 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
676 switch (oldTyClass) {
679 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
680 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
683 default: goto not_yet;
687 default: goto not_yet;
691 std::cerr << "Sorry, cast still unsupported: SrcTy = " << *SrcTy
692 << ", DestTy = " << *DestTy << "\n";
696 void V8ISel::visitLoadInst(LoadInst &I) {
697 unsigned DestReg = getReg (I);
698 unsigned PtrReg = getReg (I.getOperand (0));
699 switch (getClassB (I.getType ())) {
701 if (I.getType ()->isSigned ())
702 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
704 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
707 if (I.getType ()->isSigned ())
708 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
710 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
713 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
716 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
717 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
720 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
723 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
726 std::cerr << "Load instruction not handled: " << I;
732 void V8ISel::visitStoreInst(StoreInst &I) {
733 Value *SrcVal = I.getOperand (0);
734 unsigned SrcReg = getReg (SrcVal);
735 unsigned PtrReg = getReg (I.getOperand (1));
736 switch (getClassB (SrcVal->getType ())) {
738 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
741 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
744 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
747 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
748 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
751 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
754 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
757 std::cerr << "Store instruction not handled: " << I;
763 void V8ISel::visitCallInst(CallInst &I) {
764 MachineInstr *TheCall;
765 // Is it an intrinsic function call?
766 if (Function *F = I.getCalledFunction()) {
767 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
768 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
773 unsigned extraStack = 0;
774 // How much extra call stack will we need?
775 for (unsigned i = 7; i < I.getNumOperands (); ++i) {
776 switch (getClassB (I.getOperand (i)->getType ())) {
777 case cLong: extraStack += 8; break;
778 case cFloat: extraStack += 4; break;
779 case cDouble: extraStack += 8; break;
780 default: extraStack += 4; break;
785 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
787 for (unsigned i = 1; i < I.getNumOperands (); ++i) {
788 unsigned ArgReg = getReg (I.getOperand (i));
790 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
791 // Schlep it over into the incoming arg register
792 BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0)
794 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
795 // Single-fp args are passed in integer registers; go through
796 // memory to get them out of FP registers. (Bleh!)
797 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
798 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
799 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0)
801 BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
803 } else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
804 // Double-fp args are passed in pairs of integer registers; go through
805 // memory to get them out of FP registers. (Bleh!)
806 assert (i <= 5 && "Can't deal with double-fp args past #5 yet");
807 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
808 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
809 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
811 BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
813 BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i]).addFrameIndex (FI)
816 assert (0 && "64-bit (double, long, etc.) 'call' opnds not handled");
819 if (i == 7 && extraStack)
820 BuildMI (BB, V8::ADJCALLSTACKDOWN, 1).addImm (extraStack);
821 // Store arg into designated outgoing-arg stack slot
822 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
823 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (64+4*i)
826 assert (0 && "can't push this kind of excess arg on stack yet");
831 // Emit call instruction
832 if (Function *F = I.getCalledFunction ()) {
833 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
834 } else { // Emit an indirect call...
835 unsigned Reg = getReg (I.getCalledValue ());
836 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
839 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKUP, 1).addImm (extraStack);
841 // Deal w/ return value: schlep it over into the destination register
842 if (I.getType () == Type::VoidTy)
844 unsigned DestReg = getReg (I);
845 switch (getClassB (I.getType ())) {
849 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
852 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
855 BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
858 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
859 BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
862 std::cerr << "Return type of call instruction not handled: " << I;
867 void V8ISel::visitReturnInst(ReturnInst &I) {
868 if (I.getNumOperands () == 1) {
869 unsigned RetValReg = getReg (I.getOperand (0));
870 switch (getClassB (I.getOperand (0)->getType ())) {
874 // Schlep it over into i0 (where it will become o0 after restore).
875 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
878 BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
881 BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
884 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
885 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
888 std::cerr << "Return instruction of this type not handled: " << I;
893 // Just emit a 'retl' instruction to return.
894 BuildMI(BB, V8::RETL, 0);
898 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
899 Function::iterator I = BB; ++I; // Get iterator to next block
900 return I != BB->getParent()->end() ? &*I : 0;
903 /// visitBranchInst - Handles conditional and unconditional branches.
905 void V8ISel::visitBranchInst(BranchInst &I) {
906 BasicBlock *takenSucc = I.getSuccessor (0);
907 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
908 BB->addSuccessor (takenSuccMBB);
909 if (I.isConditional()) { // conditional branch
910 BasicBlock *notTakenSucc = I.getSuccessor (1);
911 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
912 BB->addSuccessor (notTakenSuccMBB);
914 // CondReg=(<condition>);
915 // If (CondReg==0) goto notTakenSuccMBB;
916 unsigned CondReg = getReg (I.getCondition ());
917 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
918 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
920 // goto takenSuccMBB;
921 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
924 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
925 /// constant expression GEP support.
927 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
928 MachineBasicBlock::iterator IP,
929 Value *Src, User::op_iterator IdxBegin,
930 User::op_iterator IdxEnd, unsigned TargetReg) {
931 const TargetData &TD = TM.getTargetData ();
932 const Type *Ty = Src->getType ();
933 unsigned basePtrReg = getReg (Src, MBB, IP);
935 // GEPs have zero or more indices; we must perform a struct access
936 // or array access for each one.
937 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
940 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
941 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
942 // It's a struct access. idx is the index into the structure,
943 // which names the field. Use the TargetData structure to
944 // pick out what the layout of the structure is in memory.
945 // Use the (constant) structure index's value to find the
946 // right byte offset from the StructLayout class's list of
947 // structure member offsets.
948 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
949 unsigned memberOffset =
950 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
951 // Emit an ADD to add memberOffset to the basePtr.
952 BuildMI (*MBB, IP, V8::ADDri, 2,
953 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
954 // The next type is the member of the structure selected by the
956 Ty = StTy->getElementType (fieldIndex);
957 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
958 // It's an array or pointer access: [ArraySize x ElementType].
959 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
960 // must find the size of the pointed-to type (Not coincidentally, the next
961 // type is the type of the elements in the array).
962 Ty = SqTy->getElementType ();
963 unsigned elementSize = TD.getTypeSize (Ty);
964 unsigned idxReg = getReg (idx, MBB, IP);
965 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
966 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
967 copyConstantToRegister (MBB, IP,
968 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
969 // Emit a SMUL to multiply the register holding the index by
970 // elementSize, putting the result in OffsetReg.
971 BuildMI (*MBB, IP, V8::SMULrr, 2,
972 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
973 // Emit an ADD to add OffsetReg to the basePtr.
974 BuildMI (*MBB, IP, V8::ADDrr, 2,
975 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
977 basePtrReg = nextBasePtrReg;
979 // After we have processed all the indices, the result is left in
980 // basePtrReg. Move it to the register where we were expected to
982 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
985 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
986 unsigned outputReg = getReg (I);
987 emitGEPOperation (BB, BB->end (), I.getOperand (0),
988 I.op_begin ()+1, I.op_end (), outputReg);
992 void V8ISel::visitBinaryOperator (Instruction &I) {
993 unsigned DestReg = getReg (I);
994 unsigned Op0Reg = getReg (I.getOperand (0));
995 unsigned Op1Reg = getReg (I.getOperand (1));
997 unsigned Class = getClassB (I.getType());
998 unsigned OpCase = ~0;
1000 if (Class > cLong) {
1001 switch (I.getOpcode ()) {
1002 case Instruction::Add: OpCase = 0; break;
1003 case Instruction::Sub: OpCase = 1; break;
1004 case Instruction::Mul: OpCase = 2; break;
1005 case Instruction::Div: OpCase = 3; break;
1006 default: visitInstruction (I); return;
1008 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
1009 V8::FSUBS, V8::FSUBD,
1010 V8::FMULS, V8::FMULD,
1011 V8::FDIVS, V8::FDIVD };
1012 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
1013 .addReg (Op0Reg).addReg (Op1Reg);
1017 unsigned ResultReg = DestReg;
1018 if (Class != cInt && Class != cLong)
1019 ResultReg = makeAnotherReg (I.getType ());
1021 if (Class == cLong) {
1022 DEBUG (std::cerr << "Class = cLong\n");
1023 DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
1024 DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
1025 DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
1026 DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
1029 // FIXME: support long, ulong.
1030 switch (I.getOpcode ()) {
1031 case Instruction::Add: OpCase = 0; break;
1032 case Instruction::Sub: OpCase = 1; break;
1033 case Instruction::Mul: OpCase = 2; break;
1034 case Instruction::And: OpCase = 3; break;
1035 case Instruction::Or: OpCase = 4; break;
1036 case Instruction::Xor: OpCase = 5; break;
1037 case Instruction::Shl: OpCase = 6; break;
1038 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
1040 case Instruction::Div:
1041 case Instruction::Rem: {
1042 unsigned Dest = ResultReg;
1043 if (I.getOpcode() == Instruction::Rem)
1044 Dest = makeAnotherReg(I.getType());
1046 // FIXME: this is probably only right for 32 bit operands.
1047 if (I.getType ()->isSigned()) {
1048 unsigned Tmp = makeAnotherReg (I.getType ());
1049 // Sign extend into the Y register
1050 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
1051 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
1052 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1054 // Zero extend into the Y register, ie, just set it to zero
1055 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
1056 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1059 if (I.getOpcode() == Instruction::Rem) {
1060 unsigned Tmp = makeAnotherReg (I.getType ());
1061 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
1062 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
1067 visitInstruction (I);
1071 static const unsigned Opcodes[] = {
1072 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
1073 V8::SLLrr, V8::SRLrr, V8::SRArr
1075 if (OpCase != ~0U) {
1076 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1079 switch (getClassB (I.getType ())) {
1081 if (I.getType ()->isSigned ()) { // add byte
1082 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
1083 } else { // add ubyte
1084 unsigned TmpReg = makeAnotherReg (I.getType ());
1085 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
1086 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
1090 if (I.getType ()->isSigned ()) { // add short
1091 unsigned TmpReg = makeAnotherReg (I.getType ());
1092 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1093 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
1094 } else { // add ushort
1095 unsigned TmpReg = makeAnotherReg (I.getType ());
1096 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1097 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
1101 // Nothing to do here.
1104 // Only support and, or, xor.
1105 if (OpCase < 3 || OpCase > 5) {
1106 visitInstruction (I);
1109 // Do the other half of the value:
1110 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
1114 visitInstruction (I);
1118 void V8ISel::visitSetCondInst(SetCondInst &I) {
1119 unsigned Op0Reg = getReg (I.getOperand (0));
1120 unsigned Op1Reg = getReg (I.getOperand (1));
1121 unsigned DestReg = getReg (I);
1122 const Type *Ty = I.getOperand (0)->getType ();
1124 // Compare the two values.
1125 assert (getClass (Ty) != cLong && "can't setcc on longs yet");
1126 if (getClass (Ty) < cLong) {
1127 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1128 } else if (getClass (Ty) == cFloat) {
1129 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1130 } else if (getClass (Ty) == cDouble) {
1131 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1135 switch (I.getOpcode()) {
1136 default: assert(0 && "Unknown setcc instruction!");
1137 case Instruction::SetEQ: BranchIdx = 0; break;
1138 case Instruction::SetNE: BranchIdx = 1; break;
1139 case Instruction::SetLT: BranchIdx = 2; break;
1140 case Instruction::SetGT: BranchIdx = 3; break;
1141 case Instruction::SetLE: BranchIdx = 4; break;
1142 case Instruction::SetGE: BranchIdx = 5; break;
1144 unsigned Column = 0;
1145 if (Ty->isSigned()) ++Column;
1146 if (Ty->isFloatingPoint()) ++Column;
1147 static unsigned OpcodeTab[3*6] = {
1149 // unsigned signed fp
1150 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1151 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1152 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1153 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1154 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1155 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1157 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1159 MachineBasicBlock *thisMBB = BB;
1160 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1163 // subcc %reg0, %reg1, %g0
1167 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1168 // if we could insert other, non-terminator instructions after the
1169 // bCC. But MBB->getFirstTerminator() can't understand this.
1170 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
1171 F->getBasicBlockList ().push_back (copy1MBB);
1172 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
1173 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1174 F->getBasicBlockList ().push_back (copy0MBB);
1175 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
1176 // Update machine-CFG edges
1177 BB->addSuccessor (copy1MBB);
1178 BB->addSuccessor (copy0MBB);
1181 // %FalseValue = or %G0, 0
1184 unsigned FalseValue = makeAnotherReg (I.getType ());
1185 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
1186 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1187 F->getBasicBlockList ().push_back (sinkMBB);
1188 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1189 // Update machine-CFG edges
1190 BB->addSuccessor (sinkMBB);
1192 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1193 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
1194 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1195 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1198 // %TrueValue = or %G0, 1
1201 unsigned TrueValue = makeAnotherReg (I.getType ());
1202 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1203 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1204 // Update machine-CFG edges
1205 BB->addSuccessor (sinkMBB);
1208 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1211 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1212 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1215 void V8ISel::visitAllocaInst(AllocaInst &I) {
1216 // Find the data size of the alloca inst's getAllocatedType.
1217 const Type *Ty = I.getAllocatedType();
1218 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1220 unsigned ArraySizeReg = getReg (I.getArraySize ());
1221 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1222 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1223 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1224 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1226 // StackAdjReg = (ArraySize * TySize) rounded up to nearest doubleword boundary
1227 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1229 // Round up TmpReg1 to nearest doubleword boundary:
1230 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1231 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1233 // Subtract size from stack pointer, thereby allocating some space.
1234 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1236 // Put a pointer to the space into the result register, by copying
1237 // the stack pointer.
1238 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1240 // Inform the Frame Information that we have just allocated a variable-sized
1242 F->getFrameInfo()->CreateVariableSizedObject();
1245 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1246 /// function, lowering any calls to unknown intrinsic functions into the
1247 /// equivalent LLVM code.
1248 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1249 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1250 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1251 if (CallInst *CI = dyn_cast<CallInst>(I++))
1252 if (Function *F = CI->getCalledFunction())
1253 switch (F->getIntrinsicID()) {
1254 case Intrinsic::not_intrinsic: break;
1256 // All other intrinsic calls we must lower.
1257 Instruction *Before = CI->getPrev();
1258 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1259 if (Before) { // Move iterator to instruction after call
1268 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1269 unsigned TmpReg1, TmpReg2;
1271 default: assert(0 && "Intrinsic not supported!");