1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "llvm/Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/CodeGen/IntrinsicLowering.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
33 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
35 MachineFunction *F; // The function we are compiling into
36 MachineBasicBlock *BB; // The current MBB we are compiling
37 int VarArgsOffset; // Offset from fp for start of varargs area
39 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
41 // MBBMap - Mapping between LLVM BB -> Machine BB
42 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
44 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
46 /// runOnFunction - Top level implementation of instruction selection for
47 /// the entire function.
49 bool runOnFunction(Function &Fn);
51 virtual const char *getPassName() const {
52 return "SparcV8 Simple Instruction Selection";
55 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
56 /// constant expression GEP support.
58 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
59 Value *Src, User::op_iterator IdxBegin,
60 User::op_iterator IdxEnd, unsigned TargetReg);
62 /// emitCastOperation - Common code shared between visitCastInst and
63 /// constant expression cast support.
65 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
66 Value *Src, const Type *DestTy, unsigned TargetReg);
68 /// emitIntegerCast, emitFPToIntegerCast - Helper methods for
69 /// emitCastOperation.
71 unsigned emitIntegerCast (MachineBasicBlock *BB,
72 MachineBasicBlock::iterator IP,
73 const Type *oldTy, unsigned SrcReg,
74 const Type *newTy, unsigned DestReg,
75 bool castToLong = false);
76 void emitFPToIntegerCast (MachineBasicBlock *BB,
77 MachineBasicBlock::iterator IP, const Type *oldTy,
78 unsigned SrcReg, const Type *newTy,
81 /// visitBasicBlock - This method is called when we are visiting a new basic
82 /// block. This simply creates a new MachineBasicBlock to emit code into
83 /// and adds it to the current MachineFunction. Subsequent visit* for
84 /// instructions will be invoked for all instructions in the basic block.
86 void visitBasicBlock(BasicBlock &LLVM_BB) {
87 BB = MBBMap[&LLVM_BB];
90 void emitOp64LibraryCall (MachineBasicBlock *MBB,
91 MachineBasicBlock::iterator IP,
92 unsigned DestReg, const char *FuncName,
93 unsigned Op0Reg, unsigned Op1Reg);
94 void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
95 Instruction &I, unsigned DestReg, unsigned Op0Reg,
97 void visitBinaryOperator(Instruction &I);
98 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
99 void visitSetCondInst(SetCondInst &I);
100 void visitCallInst(CallInst &I);
101 void visitReturnInst(ReturnInst &I);
102 void visitBranchInst(BranchInst &I);
103 void visitUnreachableInst(UnreachableInst &I) {}
104 void visitCastInst(CastInst &I);
105 void visitVANextInst(VANextInst &I);
106 void visitVAArgInst(VAArgInst &I);
107 void visitLoadInst(LoadInst &I);
108 void visitStoreInst(StoreInst &I);
109 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
110 void visitGetElementPtrInst(GetElementPtrInst &I);
111 void visitAllocaInst(AllocaInst &I);
113 void visitInstruction(Instruction &I) {
114 std::cerr << "Unhandled instruction: " << I;
118 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
119 /// function, lowering any calls to unknown intrinsic functions into the
120 /// equivalent LLVM code.
121 void LowerUnknownIntrinsicFunctionCalls(Function &F);
122 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
124 void LoadArgumentsToVirtualRegs(Function *F);
126 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
127 /// because we have to generate our sources into the source basic blocks,
128 /// not the current one.
130 void SelectPHINodes();
132 /// copyConstantToRegister - Output the instructions required to put the
133 /// specified constant into the specified register.
135 void copyConstantToRegister(MachineBasicBlock *MBB,
136 MachineBasicBlock::iterator IP,
137 Constant *C, unsigned R);
139 /// makeAnotherReg - This method returns the next register number we haven't
142 /// Long values are handled somewhat specially. They are always allocated
143 /// as pairs of 32 bit integer values. The register number returned is the
144 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
145 /// of the long value.
147 unsigned makeAnotherReg(const Type *Ty) {
148 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
149 "Current target doesn't have SparcV8 reg info??");
150 const SparcV8RegisterInfo *MRI =
151 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
152 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
153 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
154 // Create the lower part
155 F->getSSARegMap()->createVirtualRegister(RC);
156 // Create the upper part.
157 return F->getSSARegMap()->createVirtualRegister(RC)-1;
160 // Add the mapping of regnumber => reg class to MachineFunction
161 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
162 return F->getSSARegMap()->createVirtualRegister(RC);
165 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
166 unsigned getReg(Value *V) {
167 // Just append to the end of the current bb.
168 MachineBasicBlock::iterator It = BB->end();
169 return getReg(V, BB, It);
171 unsigned getReg(Value *V, MachineBasicBlock *MBB,
172 MachineBasicBlock::iterator IPt) {
173 unsigned &Reg = RegMap[V];
175 Reg = makeAnotherReg(V->getType());
178 // If this operand is a constant, emit the code to copy the constant into
179 // the register here...
181 if (Constant *C = dyn_cast<Constant>(V)) {
182 copyConstantToRegister(MBB, IPt, C, Reg);
183 RegMap.erase(V); // Assign a new name to this constant if ref'd again
184 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
185 // Move the address of the global into the register
186 unsigned TmpReg = makeAnotherReg(V->getType());
187 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
188 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
189 .addGlobalAddress (GV);
190 RegMap.erase(V); // Assign a new name to this address if ref'd again
199 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
200 return new V8ISel(TM);
204 cByte, cShort, cInt, cLong, cFloat, cDouble
207 static TypeClass getClass (const Type *T) {
208 switch (T->getTypeID()) {
209 case Type::UByteTyID: case Type::SByteTyID: return cByte;
210 case Type::UShortTyID: case Type::ShortTyID: return cShort;
211 case Type::PointerTyID:
212 case Type::UIntTyID: case Type::IntTyID: return cInt;
213 case Type::ULongTyID: case Type::LongTyID: return cLong;
214 case Type::FloatTyID: return cFloat;
215 case Type::DoubleTyID: return cDouble;
217 assert (0 && "Type of unknown class passed to getClass?");
222 static TypeClass getClassB(const Type *T) {
223 if (T == Type::BoolTy) return cByte;
227 /// copyConstantToRegister - Output the instructions required to put the
228 /// specified constant into the specified register.
230 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
231 MachineBasicBlock::iterator IP,
232 Constant *C, unsigned R) {
233 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
234 switch (CE->getOpcode()) {
235 case Instruction::GetElementPtr:
236 emitGEPOperation(MBB, IP, CE->getOperand(0),
237 CE->op_begin()+1, CE->op_end(), R);
239 case Instruction::Cast:
240 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
243 std::cerr << "Copying this constant expr not yet handled: " << *CE;
246 } else if (isa<UndefValue>(C)) {
247 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
248 if (getClassB (C->getType ()) == cLong)
249 BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
253 if (C->getType()->isIntegral ()) {
254 unsigned Class = getClassB (C->getType ());
255 if (Class == cLong) {
256 unsigned TmpReg = makeAnotherReg (Type::IntTy);
257 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
258 // Copy the value into the register pair.
259 // R = top(more-significant) half, R+1 = bottom(less-significant) half
260 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
261 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
263 copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
264 Val & 0xffffffffU), R+1);
268 assert(Class <= cInt && "Type not handled yet!");
271 if (C->getType() == Type::BoolTy) {
272 Val = (C == ConstantBool::True);
274 ConstantIntegral *CI = cast<ConstantIntegral> (C);
275 Val = CI->getRawValue();
277 if (C->getType()->isSigned()) {
279 case cByte: Val = (int8_t) Val; break;
280 case cShort: Val = (int16_t) Val; break;
281 case cInt: Val = (int32_t) Val; break;
285 case cByte: Val = (uint8_t) Val; break;
286 case cShort: Val = (uint16_t) Val; break;
287 case cInt: Val = (uint32_t) Val; break;
291 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
292 } else if ((int)Val >= -4096 && (int)Val <= 4095) {
293 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
295 unsigned TmpReg = makeAnotherReg (C->getType ());
296 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
297 .addSImm (((uint32_t) Val) >> 10);
298 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
299 .addSImm (((uint32_t) Val) & 0x03ff);
302 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
303 // We need to spill the constant to memory...
304 MachineConstantPool *CP = F->getConstantPool();
305 unsigned CPI = CP->getConstantPoolIndex(CFP);
306 const Type *Ty = CFP->getType();
307 unsigned TmpReg = makeAnotherReg (Type::UIntTy);
308 unsigned AddrReg = makeAnotherReg (Type::UIntTy);
310 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
311 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
312 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
313 BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
314 .addConstantPoolIndex (CPI);
315 BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
316 } else if (isa<ConstantPointerNull>(C)) {
317 // Copy zero (null pointer) to the register.
318 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
319 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
320 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
321 // that SETHI %reg,global == SETHI %reg,%hi(global) and
322 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
323 unsigned TmpReg = makeAnotherReg (C->getType ());
324 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
325 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
327 std::cerr << "Offending constant: " << *C << "\n";
328 assert (0 && "Can't copy this kind of constant into register yet");
332 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
333 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
334 V8::I3, V8::I4, V8::I5 };
336 // Add IMPLICIT_DEFs of input regs.
338 for (Function::aiterator I = LF->abegin(), E = LF->aend();
339 I != E && ArgNo < 6; ++I, ++ArgNo) {
340 switch (getClassB(I->getType())) {
345 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
349 // Double and Long use register pairs.
350 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
353 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
356 assert (0 && "type not handled");
361 const unsigned *IAREnd = &IncomingArgRegs[6];
362 const unsigned *IAR = &IncomingArgRegs[0];
363 unsigned ArgOffset = 68;
365 // Store registers onto stack if this is a varargs function.
366 // FIXME: This doesn't really pertain to "loading arguments into
367 // virtual registers", so it's not clear that it really belongs here.
368 // FIXME: We could avoid storing any args onto the stack that don't
369 // need to be in memory, because they come before the ellipsis in the
370 // parameter list (and thus could never be accessed through va_arg).
371 if (LF->getFunctionType ()->isVarArg ()) {
372 for (unsigned i = 0; i < 6; ++i) {
373 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
374 assert (IAR != IAREnd
375 && "About to dereference past end of IncomingArgRegs");
376 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
379 // Reset the pointers now that we're done.
381 IAR = &IncomingArgRegs[0];
384 // Copy args out of their incoming hard regs or stack slots into virtual regs.
385 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
387 unsigned ArgReg = getReg (A);
388 if (getClassB (A.getType ()) < cLong) {
389 // Get it out of the incoming arg register
390 if (ArgOffset < 92) {
391 assert (IAR != IAREnd
392 && "About to dereference past end of IncomingArgRegs");
393 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
395 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
396 BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
399 } else if (getClassB (A.getType ()) == cFloat) {
400 if (ArgOffset < 92) {
401 // Single-fp args are passed in integer registers; go through
402 // memory to get them out of integer registers and back into fp. (Bleh!)
403 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
404 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
405 assert (IAR != IAREnd
406 && "About to dereference past end of IncomingArgRegs");
407 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
408 BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
410 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
411 BuildMI (BB, V8::LDFri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
414 } else if (getClassB (A.getType ()) == cDouble) {
415 // Double-fp args are passed in pairs of integer registers; go through
416 // memory to get them out of integer registers and back into fp. (Bleh!)
417 // We'd like to 'ldd' these right out of the incoming-args area,
418 // but it might not be 8-byte aligned (e.g., call x(int x, double d)).
419 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
420 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
421 if (ArgOffset < 92 && IAR != IAREnd) {
422 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
424 unsigned TempReg = makeAnotherReg (Type::IntTy);
425 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
426 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
429 if (ArgOffset < 92 && IAR != IAREnd) {
430 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
432 unsigned TempReg = makeAnotherReg (Type::IntTy);
433 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
434 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
437 BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
438 } else if (getClassB (A.getType ()) == cLong) {
439 // do the first half...
440 if (ArgOffset < 92) {
441 assert (IAR != IAREnd
442 && "About to dereference past end of IncomingArgRegs");
443 BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
445 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
446 BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
449 // ...then do the second half
450 if (ArgOffset < 92) {
451 assert (IAR != IAREnd
452 && "About to dereference past end of IncomingArgRegs");
453 BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
455 int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
456 BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
460 assert (0 && "Unknown class?!");
464 // If the function takes variable number of arguments, remember the fp
465 // offset for the start of the first vararg value... this is used to expand
467 if (LF->getFunctionType ()->isVarArg ())
468 VarArgsOffset = ArgOffset;
471 void V8ISel::SelectPHINodes() {
472 const TargetInstrInfo &TII = *TM.getInstrInfo();
473 const Function &LF = *F->getFunction(); // The LLVM function...
474 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
475 const BasicBlock *BB = I;
476 MachineBasicBlock &MBB = *MBBMap[I];
478 // Loop over all of the PHI nodes in the LLVM basic block...
479 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
480 for (BasicBlock::const_iterator I = BB->begin();
481 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
483 // Create a new machine instr PHI node, and insert it.
484 unsigned PHIReg = getReg(*PN);
485 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
486 V8::PHI, PN->getNumOperands(), PHIReg);
488 MachineInstr *LongPhiMI = 0;
489 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
490 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
491 V8::PHI, PN->getNumOperands(), PHIReg+1);
493 // PHIValues - Map of blocks to incoming virtual registers. We use this
494 // so that we only initialize one incoming value for a particular block,
495 // even if the block has multiple entries in the PHI node.
497 std::map<MachineBasicBlock*, unsigned> PHIValues;
499 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
500 MachineBasicBlock *PredMBB = 0;
501 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
502 PE = MBB.pred_end (); PI != PE; ++PI)
503 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
507 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
510 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
511 PHIValues.lower_bound(PredMBB);
513 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
514 // We already inserted an initialization of the register for this
515 // predecessor. Recycle it.
516 ValReg = EntryIt->second;
519 // Get the incoming value into a virtual register.
521 Value *Val = PN->getIncomingValue(i);
523 // If this is a constant or GlobalValue, we may have to insert code
524 // into the basic block to compute it into a virtual register.
525 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
526 isa<GlobalValue>(Val)) {
527 // Simple constants get emitted at the end of the basic block,
528 // before any terminator instructions. We "know" that the code to
529 // move a constant into a register will never clobber any flags.
530 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
532 // Because we don't want to clobber any values which might be in
533 // physical registers with the computation of this constant (which
534 // might be arbitrarily complex if it is a constant expression),
535 // just insert the computation at the top of the basic block.
536 MachineBasicBlock::iterator PI = PredMBB->begin();
538 // Skip over any PHI nodes though!
539 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
542 ValReg = getReg(Val, PredMBB, PI);
545 // Remember that we inserted a value for this PHI for this predecessor
546 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
549 PhiMI->addRegOperand(ValReg);
550 PhiMI->addMachineBasicBlockOperand(PredMBB);
552 LongPhiMI->addRegOperand(ValReg+1);
553 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
557 // Now that we emitted all of the incoming values for the PHI node, make
558 // sure to reposition the InsertPoint after the PHI that we just added.
559 // This is needed because we might have inserted a constant into this
560 // block, right after the PHI's which is before the old insert point!
561 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
567 bool V8ISel::runOnFunction(Function &Fn) {
568 // First pass over the function, lower any unknown intrinsic functions
569 // with the IntrinsicLowering class.
570 LowerUnknownIntrinsicFunctionCalls(Fn);
572 F = &MachineFunction::construct(&Fn, TM);
574 // Create all of the machine basic blocks for the function...
575 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
576 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
580 // Set up a frame object for the return address. This is used by the
581 // llvm.returnaddress & llvm.frameaddress intrinisics.
582 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
584 // Copy incoming arguments off of the stack and out of fixed registers.
585 LoadArgumentsToVirtualRegs(&Fn);
587 // Instruction select everything except PHI nodes
590 // Select the PHI nodes
596 // We always build a machine code representation for the function
600 void V8ISel::visitCastInst(CastInst &I) {
601 Value *Op = I.getOperand(0);
602 unsigned DestReg = getReg(I);
603 MachineBasicBlock::iterator MI = BB->end();
604 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
607 unsigned V8ISel::emitIntegerCast (MachineBasicBlock *BB,
608 MachineBasicBlock::iterator IP, const Type *oldTy,
609 unsigned SrcReg, const Type *newTy,
610 unsigned DestReg, bool castToLong) {
611 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
612 if (oldTy == newTy || (!castToLong && shiftWidth == 0)) {
613 // No-op cast - just emit a copy; assume the reg. allocator will zap it.
614 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg(SrcReg);
617 // Emit left-shift, then right-shift to sign- or zero-extend.
618 unsigned TmpReg = makeAnotherReg (newTy);
619 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg).addZImm (shiftWidth).addReg(SrcReg);
620 if (newTy->isSigned ()) { // sign-extend with SRA
621 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
622 } else { // zero-extend with SRL
623 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
625 // Return the temp reg. in case this is one half of a cast to long.
629 void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
630 MachineBasicBlock::iterator IP,
631 const Type *oldTy, unsigned SrcReg,
632 const Type *newTy, unsigned DestReg) {
633 unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
634 unsigned oldTyClass = getClassB(oldTy);
635 if (oldTyClass == cFloat) {
636 FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
637 FPAlign = TM.getTargetData().getFloatAlignment();
638 } else { // it's a double
639 FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
640 FPAlign = TM.getTargetData().getDoubleAlignment();
642 unsigned TempReg = makeAnotherReg (oldTy);
643 BuildMI (*BB, IP, FPCastOpcode, 1, TempReg).addReg (SrcReg);
644 int FI = F->getFrameInfo()->CreateStackObject(FPSize, FPAlign);
645 BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
647 unsigned TempReg2 = makeAnotherReg (newTy);
648 BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
649 emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
652 /// emitCastOperation - Common code shared between visitCastInst and constant
653 /// expression cast support.
655 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
656 MachineBasicBlock::iterator IP, Value *Src,
657 const Type *DestTy, unsigned DestReg) {
658 const Type *SrcTy = Src->getType();
659 unsigned SrcClass = getClassB(SrcTy);
660 unsigned DestClass = getClassB(DestTy);
661 unsigned SrcReg = getReg(Src, BB, IP);
663 const Type *oldTy = SrcTy;
664 const Type *newTy = DestTy;
665 unsigned oldTyClass = SrcClass;
666 unsigned newTyClass = DestClass;
668 if (oldTyClass < cLong && newTyClass < cLong) {
669 emitIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
670 } else switch (newTyClass) {
674 switch (oldTyClass) {
676 // Treat it like a cast from the lower half of the value.
677 emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
681 emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
683 default: goto not_yet;
688 switch (oldTyClass) {
689 case cLong: goto not_yet;
691 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
694 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
697 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
698 // cast integer type to float. Store it to a stack slot and then load
699 // it using ldf into a floating point register. then do fitos.
700 unsigned TmpReg = makeAnotherReg (newTy);
701 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
702 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
704 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
705 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
712 switch (oldTyClass) {
713 case cLong: goto not_yet;
715 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
717 case cDouble: // use double move pseudo-instr
718 BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
721 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
722 unsigned TmpReg = makeAnotherReg (newTy);
723 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
724 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
726 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
727 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
734 switch (oldTyClass) {
738 // Cast to (u)int in the bottom half, and sign(zero) extend in the top
740 const Type *OldHalfTy = oldTy->isSigned() ? Type::IntTy : Type::UIntTy;
741 const Type *NewHalfTy = newTy->isSigned() ? Type::IntTy : Type::UIntTy;
742 unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
743 NewHalfTy, DestReg+1, true);
744 if (newTy->isSigned ()) {
745 BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
748 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
754 // Just copy both halves.
755 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
756 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
759 default: goto not_yet;
763 default: goto not_yet;
767 std::cerr << "Sorry, cast still unsupported: SrcTy = " << *SrcTy
768 << ", DestTy = " << *DestTy << "\n";
772 void V8ISel::visitLoadInst(LoadInst &I) {
773 unsigned DestReg = getReg (I);
774 unsigned PtrReg = getReg (I.getOperand (0));
775 switch (getClassB (I.getType ())) {
777 if (I.getType ()->isSigned ())
778 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
780 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
783 if (I.getType ()->isSigned ())
784 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
786 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
789 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
792 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
793 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
796 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
799 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
802 std::cerr << "Load instruction not handled: " << I;
808 void V8ISel::visitStoreInst(StoreInst &I) {
809 Value *SrcVal = I.getOperand (0);
810 unsigned SrcReg = getReg (SrcVal);
811 unsigned PtrReg = getReg (I.getOperand (1));
812 switch (getClassB (SrcVal->getType ())) {
814 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
817 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
820 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
823 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
824 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
827 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
830 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
833 std::cerr << "Store instruction not handled: " << I;
839 void V8ISel::visitCallInst(CallInst &I) {
840 MachineInstr *TheCall;
841 // Is it an intrinsic function call?
842 if (Function *F = I.getCalledFunction()) {
843 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
844 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
849 // How much extra call stack will we need?
851 for (unsigned i = 0; i < I.getNumOperands (); ++i) {
852 switch (getClassB (I.getOperand (i)->getType ())) {
853 case cLong: extraStack += 8; break;
854 case cFloat: extraStack += 4; break;
855 case cDouble: extraStack += 8; break;
856 default: extraStack += 4; break;
860 if (extraStack < 0) {
863 // Round up extra stack size to the nearest doubleword.
864 extraStack = (extraStack + 7) & ~7;
868 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
870 const unsigned *OAREnd = &OutgoingArgRegs[6];
871 const unsigned *OAR = &OutgoingArgRegs[0];
872 unsigned ArgOffset = 68;
873 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKDOWN, 1).addImm (extraStack);
874 for (unsigned i = 1; i < I.getNumOperands (); ++i) {
875 unsigned ArgReg = getReg (I.getOperand (i));
876 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
877 // Schlep it over into the incoming arg register
878 if (ArgOffset < 92) {
879 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
880 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
882 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
885 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
886 if (ArgOffset < 92) {
887 // Single-fp args are passed in integer registers; go through
888 // memory to get them out of FP registers. (Bleh!)
889 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
890 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
891 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
892 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
893 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
895 BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
898 } else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
899 // Double-fp args are passed in pairs of integer registers; go through
900 // memory to get them out of FP registers. (Bleh!)
901 // We'd like to 'std' these right onto the outgoing-args area, but it might
902 // not be 8-byte aligned (e.g., call x(int x, double d)). sigh.
903 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
904 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
905 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
906 if (ArgOffset < 92 && OAR != OAREnd) {
907 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
908 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
910 unsigned TempReg = makeAnotherReg (Type::IntTy);
911 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
912 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
915 if (ArgOffset < 92 && OAR != OAREnd) {
916 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
917 BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
919 unsigned TempReg = makeAnotherReg (Type::IntTy);
920 BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
921 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
924 } else if (getClassB (I.getOperand (i)->getType ()) == cLong) {
925 // do the first half...
926 if (ArgOffset < 92) {
927 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
928 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
930 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
933 // ...then do the second half
934 if (ArgOffset < 92) {
935 assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
936 BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
938 BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg+1);
942 assert (0 && "Unknown class?!");
946 // Emit call instruction
947 if (Function *F = I.getCalledFunction ()) {
948 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
949 } else { // Emit an indirect call...
950 unsigned Reg = getReg (I.getCalledValue ());
951 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
954 if (extraStack) BuildMI (BB, V8::ADJCALLSTACKUP, 1).addImm (extraStack);
956 // Deal w/ return value: schlep it over into the destination register
957 if (I.getType () == Type::VoidTy)
959 unsigned DestReg = getReg (I);
960 switch (getClassB (I.getType ())) {
964 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
967 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
970 BuildMI (BB, V8::FpMOVD, 2, DestReg).addReg(V8::D0);
973 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
974 BuildMI (BB, V8::ORrr, 2, DestReg+1).addReg(V8::G0).addReg(V8::O1);
977 std::cerr << "Return type of call instruction not handled: " << I;
982 void V8ISel::visitReturnInst(ReturnInst &I) {
983 if (I.getNumOperands () == 1) {
984 unsigned RetValReg = getReg (I.getOperand (0));
985 switch (getClassB (I.getOperand (0)->getType ())) {
989 // Schlep it over into i0 (where it will become o0 after restore).
990 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
993 BuildMI (BB, V8::FMOVS, 1, V8::F0).addReg(RetValReg);
996 BuildMI (BB, V8::FpMOVD, 1, V8::D0).addReg(RetValReg);
999 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
1000 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
1003 std::cerr << "Return instruction of this type not handled: " << I;
1008 // Just emit a 'retl' instruction to return.
1009 BuildMI(BB, V8::RETL, 0);
1013 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1014 Function::iterator I = BB; ++I; // Get iterator to next block
1015 return I != BB->getParent()->end() ? &*I : 0;
1018 /// canFoldSetCCIntoBranch - Return the setcc instruction if we can fold it
1019 /// into the conditional branch which is the only user of the cc instruction.
1020 /// This is the case if the conditional branch is the only user of the setcc.
1022 static SetCondInst *canFoldSetCCIntoBranch(Value *V) {
1023 //return 0; // disable.
1024 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
1025 if (SCI->hasOneUse()) {
1026 BranchInst *User = dyn_cast<BranchInst>(SCI->use_back());
1028 && (SCI->getNext() == User)
1029 && (getClassB(SCI->getOperand(0)->getType()) != cLong)
1030 && User->isConditional() && (User->getCondition() == V))
1036 /// visitBranchInst - Handles conditional and unconditional branches.
1038 void V8ISel::visitBranchInst(BranchInst &I) {
1039 BasicBlock *takenSucc = I.getSuccessor (0);
1040 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
1041 BB->addSuccessor (takenSuccMBB);
1042 if (I.isConditional()) { // conditional branch
1043 BasicBlock *notTakenSucc = I.getSuccessor (1);
1044 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
1045 BB->addSuccessor (notTakenSuccMBB);
1047 // See if we can fold a previous setcc instr into this branch.
1048 SetCondInst *SCI = canFoldSetCCIntoBranch(I.getCondition());
1050 // The condition did not come from a setcc which we could fold.
1051 // CondReg=(<condition>);
1052 // If (CondReg==0) goto notTakenSuccMBB;
1053 unsigned CondReg = getReg (I.getCondition ());
1054 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
1055 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
1056 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
1060 // Fold the setCC instr into the branch.
1061 unsigned Op0Reg = getReg (SCI->getOperand (0));
1062 unsigned Op1Reg = getReg (SCI->getOperand (1));
1063 const Type *Ty = SCI->getOperand (0)->getType ();
1065 // Compare the two values.
1066 if (getClass (Ty) < cLong) {
1067 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1068 } else if (getClass (Ty) == cLong) {
1069 assert (0 && "Can't fold setcc long/ulong into branch");
1070 } else if (getClass (Ty) == cFloat) {
1071 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1072 } else if (getClass (Ty) == cDouble) {
1073 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1077 switch (SCI->getOpcode()) {
1078 default: assert(0 && "Unknown setcc instruction!");
1079 case Instruction::SetEQ: BranchIdx = 0; break;
1080 case Instruction::SetNE: BranchIdx = 1; break;
1081 case Instruction::SetLT: BranchIdx = 2; break;
1082 case Instruction::SetGT: BranchIdx = 3; break;
1083 case Instruction::SetLE: BranchIdx = 4; break;
1084 case Instruction::SetGE: BranchIdx = 5; break;
1087 unsigned Column = 0;
1088 if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
1089 if (Ty->isFloatingPoint()) Column = 2;
1090 static unsigned OpcodeTab[3*6] = {
1092 // unsigned signed fp
1093 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1094 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1095 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1096 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1097 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1098 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1100 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1101 BuildMI (BB, Opcode, 1).addMBB (takenSuccMBB);
1102 BuildMI (BB, V8::BA, 1).addMBB (notTakenSuccMBB);
1104 // goto takenSuccMBB;
1105 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
1109 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
1110 /// constant expression GEP support.
1112 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
1113 MachineBasicBlock::iterator IP,
1114 Value *Src, User::op_iterator IdxBegin,
1115 User::op_iterator IdxEnd, unsigned TargetReg) {
1116 const TargetData &TD = TM.getTargetData ();
1117 const Type *Ty = Src->getType ();
1118 unsigned basePtrReg = getReg (Src, MBB, IP);
1120 // GEPs have zero or more indices; we must perform a struct access
1121 // or array access for each one.
1122 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
1125 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
1126 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
1127 // It's a struct access. idx is the index into the structure,
1128 // which names the field. Use the TargetData structure to
1129 // pick out what the layout of the structure is in memory.
1130 // Use the (constant) structure index's value to find the
1131 // right byte offset from the StructLayout class's list of
1132 // structure member offsets.
1133 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
1134 unsigned memberOffset =
1135 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
1136 // Emit an ADD to add memberOffset to the basePtr.
1137 // We might have to copy memberOffset into a register first, if
1139 if (memberOffset + 4096 < 8191) {
1140 BuildMI (*MBB, IP, V8::ADDri, 2,
1141 nextBasePtrReg).addReg (basePtrReg).addSImm (memberOffset);
1143 unsigned offsetReg = makeAnotherReg (Type::IntTy);
1144 copyConstantToRegister (MBB, IP,
1145 ConstantSInt::get(Type::IntTy, memberOffset), offsetReg);
1146 BuildMI (*MBB, IP, V8::ADDrr, 2,
1147 nextBasePtrReg).addReg (basePtrReg).addReg (offsetReg);
1149 // The next type is the member of the structure selected by the
1151 Ty = StTy->getElementType (fieldIndex);
1152 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
1153 // It's an array or pointer access: [ArraySize x ElementType].
1154 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
1155 // must find the size of the pointed-to type (Not coincidentally, the next
1156 // type is the type of the elements in the array).
1157 Ty = SqTy->getElementType ();
1158 unsigned elementSize = TD.getTypeSize (Ty);
1159 unsigned OffsetReg = ~0U;
1160 int64_t Offset = -1;
1161 bool addImmed = false;
1162 if (isa<ConstantIntegral> (idx)) {
1163 // If idx is a constant, we don't have to emit the multiply.
1164 int64_t Val = cast<ConstantIntegral> (idx)->getRawValue ();
1165 if ((Val * elementSize) + 4096 < 8191) {
1166 // (Val * elementSize) is constant and fits in an immediate field.
1167 // emit: nextBasePtrReg = ADDri basePtrReg, (Val * elementSize)
1169 Offset = Val * elementSize;
1171 // (Val * elementSize) is constant, but doesn't fit in an immediate
1172 // field. emit: OffsetReg = (Val * elementSize)
1173 // nextBasePtrReg = ADDrr OffsetReg, basePtrReg
1174 OffsetReg = makeAnotherReg (Type::IntTy);
1175 copyConstantToRegister (MBB, IP,
1176 ConstantSInt::get(Type::IntTy, Val * elementSize), OffsetReg);
1179 // idx is not constant, we have to shift or multiply.
1180 OffsetReg = makeAnotherReg (Type::IntTy);
1181 unsigned idxReg = getReg (idx, MBB, IP);
1182 switch (elementSize) {
1184 BuildMI (*MBB, IP, V8::ORrr, 2, OffsetReg).addReg (V8::G0).addReg (idxReg);
1187 BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (1);
1190 BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (2);
1193 BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (3);
1196 if (elementSize + 4096 < 8191) {
1197 // Emit a SMUL to multiply the register holding the index by
1198 // elementSize, putting the result in OffsetReg.
1199 BuildMI (*MBB, IP, V8::SMULri, 2,
1200 OffsetReg).addReg (idxReg).addSImm (elementSize);
1202 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
1203 copyConstantToRegister (MBB, IP,
1204 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
1205 // Emit a SMUL to multiply the register holding the index by
1206 // the register w/ elementSize, putting the result in OffsetReg.
1207 BuildMI (*MBB, IP, V8::SMULrr, 2,
1208 OffsetReg).addReg (idxReg).addReg (elementSizeReg);
1215 // Emit an ADD to add the constant immediate Offset to the basePtr.
1216 BuildMI (*MBB, IP, V8::ADDri, 2,
1217 nextBasePtrReg).addReg (basePtrReg).addSImm (Offset);
1219 // Emit an ADD to add OffsetReg to the basePtr.
1220 BuildMI (*MBB, IP, V8::ADDrr, 2,
1221 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
1224 basePtrReg = nextBasePtrReg;
1226 // After we have processed all the indices, the result is left in
1227 // basePtrReg. Move it to the register where we were expected to
1229 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
1232 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
1233 unsigned outputReg = getReg (I);
1234 emitGEPOperation (BB, BB->end (), I.getOperand (0),
1235 I.op_begin ()+1, I.op_end (), outputReg);
1238 void V8ISel::emitOp64LibraryCall (MachineBasicBlock *MBB,
1239 MachineBasicBlock::iterator IP,
1241 const char *FuncName,
1242 unsigned Op0Reg, unsigned Op1Reg) {
1243 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O0).addReg (V8::G0).addReg (Op0Reg);
1244 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O1).addReg (V8::G0).addReg (Op0Reg+1);
1245 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O2).addReg (V8::G0).addReg (Op1Reg);
1246 BuildMI (*MBB, IP, V8::ORrr, 2, V8::O3).addReg (V8::G0).addReg (Op1Reg+1);
1247 BuildMI (*MBB, IP, V8::CALL, 1).addExternalSymbol (FuncName, true);
1248 BuildMI (*MBB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (V8::O0);
1249 BuildMI (*MBB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0).addReg (V8::O1);
1252 void V8ISel::emitShift64 (MachineBasicBlock *MBB,
1253 MachineBasicBlock::iterator IP, Instruction &I,
1254 unsigned DestReg, unsigned SrcReg,
1255 unsigned ShiftAmtReg) {
1256 bool isSigned = I.getType()->isSigned();
1258 switch (I.getOpcode ()) {
1259 case Instruction::Shr: {
1260 unsigned CarryReg = makeAnotherReg (Type::IntTy),
1261 ThirtyTwo = makeAnotherReg (Type::IntTy),
1262 HalfShiftReg = makeAnotherReg (Type::IntTy),
1263 NegHalfShiftReg = makeAnotherReg (Type::IntTy),
1264 TempReg = makeAnotherReg (Type::IntTy);
1265 unsigned OneShiftOutReg = makeAnotherReg (Type::ULongTy),
1266 TwoShiftsOutReg = makeAnotherReg (Type::ULongTy);
1268 MachineBasicBlock *thisMBB = BB;
1269 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1270 MachineBasicBlock *shiftMBB = new MachineBasicBlock (LLVM_BB);
1271 F->getBasicBlockList ().push_back (shiftMBB);
1272 MachineBasicBlock *oneShiftMBB = new MachineBasicBlock (LLVM_BB);
1273 F->getBasicBlockList ().push_back (oneShiftMBB);
1274 MachineBasicBlock *twoShiftsMBB = new MachineBasicBlock (LLVM_BB);
1275 F->getBasicBlockList ().push_back (twoShiftsMBB);
1276 MachineBasicBlock *continueMBB = new MachineBasicBlock (LLVM_BB);
1277 F->getBasicBlockList ().push_back (continueMBB);
1281 // subcc %g0, ShiftAmtReg, %g0 ! Is ShAmt == 0?
1282 // be .lshr_continue ! Then don't shift.
1283 // ba .lshr_shift ! else shift.
1285 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (V8::G0)
1286 .addReg (ShiftAmtReg);
1287 BuildMI (BB, V8::BE, 1).addMBB (continueMBB);
1288 BuildMI (BB, V8::BA, 1).addMBB (shiftMBB);
1290 // Update machine-CFG edges
1291 BB->addSuccessor (continueMBB);
1292 BB->addSuccessor (shiftMBB);
1294 // .lshr_shift: ! [preds: begin]
1295 // or %g0, 32, ThirtyTwo
1296 // subcc ThirtyTwo, ShiftAmtReg, HalfShiftReg ! Calculate 32 - shamt
1297 // bg .lshr_two_shifts ! If >0, b two_shifts
1298 // ba .lshr_one_shift ! else one_shift.
1302 BuildMI (BB, V8::ORri, 2, ThirtyTwo).addReg (V8::G0).addSImm (32);
1303 BuildMI (BB, V8::SUBCCrr, 2, HalfShiftReg).addReg (ThirtyTwo)
1304 .addReg (ShiftAmtReg);
1305 BuildMI (BB, V8::BG, 1).addMBB (twoShiftsMBB);
1306 BuildMI (BB, V8::BA, 1).addMBB (oneShiftMBB);
1308 // Update machine-CFG edges
1309 BB->addSuccessor (twoShiftsMBB);
1310 BB->addSuccessor (oneShiftMBB);
1312 // .lshr_two_shifts: ! [preds: shift]
1313 // sll SrcReg, HalfShiftReg, CarryReg ! Save the borrows
1314 // ! <SHIFT> in following is sra if signed, srl if unsigned
1315 // <SHIFT> SrcReg, ShiftAmtReg, TwoShiftsOutReg ! Shift top half
1316 // srl SrcReg+1, ShiftAmtReg, TempReg ! Shift bottom half
1317 // or TempReg, CarryReg, TwoShiftsOutReg+1 ! Restore the borrows
1318 // ba .lshr_continue
1319 unsigned ShiftOpcode = (isSigned ? V8::SRArr : V8::SRLrr);
1323 BuildMI (BB, V8::SLLrr, 2, CarryReg).addReg (SrcReg)
1324 .addReg (HalfShiftReg);
1325 BuildMI (BB, ShiftOpcode, 2, TwoShiftsOutReg).addReg (SrcReg)
1326 .addReg (ShiftAmtReg);
1327 BuildMI (BB, V8::SRLrr, 2, TempReg).addReg (SrcReg+1)
1328 .addReg (ShiftAmtReg);
1329 BuildMI (BB, V8::ORrr, 2, TwoShiftsOutReg+1).addReg (TempReg)
1331 BuildMI (BB, V8::BA, 1).addMBB (continueMBB);
1333 // Update machine-CFG edges
1334 BB->addSuccessor (continueMBB);
1336 // .lshr_one_shift: ! [preds: shift]
1338 // or %g0, %g0, OneShiftOutReg ! Zero top half
1340 // sra SrcReg, 31, OneShiftOutReg ! Sign-ext top half
1341 // sub %g0, HalfShiftReg, NegHalfShiftReg ! Make ShiftAmt >0
1342 // <SHIFT> SrcReg, NegHalfShiftReg, OneShiftOutReg+1 ! Shift bottom half
1343 // ba .lshr_continue
1348 BuildMI (BB, V8::SRAri, 2, OneShiftOutReg).addReg (SrcReg).addZImm (31);
1350 BuildMI (BB, V8::ORrr, 2, OneShiftOutReg).addReg (V8::G0)
1352 BuildMI (BB, V8::SUBrr, 2, NegHalfShiftReg).addReg (V8::G0)
1353 .addReg (HalfShiftReg);
1354 BuildMI (BB, ShiftOpcode, 2, OneShiftOutReg+1).addReg (SrcReg)
1355 .addReg (NegHalfShiftReg);
1356 BuildMI (BB, V8::BA, 1).addMBB (continueMBB);
1358 // Update machine-CFG edges
1359 BB->addSuccessor (continueMBB);
1361 // .lshr_continue: ! [preds: begin, do_one_shift, do_two_shifts]
1362 // phi (SrcReg, begin), (TwoShiftsOutReg, two_shifts),
1363 // (OneShiftOutReg, one_shift), DestReg ! Phi top half...
1364 // phi (SrcReg+1, begin), (TwoShiftsOutReg+1, two_shifts),
1365 // (OneShiftOutReg+1, one_shift), DestReg+1 ! And phi bottom half.
1368 BuildMI (BB, V8::PHI, 6, DestReg).addReg (SrcReg).addMBB (thisMBB)
1369 .addReg (TwoShiftsOutReg).addMBB (twoShiftsMBB)
1370 .addReg (OneShiftOutReg).addMBB (oneShiftMBB);
1371 BuildMI (BB, V8::PHI, 6, DestReg+1).addReg (SrcReg+1).addMBB (thisMBB)
1372 .addReg (TwoShiftsOutReg+1).addMBB (twoShiftsMBB)
1373 .addReg (OneShiftOutReg+1).addMBB (oneShiftMBB);
1376 case Instruction::Shl:
1378 std::cerr << "Sorry, 64-bit shifts are not yet supported:\n" << I;
1383 void V8ISel::visitBinaryOperator (Instruction &I) {
1384 unsigned DestReg = getReg (I);
1385 unsigned Op0Reg = getReg (I.getOperand (0));
1387 unsigned Class = getClassB (I.getType());
1388 unsigned OpCase = ~0;
1390 if (Class > cLong) {
1391 unsigned Op1Reg = getReg (I.getOperand (1));
1392 switch (I.getOpcode ()) {
1393 case Instruction::Add: OpCase = 0; break;
1394 case Instruction::Sub: OpCase = 1; break;
1395 case Instruction::Mul: OpCase = 2; break;
1396 case Instruction::Div: OpCase = 3; break;
1397 default: visitInstruction (I); return;
1399 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
1400 V8::FSUBS, V8::FSUBD,
1401 V8::FMULS, V8::FMULD,
1402 V8::FDIVS, V8::FDIVD };
1403 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
1404 .addReg (Op0Reg).addReg (Op1Reg);
1408 unsigned ResultReg = DestReg;
1409 if (Class != cInt && Class != cLong)
1410 ResultReg = makeAnotherReg (I.getType ());
1412 if (Class == cLong) {
1413 const char *FuncName;
1414 unsigned Op1Reg = getReg (I.getOperand (1));
1415 DEBUG (std::cerr << "Class = cLong\n");
1416 DEBUG (std::cerr << "Op0Reg = " << Op0Reg << ", " << Op0Reg+1 << "\n");
1417 DEBUG (std::cerr << "Op1Reg = " << Op1Reg << ", " << Op1Reg+1 << "\n");
1418 DEBUG (std::cerr << "ResultReg = " << ResultReg << ", " << ResultReg+1 << "\n");
1419 DEBUG (std::cerr << "DestReg = " << DestReg << ", " << DestReg+1 << "\n");
1420 switch (I.getOpcode ()) {
1421 case Instruction::Add:
1422 BuildMI (BB, V8::ADDCCrr, 2, ResultReg+1).addReg (Op0Reg+1)
1424 BuildMI (BB, V8::ADDXrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1426 case Instruction::Sub:
1427 BuildMI (BB, V8::SUBCCrr, 2, ResultReg+1).addReg (Op0Reg+1)
1429 BuildMI (BB, V8::SUBXrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1431 case Instruction::Mul:
1432 FuncName = I.getType ()->isSigned () ? "__mul64" : "__umul64";
1433 emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
1435 case Instruction::Div:
1436 FuncName = I.getType ()->isSigned () ? "__div64" : "__udiv64";
1437 emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
1439 case Instruction::Rem:
1440 FuncName = I.getType ()->isSigned () ? "__rem64" : "__urem64";
1441 emitOp64LibraryCall (BB, BB->end (), DestReg, FuncName, Op0Reg, Op1Reg);
1443 case Instruction::Shl:
1444 case Instruction::Shr:
1445 emitShift64 (BB, BB->end (), I, DestReg, Op0Reg, Op1Reg);
1450 switch (I.getOpcode ()) {
1451 case Instruction::Add: OpCase = 0; break;
1452 case Instruction::Sub: OpCase = 1; break;
1453 case Instruction::Mul: OpCase = 2; break;
1454 case Instruction::And: OpCase = 3; break;
1455 case Instruction::Or: OpCase = 4; break;
1456 case Instruction::Xor: OpCase = 5; break;
1457 case Instruction::Shl: OpCase = 6; break;
1458 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
1460 case Instruction::Div:
1461 case Instruction::Rem: {
1462 unsigned Dest = ResultReg;
1463 unsigned Op1Reg = getReg (I.getOperand (1));
1464 if (I.getOpcode() == Instruction::Rem)
1465 Dest = makeAnotherReg(I.getType());
1467 // FIXME: this is probably only right for 32 bit operands.
1468 if (I.getType ()->isSigned()) {
1469 unsigned Tmp = makeAnotherReg (I.getType ());
1470 // Sign extend into the Y register
1471 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
1472 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
1473 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1475 // Zero extend into the Y register, ie, just set it to zero
1476 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
1477 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
1480 if (I.getOpcode() == Instruction::Rem) {
1481 unsigned Tmp = makeAnotherReg (I.getType ());
1482 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
1483 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
1488 visitInstruction (I);
1492 static const unsigned Opcodes[] = {
1493 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
1494 V8::SLLrr, V8::SRLrr, V8::SRArr
1496 static const unsigned OpcodesRI[] = {
1497 V8::ADDri, V8::SUBri, V8::SMULri, V8::ANDri, V8::ORri, V8::XORri,
1498 V8::SLLri, V8::SRLri, V8::SRAri
1500 unsigned Op1Reg = ~0U;
1501 if (OpCase != ~0U) {
1502 Value *Arg1 = I.getOperand (1);
1503 bool useImmed = false;
1505 if ((getClassB (I.getType ()) <= cInt) && (isa<ConstantIntegral> (Arg1))) {
1506 Val = cast<ConstantIntegral> (Arg1)->getRawValue ();
1507 useImmed = (Val > -4096 && Val < 4095);
1510 BuildMI (BB, OpcodesRI[OpCase], 2, ResultReg).addReg (Op0Reg).addSImm (Val);
1512 Op1Reg = getReg (I.getOperand (1));
1513 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
1517 switch (getClassB (I.getType ())) {
1519 if (I.getType ()->isSigned ()) { // add byte
1520 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
1521 } else { // add ubyte
1522 unsigned TmpReg = makeAnotherReg (I.getType ());
1523 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
1524 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
1528 if (I.getType ()->isSigned ()) { // add short
1529 unsigned TmpReg = makeAnotherReg (I.getType ());
1530 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1531 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
1532 } else { // add ushort
1533 unsigned TmpReg = makeAnotherReg (I.getType ());
1534 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
1535 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
1539 // Nothing to do here.
1542 // Only support and, or, xor here - others taken care of above.
1543 if (OpCase < 3 || OpCase > 5) {
1544 visitInstruction (I);
1547 // Do the other half of the value:
1548 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
1553 visitInstruction (I);
1557 void V8ISel::visitSetCondInst(SetCondInst &I) {
1558 if (canFoldSetCCIntoBranch(&I))
1559 return; // Fold this into a branch.
1561 unsigned Op0Reg = getReg (I.getOperand (0));
1562 unsigned Op1Reg = getReg (I.getOperand (1));
1563 unsigned DestReg = getReg (I);
1564 const Type *Ty = I.getOperand (0)->getType ();
1566 // Compare the two values.
1567 if (getClass (Ty) < cLong) {
1568 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1569 } else if (getClass (Ty) == cLong) {
1570 switch (I.getOpcode()) {
1571 default: assert(0 && "Unknown setcc instruction!");
1572 case Instruction::SetEQ:
1573 case Instruction::SetNE: {
1574 unsigned TempReg0 = makeAnotherReg (Type::IntTy),
1575 TempReg1 = makeAnotherReg (Type::IntTy),
1576 TempReg2 = makeAnotherReg (Type::IntTy),
1577 TempReg3 = makeAnotherReg (Type::IntTy);
1578 MachineOpCode Opcode;
1580 // These guys are special - no branches needed!
1581 BuildMI (BB, V8::XORrr, 2, TempReg0).addReg (Op0Reg+1).addReg (Op1Reg+1);
1582 BuildMI (BB, V8::XORrr, 2, TempReg1).addReg (Op0Reg).addReg (Op1Reg);
1583 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (V8::G0).addReg (TempReg1);
1584 Opcode = I.getOpcode() == Instruction::SetEQ ? V8::SUBXri : V8::ADDXri;
1585 Immed = I.getOpcode() == Instruction::SetEQ ? -1 : 0;
1586 BuildMI (BB, Opcode, 2, TempReg2).addReg (V8::G0).addSImm (Immed);
1587 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (V8::G0).addReg (TempReg0);
1588 BuildMI (BB, Opcode, 2, TempReg3).addReg (V8::G0).addSImm (Immed);
1589 Opcode = I.getOpcode() == Instruction::SetEQ ? V8::ANDrr : V8::ORrr;
1590 BuildMI (BB, Opcode, 2, DestReg).addReg (TempReg2).addReg (TempReg3);
1593 case Instruction::SetLT:
1594 case Instruction::SetGE:
1595 BuildMI (BB, V8::SUBCCrr, 2, V8::G0).addReg (Op0Reg+1).addReg (Op1Reg+1);
1596 BuildMI (BB, V8::SUBXCCrr, 2, V8::G0).addReg (Op0Reg).addReg (Op1Reg);
1598 case Instruction::SetGT:
1599 case Instruction::SetLE:
1600 BuildMI (BB, V8::SUBCCri, 2, V8::G0).addReg (V8::G0).addSImm (1);
1601 BuildMI (BB, V8::SUBXCCrr, 2, V8::G0).addReg (Op0Reg+1).addReg (Op1Reg+1);
1602 BuildMI (BB, V8::SUBXCCrr, 2, V8::G0).addReg (Op0Reg).addReg (Op1Reg);
1605 } else if (getClass (Ty) == cFloat) {
1606 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1607 } else if (getClass (Ty) == cDouble) {
1608 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1612 switch (I.getOpcode()) {
1613 default: assert(0 && "Unknown setcc instruction!");
1614 case Instruction::SetEQ: BranchIdx = 0; break;
1615 case Instruction::SetNE: BranchIdx = 1; break;
1616 case Instruction::SetLT: BranchIdx = 2; break;
1617 case Instruction::SetGT: BranchIdx = 3; break;
1618 case Instruction::SetLE: BranchIdx = 4; break;
1619 case Instruction::SetGE: BranchIdx = 5; break;
1622 unsigned Column = 0;
1623 if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
1624 if (Ty->isFloatingPoint()) Column = 2;
1625 static unsigned OpcodeTab[3*6] = {
1627 // unsigned signed fp
1628 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1629 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1630 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1631 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1632 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1633 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1635 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1637 MachineBasicBlock *thisMBB = BB;
1638 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1641 // subcc %reg0, %reg1, %g0
1642 // TrueVal = or G0, 1
1645 unsigned TrueValue = makeAnotherReg (I.getType ());
1646 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1648 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1649 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1650 BuildMI (BB, Opcode, 1).addMBB (sinkMBB);
1652 // Update machine-CFG edges
1653 BB->addSuccessor (sinkMBB);
1654 BB->addSuccessor (copy0MBB);
1657 // %FalseValue = or %G0, 0
1660 F->getBasicBlockList ().push_back (BB);
1661 unsigned FalseValue = makeAnotherReg (I.getType ());
1662 BuildMI (BB, V8::ORrr, 2, FalseValue).addReg (V8::G0).addReg (V8::G0);
1664 // Update machine-CFG edges
1665 BB->addSuccessor (sinkMBB);
1667 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1668 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1669 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1672 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1675 F->getBasicBlockList ().push_back (BB);
1676 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1677 .addMBB (copy0MBB).addReg (TrueValue).addMBB (thisMBB);
1680 void V8ISel::visitAllocaInst(AllocaInst &I) {
1681 // Find the data size of the alloca inst's getAllocatedType.
1682 const Type *Ty = I.getAllocatedType();
1683 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1685 unsigned ArraySizeReg = getReg (I.getArraySize ());
1686 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1687 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1688 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1689 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1691 // StackAdjReg = (ArraySize * TySize) rounded up to nearest
1692 // doubleword boundary.
1693 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1695 // Round up TmpReg1 to nearest doubleword boundary:
1696 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1697 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1699 // Subtract size from stack pointer, thereby allocating some space.
1700 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1702 // Put a pointer to the space into the result register, by copying
1703 // the stack pointer.
1704 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1706 // Inform the Frame Information that we have just allocated a variable-sized
1708 F->getFrameInfo()->CreateVariableSizedObject();
1711 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1712 /// function, lowering any calls to unknown intrinsic functions into the
1713 /// equivalent LLVM code.
1714 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1715 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1716 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1717 if (CallInst *CI = dyn_cast<CallInst>(I++))
1718 if (Function *F = CI->getCalledFunction())
1719 switch (F->getIntrinsicID()) {
1720 case Intrinsic::vastart:
1721 case Intrinsic::vacopy:
1722 case Intrinsic::vaend:
1723 // We directly implement these intrinsics
1724 case Intrinsic::not_intrinsic: break;
1726 // All other intrinsic calls we must lower.
1727 Instruction *Before = CI->getPrev();
1728 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1729 if (Before) { // Move iterator to instruction after call
1738 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1741 std::cerr << "Sorry, unknown intrinsic function call:\n" << CI; abort ();
1743 case Intrinsic::vastart: {
1744 // Add the VarArgsOffset to the frame pointer, and copy it to the result.
1745 unsigned DestReg = getReg (CI);
1746 BuildMI (BB, V8::ADDri, 2, DestReg).addReg (V8::FP).addSImm (VarArgsOffset);
1750 case Intrinsic::vaend:
1751 // va_end is a no-op on SparcV8.
1754 case Intrinsic::vacopy: {
1755 // Copy the va_list ptr (arg1) to the result.
1756 unsigned DestReg = getReg (CI), SrcReg = getReg (CI.getOperand (1));
1757 BuildMI (BB, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
1763 void V8ISel::visitVANextInst (VANextInst &I) {
1764 // Add the type size to the vararg pointer (arg0).
1765 unsigned DestReg = getReg (I);
1766 unsigned SrcReg = getReg (I.getOperand (0));
1767 unsigned TySize = TM.getTargetData ().getTypeSize (I.getArgType ());
1768 BuildMI (BB, V8::ADDri, 2, DestReg).addReg (SrcReg).addSImm (TySize);
1771 void V8ISel::visitVAArgInst (VAArgInst &I) {
1772 unsigned VAList = getReg (I.getOperand (0));
1773 unsigned DestReg = getReg (I);
1775 switch (I.getType ()->getTypeID ()) {
1776 case Type::PointerTyID:
1777 case Type::UIntTyID:
1779 BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
1782 case Type::ULongTyID:
1783 case Type::LongTyID:
1784 BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
1785 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
1788 case Type::DoubleTyID: {
1789 unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
1790 unsigned TempReg = makeAnotherReg (Type::IntTy);
1791 unsigned TempReg2 = makeAnotherReg (Type::IntTy);
1792 int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
1793 BuildMI (BB, V8::LD, 2, TempReg).addReg (VAList).addSImm (0);
1794 BuildMI (BB, V8::LD, 2, TempReg2).addReg (VAList).addSImm (4);
1795 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
1796 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
1797 BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
1802 std::cerr << "Sorry, vaarg instruction of this type still unsupported:\n"