1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
37 // Pseudo instructions.
38 class PseudoInstV8<string nm> : InstV8 {
41 def PHI : PseudoInstV8<"PHI">;
42 def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN">;
43 def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">;
44 def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">;
45 def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">;
46 def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move
48 // Section A.3 - Synthetic Instructions, p. 85
49 // special cases of JMPL:
50 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
51 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
52 def RET : F3_2<2, 0b111000, "ret">;
53 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
54 def RETL: F3_2<2, 0b111000, "retl">;
56 // CMP is a special case of SUBCC where destination is ignored, by setting it to
57 // %g0 (hardwired zero).
58 // FIXME: should keep track of the fact that it defs the integer condition codes
60 def CMPri: F3_2<2, 0b010100, "cmp">;
62 // Section B.1 - Load Integer Instructions, p. 90
63 def LDSB: F3_2<3, 0b001001, "ldsb">;
64 def LDSH: F3_2<3, 0b001010, "ldsh">;
65 def LDUB: F3_2<3, 0b000001, "ldub">;
66 def LDUH: F3_2<3, 0b000010, "lduh">;
67 def LD : F3_2<3, 0b000000, "ld">;
68 def LDD : F3_2<3, 0b000011, "ldd">;
70 // Section B.2 - Load Floating-point Instructions, p. 92
71 def LDFrr : F3_1<3, 0b100000, "ld">;
72 def LDFri : F3_2<3, 0b100000, "ld">;
73 def LDDFrr : F3_1<3, 0b100011, "ldd">;
74 def LDDFri : F3_2<3, 0b100011, "ldd">;
75 def LDFSRrr: F3_1<3, 0b100001, "ld">;
76 def LDFSRri: F3_2<3, 0b100001, "ld">;
78 // Section B.4 - Store Integer Instructions, p. 95
79 def STB : F3_2<3, 0b000101, "stb">;
80 def STH : F3_2<3, 0b000110, "sth">;
81 def ST : F3_2<3, 0b000100, "st">;
82 def STD : F3_2<3, 0b000111, "std">;
84 // Section B.5 - Store Floating-point Instructions, p. 97
85 def STFrr : F3_1<3, 0b100100, "st">;
86 def STFri : F3_2<3, 0b100100, "st">;
87 def STDFrr : F3_1<3, 0b100111, "std">;
88 def STDFri : F3_2<3, 0b100111, "std">;
89 def STFSRrr : F3_1<3, 0b100101, "st">;
90 def STFSRri : F3_2<3, 0b100101, "st">;
91 def STDFQrr : F3_1<3, 0b100110, "std">;
92 def STDFQri : F3_2<3, 0b100110, "std">;
94 // Section B.9 - SETHI Instruction, p. 104
95 def SETHIi: F2_1<0b100, "sethi">;
97 // Section B.10 - NOP Instruction, p. 105
98 // (It's a special case of SETHI)
99 let rd = 0, imm22 = 0 in
100 def NOP : F2_1<0b100, "nop">;
102 // Section B.11 - Logical Instructions, p. 106
103 def ANDrr : F3_1<2, 0b000001, "and">;
104 def ANDri : F3_2<2, 0b000001, "and">;
105 def ANDCCrr : F3_1<2, 0b010001, "andcc">;
106 def ANDCCri : F3_2<2, 0b010001, "andcc">;
107 def ANDNrr : F3_1<2, 0b000101, "andn">;
108 def ANDNri : F3_2<2, 0b000101, "andn">;
109 def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
110 def ANDNCCri: F3_2<2, 0b010101, "andncc">;
111 def ORrr : F3_1<2, 0b000010, "or">;
112 def ORri : F3_2<2, 0b000010, "or">;
113 def ORCCrr : F3_1<2, 0b010010, "orcc">;
114 def ORCCri : F3_2<2, 0b010010, "orcc">;
115 def ORNrr : F3_1<2, 0b000110, "orn">;
116 def ORNri : F3_2<2, 0b000110, "orn">;
117 def ORNCCrr : F3_1<2, 0b010110, "orncc">;
118 def ORNCCri : F3_2<2, 0b010110, "orncc">;
119 def XORrr : F3_1<2, 0b000011, "xor">;
120 def XORri : F3_2<2, 0b000011, "xor">;
121 def XORCCrr : F3_1<2, 0b010011, "xorcc">;
122 def XORCCri : F3_2<2, 0b010011, "xorcc">;
123 def XNORrr : F3_1<2, 0b000111, "xnor">;
124 def XNORri : F3_2<2, 0b000111, "xnor">;
125 def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
126 def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
128 // Section B.12 - Shift Instructions, p. 107
129 def SLLrr : F3_1<2, 0b100101, "sll">;
130 def SLLri : F3_2<2, 0b100101, "sll">;
131 def SRLrr : F3_1<2, 0b100110, "srl">;
132 def SRLri : F3_2<2, 0b100110, "srl">;
133 def SRArr : F3_1<2, 0b100111, "sra">;
134 def SRAri : F3_2<2, 0b100111, "sra">;
136 // Section B.13 - Add Instructions, p. 108
137 def ADDrr : F3_1<2, 0b000000, "add">;
138 def ADDri : F3_2<2, 0b000000, "add">;
139 def ADDCCrr : F3_1<2, 0b010000, "addcc">;
140 def ADDCCri : F3_2<2, 0b010000, "addcc">;
141 def ADDXrr : F3_1<2, 0b001000, "addx">;
142 def ADDXri : F3_2<2, 0b001000, "addx">;
143 def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
144 def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
146 // Section B.15 - Subtract Instructions, p. 110
147 def SUBrr : F3_1<2, 0b000100, "sub">;
148 def SUBri : F3_2<2, 0b000100, "sub">;
149 def SUBCCrr : F3_1<2, 0b010100, "subcc">;
150 def SUBCCri : F3_2<2, 0b010100, "subcc">;
151 def SUBXrr : F3_1<2, 0b001100, "subx">;
152 def SUBXri : F3_2<2, 0b001100, "subx">;
153 def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
154 def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
156 // Section B.18 - Multiply Instructions, p. 113
157 def UMULrr : F3_1<2, 0b001010, "umul">;
158 def SMULrr : F3_1<2, 0b001011, "smul">;
160 // Section B.19 - Divide Instructions, p. 115
161 def UDIVrr : F3_1<2, 0b001110, "udiv">;
162 def UDIVri : F3_2<2, 0b001110, "udiv">;
163 def SDIVrr : F3_1<2, 0b001111, "sdiv">;
164 def SDIVri : F3_2<2, 0b001111, "sdiv">;
165 def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
166 def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
167 def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
168 def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
170 // Section B.20 - SAVE and RESTORE, p. 117
171 def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
172 def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
173 def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
174 def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
176 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
178 // conditional branch class:
179 class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
181 let isTerminator = 1;
182 let hasDelaySlot = 1;
186 def BA : BranchV8<0b1000, "ba">;
187 def BN : BranchV8<0b0000, "bn">;
188 def BNE : BranchV8<0b1001, "bne">;
189 def BE : BranchV8<0b0001, "be">;
190 def BG : BranchV8<0b1010, "bg">;
191 def BLE : BranchV8<0b0010, "ble">;
192 def BGE : BranchV8<0b1011, "bge">;
193 def BL : BranchV8<0b0011, "bl">;
194 def BGU : BranchV8<0b1100, "bgu">;
195 def BLEU : BranchV8<0b0100, "bleu">;
196 def BCC : BranchV8<0b1101, "bcc">;
197 def BCS : BranchV8<0b0101, "bcs">;
199 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
201 // floating-point conditional branch class:
202 class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
204 let isTerminator = 1;
205 let hasDelaySlot = 1;
208 def FBA : FPBranchV8<0b1000, "fba">;
209 def FBN : FPBranchV8<0b0000, "fbn">;
210 def FBU : FPBranchV8<0b0111, "fbu">;
211 def FBG : FPBranchV8<0b0110, "fbg">;
212 def FBUG : FPBranchV8<0b0101, "fbug">;
213 def FBL : FPBranchV8<0b0100, "fbl">;
214 def FBUL : FPBranchV8<0b0011, "fbul">;
215 def FBLG : FPBranchV8<0b0010, "fblg">;
216 def FBNE : FPBranchV8<0b0001, "fbne">;
217 def FBE : FPBranchV8<0b1001, "fbe">;
218 def FBUE : FPBranchV8<0b1010, "fbue">;
219 def FBGE : FPBranchV8<0b1011, "fbge">;
220 def FBUGE: FPBranchV8<0b1100, "fbuge">;
221 def FBLE : FPBranchV8<0b1101, "fble">;
222 def FBULE: FPBranchV8<0b1110, "fbule">;
223 def FBO : FPBranchV8<0b1111, "fbo">;
227 // Section B.24 - Call and Link Instruction, p. 125
228 // This is the only Format 1 instruction
229 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
231 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
232 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
236 let Inst{29-0} = disp;
240 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
241 // be an implicit def):
242 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
243 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
244 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
247 // Section B.29 - Write State Register Instructions
248 def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
249 def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
251 // Convert Integer to Floating-point Instructions, p. 141
252 def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
253 def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">;
255 // Convert Floating-point to Integer Instructions, p. 142
256 def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">;
257 def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">;
259 // Convert between Floating-point Formats Instructions, p. 143
260 def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">;
261 def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">;
263 // Floating-point Move Instructions, p. 144
264 def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">;
265 def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">;
266 def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">;
268 // Floating-point Add and Subtract Instructions, p. 146
269 def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">;
270 def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">;
271 def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">;
272 def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">;
274 // Floating-point Multiply and Divide Instructions, p. 147
275 def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">;
276 def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">;
277 def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">;
278 def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">;
279 def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
281 // Floating-point Compare Instructions, p. 148
282 // Note: the 2nd template arg is different for these guys.
283 // Note 2: the result of a FCMP is not available until the 2nd cycle
284 // after the instr is retired, but there is no interlock. This behavior
285 // is modelled as a delay slot.
286 let hasDelaySlot = 1 in {
287 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
288 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
289 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
290 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;