1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 def LO10 : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
46 def HI22 : SDNodeXForm<imm, [{
47 // Transformation function: shift the immediate value down into the low bits.
48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
51 def SETHIimm : PatLeaf<(imm), [{
52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
56 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
57 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
60 def MEMrr : Operand<i32> {
61 let PrintMethod = "printMemOperand";
62 let NumMIOperands = 2;
63 let MIOperandInfo = (ops IntRegs, IntRegs);
65 def MEMri : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let NumMIOperands = 2;
68 let MIOperandInfo = (ops IntRegs, i32imm);
71 // Branch targets have OtherVT type.
72 def brtarget : Operand<OtherVT>;
75 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
77 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
79 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
80 SDTCisVT<2, FlagVT>]>;
82 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
83 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
84 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
85 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
88 //===----------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
92 // Pseudo instructions.
93 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
94 let AsmString = asmstr;
95 dag OperandList = ops;
97 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
98 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
100 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
102 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
103 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
105 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
107 // Section A.3 - Synthetic Instructions, p. 85
108 // special cases of JMPL:
109 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
110 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
111 def RETL: F3_2<2, 0b111000, (ops),
115 // Section B.1 - Load Integer Instructions, p. 90
116 def LDSBrr : F3_1<3, 0b001001,
117 (ops IntRegs:$dst, MEMrr:$addr),
118 "ldsb [$addr], $dst",
119 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
120 def LDSBri : F3_2<3, 0b001001,
121 (ops IntRegs:$dst, MEMri:$addr),
122 "ldsb [$addr], $dst",
123 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
124 def LDSHrr : F3_1<3, 0b001010,
125 (ops IntRegs:$dst, MEMrr:$addr),
126 "ldsh [$addr], $dst",
127 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
128 def LDSHri : F3_2<3, 0b001010,
129 (ops IntRegs:$dst, MEMri:$addr),
130 "ldsh [$addr], $dst",
131 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
132 def LDUBrr : F3_1<3, 0b000001,
133 (ops IntRegs:$dst, MEMrr:$addr),
134 "ldub [$addr], $dst",
135 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
136 def LDUBri : F3_2<3, 0b000001,
137 (ops IntRegs:$dst, MEMri:$addr),
138 "ldub [$addr], $dst",
139 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
140 def LDUHrr : F3_1<3, 0b000010,
141 (ops IntRegs:$dst, MEMrr:$addr),
142 "lduh [$addr], $dst",
143 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
144 def LDUHri : F3_2<3, 0b000010,
145 (ops IntRegs:$dst, MEMri:$addr),
146 "lduh [$addr], $dst",
147 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
148 def LDrr : F3_1<3, 0b000000,
149 (ops IntRegs:$dst, MEMrr:$addr),
151 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
152 def LDri : F3_2<3, 0b000000,
153 (ops IntRegs:$dst, MEMri:$addr),
155 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
156 def LDDrr : F3_1<3, 0b000011,
157 (ops IntRegs:$dst, MEMrr:$addr),
158 "ldd [$addr], $dst", []>;
159 def LDDri : F3_2<3, 0b000011,
160 (ops IntRegs:$dst, MEMri:$addr),
161 "ldd [$addr], $dst", []>;
163 // Section B.2 - Load Floating-point Instructions, p. 92
164 def LDFrr : F3_1<3, 0b100000,
165 (ops FPRegs:$dst, MEMrr:$addr),
167 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
168 def LDFri : F3_2<3, 0b100000,
169 (ops FPRegs:$dst, MEMri:$addr),
171 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
172 def LDDFrr : F3_1<3, 0b100011,
173 (ops DFPRegs:$dst, MEMrr:$addr),
175 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
176 def LDDFri : F3_2<3, 0b100011,
177 (ops DFPRegs:$dst, MEMri:$addr),
179 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
181 // Section B.4 - Store Integer Instructions, p. 95
182 def STBrr : F3_1<3, 0b000101,
183 (ops MEMrr:$addr, IntRegs:$src),
185 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
186 def STBri : F3_2<3, 0b000101,
187 (ops MEMri:$addr, IntRegs:$src),
189 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
190 def STHrr : F3_1<3, 0b000110,
191 (ops MEMrr:$addr, IntRegs:$src),
193 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
194 def STHri : F3_2<3, 0b000110,
195 (ops MEMri:$addr, IntRegs:$src),
197 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
198 def STrr : F3_1<3, 0b000100,
199 (ops MEMrr:$addr, IntRegs:$src),
201 [(store IntRegs:$src, ADDRrr:$addr)]>;
202 def STri : F3_2<3, 0b000100,
203 (ops MEMri:$addr, IntRegs:$src),
205 [(store IntRegs:$src, ADDRri:$addr)]>;
206 def STDrr : F3_1<3, 0b000111,
207 (ops MEMrr:$addr, IntRegs:$src),
208 "std $src, [$addr]", []>;
209 def STDri : F3_2<3, 0b000111,
210 (ops MEMri:$addr, IntRegs:$src),
211 "std $src, [$addr]", []>;
213 // Section B.5 - Store Floating-point Instructions, p. 97
214 def STFrr : F3_1<3, 0b100100,
215 (ops MEMrr:$addr, FPRegs:$src),
217 [(store FPRegs:$src, ADDRrr:$addr)]>;
218 def STFri : F3_2<3, 0b100100,
219 (ops MEMri:$addr, FPRegs:$src),
221 [(store FPRegs:$src, ADDRri:$addr)]>;
222 def STDFrr : F3_1<3, 0b100111,
223 (ops MEMrr:$addr, DFPRegs:$src),
225 [(store DFPRegs:$src, ADDRrr:$addr)]>;
226 def STDFri : F3_2<3, 0b100111,
227 (ops MEMri:$addr, DFPRegs:$src),
229 [(store DFPRegs:$src, ADDRri:$addr)]>;
231 // Section B.9 - SETHI Instruction, p. 104
232 def SETHIi: F2_1<0b100,
233 (ops IntRegs:$dst, i32imm:$src),
235 [(set IntRegs:$dst, SETHIimm:$src)]>;
237 // Section B.10 - NOP Instruction, p. 105
238 // (It's a special case of SETHI)
239 let rd = 0, imm22 = 0 in
240 def NOP : F2_1<0b100, (ops), "nop", []>;
242 // Section B.11 - Logical Instructions, p. 106
243 def ANDrr : F3_1<2, 0b000001,
244 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
246 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
247 def ANDri : F3_2<2, 0b000001,
248 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
250 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
251 def ANDNrr : F3_1<2, 0b000101,
252 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
254 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
255 def ANDNri : F3_2<2, 0b000101,
256 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
257 "andn $b, $c, $dst", []>;
258 def ORrr : F3_1<2, 0b000010,
259 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
261 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
262 def ORri : F3_2<2, 0b000010,
263 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
265 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
266 def ORNrr : F3_1<2, 0b000110,
267 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
269 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
270 def ORNri : F3_2<2, 0b000110,
271 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
272 "orn $b, $c, $dst", []>;
273 def XORrr : F3_1<2, 0b000011,
274 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
276 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
277 def XORri : F3_2<2, 0b000011,
278 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
280 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
281 def XNORrr : F3_1<2, 0b000111,
282 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
284 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
285 def XNORri : F3_2<2, 0b000111,
286 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
287 "xnor $b, $c, $dst", []>;
289 // Section B.12 - Shift Instructions, p. 107
290 def SLLrr : F3_1<2, 0b100101,
291 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
293 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
294 def SLLri : F3_2<2, 0b100101,
295 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
297 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
298 def SRLrr : F3_1<2, 0b100110,
299 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
301 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
302 def SRLri : F3_2<2, 0b100110,
303 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
305 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
306 def SRArr : F3_1<2, 0b100111,
307 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
309 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
310 def SRAri : F3_2<2, 0b100111,
311 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
313 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
315 // Section B.13 - Add Instructions, p. 108
316 def ADDrr : F3_1<2, 0b000000,
317 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
319 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
320 def ADDri : F3_2<2, 0b000000,
321 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
323 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
324 def ADDCCrr : F3_1<2, 0b010000,
325 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
326 "addcc $b, $c, $dst", []>;
327 def ADDCCri : F3_2<2, 0b010000,
328 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
329 "addcc $b, $c, $dst", []>;
330 def ADDXrr : F3_1<2, 0b001000,
331 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
332 "addx $b, $c, $dst", []>;
333 def ADDXri : F3_2<2, 0b001000,
334 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
335 "addx $b, $c, $dst", []>;
337 // Section B.15 - Subtract Instructions, p. 110
338 def SUBrr : F3_1<2, 0b000100,
339 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
341 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
342 def SUBri : F3_2<2, 0b000100,
343 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
345 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
346 def SUBXrr : F3_1<2, 0b001100,
347 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
348 "subx $b, $c, $dst", []>;
349 def SUBXri : F3_2<2, 0b001100,
350 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
351 "subx $b, $c, $dst", []>;
352 def SUBCCrr : F3_1<2, 0b010100,
353 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
354 "subcc $b, $c, $dst", []>;
355 def SUBCCri : F3_2<2, 0b010100,
356 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
357 "subcc $b, $c, $dst", []>;
358 def SUBXCCrr: F3_1<2, 0b011100,
359 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
360 "subxcc $b, $c, $dst", []>;
362 // Section B.18 - Multiply Instructions, p. 113
363 def UMULrr : F3_1<2, 0b001010,
364 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
365 "umul $b, $c, $dst", []>;
366 def UMULri : F3_2<2, 0b001010,
367 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
368 "umul $b, $c, $dst", []>;
369 def SMULrr : F3_1<2, 0b001011,
370 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
372 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
373 def SMULri : F3_2<2, 0b001011,
374 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
376 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
378 // Section B.19 - Divide Instructions, p. 115
379 def UDIVrr : F3_1<2, 0b001110,
380 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
381 "udiv $b, $c, $dst", []>;
382 def UDIVri : F3_2<2, 0b001110,
383 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
384 "udiv $b, $c, $dst", []>;
385 def SDIVrr : F3_1<2, 0b001111,
386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
387 "sdiv $b, $c, $dst", []>;
388 def SDIVri : F3_2<2, 0b001111,
389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
390 "sdiv $b, $c, $dst", []>;
392 // Section B.20 - SAVE and RESTORE, p. 117
393 def SAVErr : F3_1<2, 0b111100,
394 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
395 "save $b, $c, $dst", []>;
396 def SAVEri : F3_2<2, 0b111100,
397 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
398 "save $b, $c, $dst", []>;
399 def RESTORErr : F3_1<2, 0b111101,
400 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
401 "restore $b, $c, $dst", []>;
402 def RESTOREri : F3_2<2, 0b111101,
403 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
404 "restore $b, $c, $dst", []>;
406 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
408 // conditional branch class:
409 class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
410 : F2_2<cc, 0b010, ops, asmstr, pattern> {
412 let isTerminator = 1;
413 let hasDelaySlot = 1;
417 def BA : BranchV8<0b1000, (ops brtarget:$dst),
420 def BNE : BranchV8<0b1001, (ops brtarget:$dst),
422 [(V8bricc bb:$dst, SETNE, ICC)]>;
423 def BE : BranchV8<0b0001, (ops brtarget:$dst),
425 [(V8bricc bb:$dst, SETEQ, ICC)]>;
426 def BG : BranchV8<0b1010, (ops brtarget:$dst),
428 [(V8bricc bb:$dst, SETGT, ICC)]>;
429 def BLE : BranchV8<0b0010, (ops brtarget:$dst),
431 [(V8bricc bb:$dst, SETLE, ICC)]>;
432 def BGE : BranchV8<0b1011, (ops brtarget:$dst),
434 [(V8bricc bb:$dst, SETGE, ICC)]>;
435 def BL : BranchV8<0b0011, (ops brtarget:$dst),
437 [(V8bricc bb:$dst, SETLT, ICC)]>;
438 def BGU : BranchV8<0b1100, (ops brtarget:$dst),
440 [(V8bricc bb:$dst, SETUGT, ICC)]>;
441 def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
443 [(V8bricc bb:$dst, SETULE, ICC)]>;
444 def BCC : BranchV8<0b1101, (ops brtarget:$dst),
446 [(V8bricc bb:$dst, SETUGE, ICC)]>;
447 def BCS : BranchV8<0b0101, (ops brtarget:$dst),
449 [(V8bricc bb:$dst, SETULT, ICC)]>;
451 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
453 // floating-point conditional branch class:
454 class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
455 : F2_2<cc, 0b110, ops, asmstr, pattern> {
457 let isTerminator = 1;
458 let hasDelaySlot = 1;
461 def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
463 [(V8brfcc bb:$dst, SETUO, FCC)]>;
464 def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
466 [(V8brfcc bb:$dst, SETGT, FCC)]>;
467 def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
469 [(V8brfcc bb:$dst, SETUGT, FCC)]>;
470 def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
472 [(V8brfcc bb:$dst, SETLT, FCC)]>;
473 def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
475 [(V8brfcc bb:$dst, SETULT, FCC)]>;
476 def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
478 [(V8brfcc bb:$dst, SETONE, FCC)]>;
479 def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
481 [(V8brfcc bb:$dst, SETNE, FCC)]>;
482 def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
484 [(V8brfcc bb:$dst, SETEQ, FCC)]>;
485 def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
487 [(V8brfcc bb:$dst, SETUEQ, FCC)]>;
488 def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
490 [(V8brfcc bb:$dst, SETGE, FCC)]>;
491 def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
493 [(V8brfcc bb:$dst, SETUGE, FCC)]>;
494 def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
496 [(V8brfcc bb:$dst, SETLE, FCC)]>;
497 def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
499 [(V8brfcc bb:$dst, SETULE, FCC)]>;
500 def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
502 [(V8brfcc bb:$dst, SETO, FCC)]>;
506 // Section B.24 - Call and Link Instruction, p. 125
507 // This is the only Format 1 instruction
508 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
510 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
511 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
513 let OperandList = (ops IntRegs:$dst);
516 let Inst{29-0} = disp;
517 let AsmString = "call $dst";
520 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
521 // be an implicit def):
522 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
523 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
524 def JMPLrr : F3_1<2, 0b111000,
525 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
526 "jmpl $b+$c, $dst", []>;
529 // Section B.28 - Read State Register Instructions
530 def RDY : F3_1<2, 0b101000,
534 // Section B.29 - Write State Register Instructions
535 def WRYrr : F3_1<2, 0b110000,
536 (ops IntRegs:$b, IntRegs:$c),
537 "wr $b, $c, %y", []>;
538 def WRYri : F3_2<2, 0b110000,
539 (ops IntRegs:$b, i32imm:$c),
540 "wr $b, $c, %y", []>;
542 // Convert Integer to Floating-point Instructions, p. 141
543 def FITOS : F3_3<2, 0b110100, 0b011000100,
544 (ops FPRegs:$dst, FPRegs:$src),
545 "fitos $src, $dst", []>;
546 def FITOD : F3_3<2, 0b110100, 0b011001000,
547 (ops DFPRegs:$dst, DFPRegs:$src),
548 "fitod $src, $dst", []>;
550 // Convert Floating-point to Integer Instructions, p. 142
551 def FSTOI : F3_3<2, 0b110100, 0b011010001,
552 (ops FPRegs:$dst, FPRegs:$src),
553 "fstoi $src, $dst", []>;
554 def FDTOI : F3_3<2, 0b110100, 0b011010010,
555 (ops DFPRegs:$dst, DFPRegs:$src),
556 "fdtoi $src, $dst", []>;
558 // Convert between Floating-point Formats Instructions, p. 143
559 def FSTOD : F3_3<2, 0b110100, 0b011001001,
560 (ops DFPRegs:$dst, FPRegs:$src),
562 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
563 def FDTOS : F3_3<2, 0b110100, 0b011000110,
564 (ops FPRegs:$dst, DFPRegs:$src),
566 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
568 // Floating-point Move Instructions, p. 144
569 def FMOVS : F3_3<2, 0b110100, 0b000000001,
570 (ops FPRegs:$dst, FPRegs:$src),
571 "fmovs $src, $dst", []>;
572 def FNEGS : F3_3<2, 0b110100, 0b000000101,
573 (ops FPRegs:$dst, FPRegs:$src),
575 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
576 def FABSS : F3_3<2, 0b110100, 0b000001001,
577 (ops FPRegs:$dst, FPRegs:$src),
579 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
580 // FIXME: ADD FNEGD/FABSD pseudo instructions.
583 // Floating-point Square Root Instructions, p.145
584 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
585 (ops FPRegs:$dst, FPRegs:$src),
587 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
588 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
589 (ops DFPRegs:$dst, DFPRegs:$src),
591 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
595 // Floating-point Add and Subtract Instructions, p. 146
596 def FADDS : F3_3<2, 0b110100, 0b001000001,
597 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
598 "fadds $src1, $src2, $dst",
599 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
600 def FADDD : F3_3<2, 0b110100, 0b001000010,
601 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
602 "faddd $src1, $src2, $dst",
603 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
604 def FSUBS : F3_3<2, 0b110100, 0b001000101,
605 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
606 "fsubs $src1, $src2, $dst",
607 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
608 def FSUBD : F3_3<2, 0b110100, 0b001000110,
609 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
610 "fsubd $src1, $src2, $dst",
611 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
613 // Floating-point Multiply and Divide Instructions, p. 147
614 def FMULS : F3_3<2, 0b110100, 0b001001001,
615 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
616 "fmuls $src1, $src2, $dst",
617 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
618 def FMULD : F3_3<2, 0b110100, 0b001001010,
619 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
620 "fmuld $src1, $src2, $dst",
621 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
622 def FSMULD : F3_3<2, 0b110100, 0b001101001,
623 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
624 "fsmuld $src1, $src2, $dst",
625 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
626 (fextend FPRegs:$src2)))]>;
627 def FDIVS : F3_3<2, 0b110100, 0b001001101,
628 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
629 "fdivs $src1, $src2, $dst",
630 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
631 def FDIVD : F3_3<2, 0b110100, 0b001001110,
632 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
633 "fdivd $src1, $src2, $dst",
634 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
636 // Floating-point Compare Instructions, p. 148
637 // Note: the 2nd template arg is different for these guys.
638 // Note 2: the result of a FCMP is not available until the 2nd cycle
639 // after the instr is retired, but there is no interlock. This behavior
640 // is modelled with a forced noop after the instruction.
641 def FCMPS : F3_3<2, 0b110101, 0b001010001,
642 (ops FPRegs:$src1, FPRegs:$src2),
643 "fcmps $src1, $src2\n\tnop",
644 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
645 def FCMPD : F3_3<2, 0b110101, 0b001010010,
646 (ops DFPRegs:$src1, DFPRegs:$src2),
647 "fcmpd $src1, $src2\n\tnop",
648 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
650 //===----------------------------------------------------------------------===//
651 // Non-Instruction Patterns
652 //===----------------------------------------------------------------------===//
655 def : Pat<(i32 simm13:$val),
656 (ORri G0, imm:$val)>;
657 // Arbitrary immediates.
658 def : Pat<(i32 imm:$val),
659 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;