1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 def LO10 : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
46 def HI22 : SDNodeXForm<imm, [{
47 // Transformation function: shift the immediate value down into the low bits.
48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
51 def SETHIimm : PatLeaf<(imm), [{
52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
56 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
57 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
60 def MEMrr : Operand<i32> {
61 let PrintMethod = "printMemOperand";
62 let NumMIOperands = 2;
63 let MIOperandInfo = (ops IntRegs, IntRegs);
65 def MEMri : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let NumMIOperands = 2;
68 let MIOperandInfo = (ops IntRegs, i32imm);
71 //===----------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
75 // Pseudo instructions.
76 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
77 let AsmString = asmstr;
78 dag OperandList = ops;
80 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
81 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
83 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
85 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
86 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
88 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
90 // Section A.3 - Synthetic Instructions, p. 85
91 // special cases of JMPL:
92 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
93 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
94 def RETL: F3_2<2, 0b111000, (ops),
97 // CMP is a special case of SUBCC where destination is ignored, by setting it to
98 // %g0 (hardwired zero).
99 // FIXME: should keep track of the fact that it defs the integer condition codes
101 def CMPri: F3_2<2, 0b010100,
102 (ops IntRegs:$b, i32imm:$c),
105 // Section B.1 - Load Integer Instructions, p. 90
106 def LDSBrr : F3_1<3, 0b001001,
107 (ops IntRegs:$dst, MEMrr:$addr),
108 "ldsb [$addr], $dst",
109 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
110 def LDSBri : F3_2<3, 0b001001,
111 (ops IntRegs:$dst, MEMri:$addr),
112 "ldsb [$addr], $dst",
113 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
114 def LDSHrr : F3_1<3, 0b001010,
115 (ops IntRegs:$dst, MEMrr:$addr),
116 "ldsh [$addr], $dst",
117 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
118 def LDSHri : F3_2<3, 0b001010,
119 (ops IntRegs:$dst, MEMri:$addr),
120 "ldsh [$addr], $dst",
121 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
122 def LDUBrr : F3_1<3, 0b000001,
123 (ops IntRegs:$dst, MEMrr:$addr),
124 "ldub [$addr], $dst",
125 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
126 def LDUBri : F3_2<3, 0b000001,
127 (ops IntRegs:$dst, MEMri:$addr),
128 "ldub [$addr], $dst",
129 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
130 def LDUHrr : F3_1<3, 0b000010,
131 (ops IntRegs:$dst, MEMrr:$addr),
132 "lduh [$addr], $dst",
133 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
134 def LDUHri : F3_2<3, 0b000010,
135 (ops IntRegs:$dst, MEMri:$addr),
136 "lduh [$addr], $dst",
137 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
138 def LDrr : F3_1<3, 0b000000,
139 (ops IntRegs:$dst, MEMrr:$addr),
141 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
142 def LDri : F3_2<3, 0b000000,
143 (ops IntRegs:$dst, MEMri:$addr),
145 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
146 def LDDrr : F3_1<3, 0b000011,
147 (ops IntRegs:$dst, MEMrr:$addr),
148 "ldd [$addr], $dst", []>;
149 def LDDri : F3_2<3, 0b000011,
150 (ops IntRegs:$dst, MEMri:$addr),
151 "ldd [$addr], $dst", []>;
153 // Section B.2 - Load Floating-point Instructions, p. 92
154 def LDFrr : F3_1<3, 0b100000,
155 (ops FPRegs:$dst, MEMrr:$addr),
157 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
158 def LDFri : F3_2<3, 0b100000,
159 (ops FPRegs:$dst, MEMri:$addr),
161 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
162 def LDDFrr : F3_1<3, 0b100011,
163 (ops DFPRegs:$dst, MEMrr:$addr),
165 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
166 def LDDFri : F3_2<3, 0b100011,
167 (ops DFPRegs:$dst, MEMri:$addr),
169 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
171 // Section B.4 - Store Integer Instructions, p. 95
172 def STBrr : F3_1<3, 0b000101,
173 (ops MEMrr:$addr, IntRegs:$src),
175 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
176 def STBri : F3_2<3, 0b000101,
177 (ops MEMri:$addr, IntRegs:$src),
179 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
180 def STHrr : F3_1<3, 0b000110,
181 (ops MEMrr:$addr, IntRegs:$src),
183 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
184 def STHri : F3_2<3, 0b000110,
185 (ops MEMri:$addr, IntRegs:$src),
187 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
188 def STrr : F3_1<3, 0b000100,
189 (ops MEMrr:$addr, IntRegs:$src),
191 [(store IntRegs:$src, ADDRrr:$addr)]>;
192 def STri : F3_2<3, 0b000100,
193 (ops MEMri:$addr, IntRegs:$src),
195 [(store IntRegs:$src, ADDRri:$addr)]>;
196 def STDrr : F3_1<3, 0b000111,
197 (ops MEMrr:$addr, IntRegs:$src),
198 "std $src, [$addr]", []>;
199 def STDri : F3_2<3, 0b000111,
200 (ops MEMri:$addr, IntRegs:$src),
201 "std $src, [$addr]", []>;
203 // Section B.5 - Store Floating-point Instructions, p. 97
204 def STFrr : F3_1<3, 0b100100,
205 (ops MEMrr:$addr, FPRegs:$src),
207 [(store FPRegs:$src, ADDRrr:$addr)]>;
208 def STFri : F3_2<3, 0b100100,
209 (ops MEMri:$addr, FPRegs:$src),
211 [(store FPRegs:$src, ADDRri:$addr)]>;
212 def STDFrr : F3_1<3, 0b100111,
213 (ops MEMrr:$addr, DFPRegs:$src),
215 [(store DFPRegs:$src, ADDRrr:$addr)]>;
216 def STDFri : F3_2<3, 0b100111,
217 (ops MEMri:$addr, DFPRegs:$src),
219 [(store DFPRegs:$src, ADDRri:$addr)]>;
221 // Section B.9 - SETHI Instruction, p. 104
222 def SETHIi: F2_1<0b100,
223 (ops IntRegs:$dst, i32imm:$src),
225 [(set IntRegs:$dst, SETHIimm:$src)]>;
227 // Section B.10 - NOP Instruction, p. 105
228 // (It's a special case of SETHI)
229 let rd = 0, imm22 = 0 in
230 def NOP : F2_1<0b100, (ops), "nop", []>;
232 // Section B.11 - Logical Instructions, p. 106
233 def ANDrr : F3_1<2, 0b000001,
234 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
236 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
237 def ANDri : F3_2<2, 0b000001,
238 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
240 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
241 def ANDNrr : F3_1<2, 0b000101,
242 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
244 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
245 def ANDNri : F3_2<2, 0b000101,
246 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
247 "andn $b, $c, $dst", []>;
248 def ORrr : F3_1<2, 0b000010,
249 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
251 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
252 def ORri : F3_2<2, 0b000010,
253 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
255 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
256 def ORNrr : F3_1<2, 0b000110,
257 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
259 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
260 def ORNri : F3_2<2, 0b000110,
261 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
262 "orn $b, $c, $dst", []>;
263 def XORrr : F3_1<2, 0b000011,
264 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
266 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
267 def XORri : F3_2<2, 0b000011,
268 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
270 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
271 def XNORrr : F3_1<2, 0b000111,
272 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
274 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
275 def XNORri : F3_2<2, 0b000111,
276 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
277 "xnor $b, $c, $dst", []>;
279 // Section B.12 - Shift Instructions, p. 107
280 def SLLrr : F3_1<2, 0b100101,
281 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
283 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
284 def SLLri : F3_2<2, 0b100101,
285 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
287 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
288 def SRLrr : F3_1<2, 0b100110,
289 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
291 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
292 def SRLri : F3_2<2, 0b100110,
293 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
295 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
296 def SRArr : F3_1<2, 0b100111,
297 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
299 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
300 def SRAri : F3_2<2, 0b100111,
301 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
303 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
305 // Section B.13 - Add Instructions, p. 108
306 def ADDrr : F3_1<2, 0b000000,
307 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
309 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
310 def ADDri : F3_2<2, 0b000000,
311 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
313 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
314 def ADDCCrr : F3_1<2, 0b010000,
315 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
316 "addcc $b, $c, $dst", []>;
317 def ADDCCri : F3_2<2, 0b010000,
318 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
319 "addcc $b, $c, $dst", []>;
320 def ADDXrr : F3_1<2, 0b001000,
321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
322 "addx $b, $c, $dst", []>;
323 def ADDXri : F3_2<2, 0b001000,
324 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
325 "addx $b, $c, $dst", []>;
327 // Section B.15 - Subtract Instructions, p. 110
328 def SUBrr : F3_1<2, 0b000100,
329 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
331 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
332 def SUBri : F3_2<2, 0b000100,
333 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
335 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
336 def SUBXrr : F3_1<2, 0b001100,
337 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
338 "subx $b, $c, $dst", []>;
339 def SUBXri : F3_2<2, 0b001100,
340 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
341 "subx $b, $c, $dst", []>;
342 def SUBCCrr : F3_1<2, 0b010100,
343 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
344 "subcc $b, $c, $dst", []>;
345 def SUBCCri : F3_2<2, 0b010100,
346 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
347 "subcc $b, $c, $dst", []>;
348 def SUBXCCrr: F3_1<2, 0b011100,
349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
350 "subxcc $b, $c, $dst", []>;
352 // Section B.18 - Multiply Instructions, p. 113
353 def UMULrr : F3_1<2, 0b001010,
354 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
355 "umul $b, $c, $dst", []>;
356 def UMULri : F3_2<2, 0b001010,
357 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
358 "umul $b, $c, $dst", []>;
359 def SMULrr : F3_1<2, 0b001011,
360 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
362 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
363 def SMULri : F3_2<2, 0b001011,
364 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
366 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
368 // Section B.19 - Divide Instructions, p. 115
369 def UDIVrr : F3_1<2, 0b001110,
370 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
371 "udiv $b, $c, $dst", []>;
372 def UDIVri : F3_2<2, 0b001110,
373 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
374 "udiv $b, $c, $dst", []>;
375 def SDIVrr : F3_1<2, 0b001111,
376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
377 "sdiv $b, $c, $dst", []>;
378 def SDIVri : F3_2<2, 0b001111,
379 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
380 "sdiv $b, $c, $dst", []>;
382 // Section B.20 - SAVE and RESTORE, p. 117
383 def SAVErr : F3_1<2, 0b111100,
384 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
385 "save $b, $c, $dst", []>;
386 def SAVEri : F3_2<2, 0b111100,
387 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
388 "save $b, $c, $dst", []>;
389 def RESTORErr : F3_1<2, 0b111101,
390 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
391 "restore $b, $c, $dst", []>;
392 def RESTOREri : F3_2<2, 0b111101,
393 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
394 "restore $b, $c, $dst", []>;
396 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
398 // conditional branch class:
399 class BranchV8<bits<4> cc, dag ops, string asmstr>
400 : F2_2<cc, 0b010, ops, asmstr> {
402 let isTerminator = 1;
403 let hasDelaySlot = 1;
407 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
408 def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
409 def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
410 def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
411 def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
412 def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
413 def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
414 def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
415 def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
416 def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
417 def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
418 def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
420 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
422 // floating-point conditional branch class:
423 class FPBranchV8<bits<4> cc, dag ops, string asmstr>
424 : F2_2<cc, 0b110, ops, asmstr> {
426 let isTerminator = 1;
427 let hasDelaySlot = 1;
430 def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
431 def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
432 def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
433 def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
434 def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
435 def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
436 def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
437 def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
438 def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
439 def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
440 def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
441 def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
442 def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
443 def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
444 def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
445 def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
449 // Section B.24 - Call and Link Instruction, p. 125
450 // This is the only Format 1 instruction
451 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
453 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
454 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
456 let OperandList = (ops IntRegs:$dst);
459 let Inst{29-0} = disp;
460 let AsmString = "call $dst";
463 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
464 // be an implicit def):
465 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
466 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
467 def JMPLrr : F3_1<2, 0b111000,
468 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
469 "jmpl $b+$c, $dst", []>;
472 // Section B.28 - Read State Register Instructions
473 def RDY : F3_1<2, 0b101000,
477 // Section B.29 - Write State Register Instructions
478 def WRYrr : F3_1<2, 0b110000,
479 (ops IntRegs:$b, IntRegs:$c),
480 "wr $b, $c, %y", []>;
481 def WRYri : F3_2<2, 0b110000,
482 (ops IntRegs:$b, i32imm:$c),
483 "wr $b, $c, %y", []>;
485 // Convert Integer to Floating-point Instructions, p. 141
486 def FITOS : F3_3<2, 0b110100, 0b011000100,
487 (ops FPRegs:$dst, FPRegs:$src),
488 "fitos $src, $dst", []>;
489 def FITOD : F3_3<2, 0b110100, 0b011001000,
490 (ops DFPRegs:$dst, DFPRegs:$src),
491 "fitod $src, $dst", []>;
493 // Convert Floating-point to Integer Instructions, p. 142
494 def FSTOI : F3_3<2, 0b110100, 0b011010001,
495 (ops FPRegs:$dst, FPRegs:$src),
496 "fstoi $src, $dst", []>;
497 def FDTOI : F3_3<2, 0b110100, 0b011010010,
498 (ops DFPRegs:$dst, DFPRegs:$src),
499 "fdtoi $src, $dst", []>;
501 // Convert between Floating-point Formats Instructions, p. 143
502 def FSTOD : F3_3<2, 0b110100, 0b011001001,
503 (ops DFPRegs:$dst, FPRegs:$src),
505 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
506 def FDTOS : F3_3<2, 0b110100, 0b011000110,
507 (ops FPRegs:$dst, DFPRegs:$src),
509 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
511 // Floating-point Move Instructions, p. 144
512 def FMOVS : F3_3<2, 0b110100, 0b000000001,
513 (ops FPRegs:$dst, FPRegs:$src),
514 "fmovs $src, $dst", []>;
515 def FNEGS : F3_3<2, 0b110100, 0b000000101,
516 (ops FPRegs:$dst, FPRegs:$src),
518 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
519 def FABSS : F3_3<2, 0b110100, 0b000001001,
520 (ops FPRegs:$dst, FPRegs:$src),
522 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
524 // Floating-point Square Root Instructions, p.145
525 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
526 (ops FPRegs:$dst, FPRegs:$src),
528 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
529 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
530 (ops DFPRegs:$dst, DFPRegs:$src),
532 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
536 // Floating-point Add and Subtract Instructions, p. 146
537 def FADDS : F3_3<2, 0b110100, 0b001000001,
538 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
539 "fadds $src1, $src2, $dst",
540 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
541 def FADDD : F3_3<2, 0b110100, 0b001000010,
542 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
543 "faddd $src1, $src2, $dst",
544 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
545 def FSUBS : F3_3<2, 0b110100, 0b001000101,
546 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
547 "fsubs $src1, $src2, $dst",
548 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
549 def FSUBD : F3_3<2, 0b110100, 0b001000110,
550 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
551 "fsubd $src1, $src2, $dst",
552 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
554 // Floating-point Multiply and Divide Instructions, p. 147
555 def FMULS : F3_3<2, 0b110100, 0b001001001,
556 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
557 "fmuls $src1, $src2, $dst",
558 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
559 def FMULD : F3_3<2, 0b110100, 0b001001010,
560 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
561 "fmuld $src1, $src2, $dst",
562 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
563 def FSMULD : F3_3<2, 0b110100, 0b001101001,
564 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
565 "fsmuld $src1, $src2, $dst",
566 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
567 (fextend FPRegs:$src2)))]>;
568 def FDIVS : F3_3<2, 0b110100, 0b001001101,
569 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
570 "fdivs $src1, $src2, $dst",
571 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
572 def FDIVD : F3_3<2, 0b110100, 0b001001110,
573 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
574 "fdivd $src1, $src2, $dst",
575 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
577 // Floating-point Compare Instructions, p. 148
578 // Note: the 2nd template arg is different for these guys.
579 // Note 2: the result of a FCMP is not available until the 2nd cycle
580 // after the instr is retired, but there is no interlock. This behavior
581 // is modelled with a forced noop after the instruction.
582 def FCMPS : F3_3<2, 0b110101, 0b001010001,
583 (ops FPRegs:$src1, FPRegs:$src2),
584 "fcmps $src1, $src2\n\tnop", []>;
585 def FCMPD : F3_3<2, 0b110101, 0b001010010,
586 (ops DFPRegs:$src1, DFPRegs:$src2),
587 "fcmpd $src1, $src2\n\tnop", []>;
589 //===----------------------------------------------------------------------===//
590 // Non-Instruction Patterns
591 //===----------------------------------------------------------------------===//
594 def : Pat<(i32 simm13:$val),
595 (ORri G0, imm:$val)>;
596 // Arbitrary immediates.
597 def : Pat<(i32 imm:$val),
598 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;