1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
37 // Pseudo instructions.
38 class PseudoInstV8<string nm, dag ops> : InstV8 {
40 dag OperandList = ops;
42 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
43 def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN", (ops variable_ops)>;
44 def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP", (ops variable_ops)>;
45 def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE", (ops variable_ops)>;
46 def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF", (ops variable_ops)>;
47 def FpMOVD : PseudoInstV8<"FpMOVD", (ops)>; // pseudo 64-bit double move
49 // Section A.3 - Synthetic Instructions, p. 85
50 // special cases of JMPL:
51 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
52 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
53 def RET : F3_2<2, 0b111000, "ret">;
54 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
55 def RETL: F3_2<2, 0b111000, "retl">;
57 // CMP is a special case of SUBCC where destination is ignored, by setting it to
58 // %g0 (hardwired zero).
59 // FIXME: should keep track of the fact that it defs the integer condition codes
61 def CMPri: F3_2<2, 0b010100, "cmp">;
63 // Section B.1 - Load Integer Instructions, p. 90
64 def LDSB: F3_2<3, 0b001001, "ldsb">;
65 def LDSH: F3_2<3, 0b001010, "ldsh">;
66 def LDUB: F3_2<3, 0b000001, "ldub">;
67 def LDUH: F3_2<3, 0b000010, "lduh">;
68 def LD : F3_2<3, 0b000000, "ld">;
69 def LDD : F3_2<3, 0b000011, "ldd">;
71 // Section B.2 - Load Floating-point Instructions, p. 92
72 def LDFrr : F3_1<3, 0b100000, "ld">;
73 def LDFri : F3_2<3, 0b100000, "ld">;
74 def LDDFrr : F3_1<3, 0b100011, "ldd">;
75 def LDDFri : F3_2<3, 0b100011, "ldd">;
76 def LDFSRrr: F3_1<3, 0b100001, "ld">;
77 def LDFSRri: F3_2<3, 0b100001, "ld">;
79 // Section B.4 - Store Integer Instructions, p. 95
80 def STB : F3_2<3, 0b000101, "stb">;
81 def STH : F3_2<3, 0b000110, "sth">;
82 def ST : F3_2<3, 0b000100, "st">;
83 def STD : F3_2<3, 0b000111, "std">;
85 // Section B.5 - Store Floating-point Instructions, p. 97
86 def STFrr : F3_1<3, 0b100100, "st">;
87 def STFri : F3_2<3, 0b100100, "st">;
88 def STDFrr : F3_1<3, 0b100111, "std">;
89 def STDFri : F3_2<3, 0b100111, "std">;
90 def STFSRrr : F3_1<3, 0b100101, "st">;
91 def STFSRri : F3_2<3, 0b100101, "st">;
92 def STDFQrr : F3_1<3, 0b100110, "std">;
93 def STDFQri : F3_2<3, 0b100110, "std">;
95 // Section B.9 - SETHI Instruction, p. 104
96 def SETHIi: F2_1<0b100, "sethi">;
98 // Section B.10 - NOP Instruction, p. 105
99 // (It's a special case of SETHI)
100 let rd = 0, imm22 = 0 in
101 def NOP : F2_1<0b100, "nop">;
103 // Section B.11 - Logical Instructions, p. 106
104 def ANDrr : F3_1<2, 0b000001, "and">;
105 def ANDri : F3_2<2, 0b000001, "and">;
106 def ANDCCrr : F3_1<2, 0b010001, "andcc">;
107 def ANDCCri : F3_2<2, 0b010001, "andcc">;
108 def ANDNrr : F3_1<2, 0b000101, "andn">;
109 def ANDNri : F3_2<2, 0b000101, "andn">;
110 def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
111 def ANDNCCri: F3_2<2, 0b010101, "andncc">;
112 def ORrr : F3_1<2, 0b000010, "or">;
113 def ORri : F3_2<2, 0b000010, "or">;
114 def ORCCrr : F3_1<2, 0b010010, "orcc">;
115 def ORCCri : F3_2<2, 0b010010, "orcc">;
116 def ORNrr : F3_1<2, 0b000110, "orn">;
117 def ORNri : F3_2<2, 0b000110, "orn">;
118 def ORNCCrr : F3_1<2, 0b010110, "orncc">;
119 def ORNCCri : F3_2<2, 0b010110, "orncc">;
120 def XORrr : F3_1<2, 0b000011, "xor">;
121 def XORri : F3_2<2, 0b000011, "xor">;
122 def XORCCrr : F3_1<2, 0b010011, "xorcc">;
123 def XORCCri : F3_2<2, 0b010011, "xorcc">;
124 def XNORrr : F3_1<2, 0b000111, "xnor">;
125 def XNORri : F3_2<2, 0b000111, "xnor">;
126 def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
127 def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
129 // Section B.12 - Shift Instructions, p. 107
130 def SLLrr : F3_1<2, 0b100101, "sll">;
131 def SLLri : F3_2<2, 0b100101, "sll">;
132 def SRLrr : F3_1<2, 0b100110, "srl">;
133 def SRLri : F3_2<2, 0b100110, "srl">;
134 def SRArr : F3_1<2, 0b100111, "sra">;
135 def SRAri : F3_2<2, 0b100111, "sra">;
137 // Section B.13 - Add Instructions, p. 108
138 def ADDrr : F3_1<2, 0b000000, "add">;
139 def ADDri : F3_2<2, 0b000000, "add">;
140 def ADDCCrr : F3_1<2, 0b010000, "addcc">;
141 def ADDCCri : F3_2<2, 0b010000, "addcc">;
142 def ADDXrr : F3_1<2, 0b001000, "addx">;
143 def ADDXri : F3_2<2, 0b001000, "addx">;
144 def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
145 def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
147 // Section B.15 - Subtract Instructions, p. 110
148 def SUBrr : F3_1<2, 0b000100, "sub">;
149 def SUBri : F3_2<2, 0b000100, "sub">;
150 def SUBCCrr : F3_1<2, 0b010100, "subcc">;
151 def SUBCCri : F3_2<2, 0b010100, "subcc">;
152 def SUBXrr : F3_1<2, 0b001100, "subx">;
153 def SUBXri : F3_2<2, 0b001100, "subx">;
154 def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
155 def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
157 // Section B.18 - Multiply Instructions, p. 113
158 def UMULrr : F3_1<2, 0b001010, "umul">;
159 def UMULri : F3_2<2, 0b001010, "umul">;
160 def SMULrr : F3_1<2, 0b001011, "smul">;
161 def SMULri : F3_2<2, 0b001011, "smul">;
162 def UMULCCrr: F3_1<2, 0b011010, "umulcc">;
163 def UMULCCri: F3_2<2, 0b011010, "umulcc">;
164 def SMULCCrr: F3_1<2, 0b011011, "smulcc">;
165 def SMULCCri: F3_2<2, 0b011011, "smulcc">;
167 // Section B.19 - Divide Instructions, p. 115
168 def UDIVrr : F3_1<2, 0b001110, "udiv">;
169 def UDIVri : F3_2<2, 0b001110, "udiv">;
170 def SDIVrr : F3_1<2, 0b001111, "sdiv">;
171 def SDIVri : F3_2<2, 0b001111, "sdiv">;
172 def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
173 def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
174 def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
175 def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
177 // Section B.20 - SAVE and RESTORE, p. 117
178 def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
179 def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
180 def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
181 def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
183 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
185 // conditional branch class:
186 class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
188 let isTerminator = 1;
189 let hasDelaySlot = 1;
193 def BA : BranchV8<0b1000, "ba">;
194 def BN : BranchV8<0b0000, "bn">;
195 def BNE : BranchV8<0b1001, "bne">;
196 def BE : BranchV8<0b0001, "be">;
197 def BG : BranchV8<0b1010, "bg">;
198 def BLE : BranchV8<0b0010, "ble">;
199 def BGE : BranchV8<0b1011, "bge">;
200 def BL : BranchV8<0b0011, "bl">;
201 def BGU : BranchV8<0b1100, "bgu">;
202 def BLEU : BranchV8<0b0100, "bleu">;
203 def BCC : BranchV8<0b1101, "bcc">;
204 def BCS : BranchV8<0b0101, "bcs">;
206 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
208 // floating-point conditional branch class:
209 class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
211 let isTerminator = 1;
212 let hasDelaySlot = 1;
215 def FBA : FPBranchV8<0b1000, "fba">;
216 def FBN : FPBranchV8<0b0000, "fbn">;
217 def FBU : FPBranchV8<0b0111, "fbu">;
218 def FBG : FPBranchV8<0b0110, "fbg">;
219 def FBUG : FPBranchV8<0b0101, "fbug">;
220 def FBL : FPBranchV8<0b0100, "fbl">;
221 def FBUL : FPBranchV8<0b0011, "fbul">;
222 def FBLG : FPBranchV8<0b0010, "fblg">;
223 def FBNE : FPBranchV8<0b0001, "fbne">;
224 def FBE : FPBranchV8<0b1001, "fbe">;
225 def FBUE : FPBranchV8<0b1010, "fbue">;
226 def FBGE : FPBranchV8<0b1011, "fbge">;
227 def FBUGE: FPBranchV8<0b1100, "fbuge">;
228 def FBLE : FPBranchV8<0b1101, "fble">;
229 def FBULE: FPBranchV8<0b1110, "fbule">;
230 def FBO : FPBranchV8<0b1111, "fbo">;
234 // Section B.24 - Call and Link Instruction, p. 125
235 // This is the only Format 1 instruction
236 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
238 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
239 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
243 let Inst{29-0} = disp;
247 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
248 // be an implicit def):
249 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
250 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
251 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
254 // Section B.29 - Write State Register Instructions
255 def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
256 def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
258 // Convert Integer to Floating-point Instructions, p. 141
259 def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
260 def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">;
262 // Convert Floating-point to Integer Instructions, p. 142
263 def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">;
264 def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">;
266 // Convert between Floating-point Formats Instructions, p. 143
267 def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">;
268 def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">;
270 // Floating-point Move Instructions, p. 144
271 def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">;
272 def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">;
273 def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">;
275 // Floating-point Add and Subtract Instructions, p. 146
276 def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">;
277 def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">;
278 def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">;
279 def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">;
281 // Floating-point Multiply and Divide Instructions, p. 147
282 def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">;
283 def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">;
284 def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">;
285 def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">;
286 def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
288 // Floating-point Compare Instructions, p. 148
289 // Note: the 2nd template arg is different for these guys.
290 // Note 2: the result of a FCMP is not available until the 2nd cycle
291 // after the instr is retired, but there is no interlock. This behavior
292 // is modelled as a delay slot.
293 let hasDelaySlot = 1 in {
294 def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
295 def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
296 def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
297 def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;