1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrInfo_F2.td"
32 include "SparcV8InstrInfo_F3.td"
34 //===----------------------------------------------------------------------===//
36 //===----------------------------------------------------------------------===//
38 // Pseudo instructions.
42 def ADJCALLSTACKDOWN : InstV8 {
43 let Name = "ADJCALLSTACKDOWN";
45 def ADJCALLSTACKUP : InstV8 {
46 let Name = "ADJCALLSTACKUP";
49 // Section A.3 - Synthetic Instructions, p. 85
50 // special cases of JMPL:
51 let isReturn = 1, isTerminator = 1, simm13 = 8 in
52 def RET : F3_2<2, 0b111000, "ret">;
53 let isReturn = 1, isTerminator = 1, simm13 = 8 in
54 def RETL: F3_2<2, 0b111000, "retl">;
55 // CMP is a special case of SUBCC where destination is ignored, by setting it to
56 // %g0 (hardwired zero).
57 // FIXME: should keep track of the fact that it defs the integer condition codes
59 def CMPri: F3_2<2, 0b010100, "cmp">;
61 // Section B.1 - Load Integer Instructions, p. 90
62 def LDSB: F3_2<3, 0b001001, "ldsb">;
63 def LDSH: F3_2<3, 0b001010, "ldsh">;
64 def LDUB: F3_2<3, 0b000001, "ldub">;
65 def LDUH: F3_2<3, 0b000010, "lduh">;
66 def LD : F3_2<3, 0b000000, "ld">;
67 def LDD : F3_2<3, 0b000011, "ldd">;
69 // Section B.2 - Load Floating-point Instructions, p. 92
70 def LDFrr : F3_1<3, 0b100000, "ld">;
71 def LDFri : F3_2<3, 0b100000, "ld">;
72 def LDDFrr : F3_1<3, 0b100011, "ldd">;
73 def LDDFri : F3_2<3, 0b100011, "ldd">;
74 def LDFSRrr: F3_1<3, 0b100001, "ld">;
75 def LDFSRri: F3_2<3, 0b100001, "ld">;
77 // Section B.4 - Store Integer Instructions, p. 95
78 def STB : F3_2<3, 0b000101, "stb">;
79 def STH : F3_2<3, 0b000110, "sth">;
80 def ST : F3_2<3, 0b000100, "st">;
81 def STD : F3_2<3, 0b000111, "std">;
83 // Section B.5 - Store Floating-point Instructions, p. 97
84 def STFrr : F3_1<3, 0b100100, "st">;
85 def STFri : F3_2<3, 0b100100, "st">;
86 def STDFrr : F3_1<3, 0b100111, "std">;
87 def STDFri : F3_2<3, 0b100111, "std">;
88 def STFSRrr : F3_1<3, 0b100101, "st">;
89 def STFSRri : F3_2<3, 0b100101, "st">;
90 def STDFQrr : F3_1<3, 0b100110, "std">;
91 def STDFQri : F3_2<3, 0b100110, "std">;
93 // Section B.9 - SETHI Instruction, p. 104
94 def SETHIi: F2_1<0b100, "sethi">;
96 // Section B.10 - NOP Instruction, p. 105
97 // (It's a special case of SETHI)
98 let rd = 0, imm = 0 in
99 def NOP : F2_1<0b100, "nop">;
101 // Section B.11 - Logical Instructions, p. 106
102 def ANDrr : F3_1<2, 0b000001, "and">;
103 def ANDri : F3_2<2, 0b000001, "and">;
104 def ORrr : F3_1<2, 0b000010, "or">;
105 def ORri : F3_2<2, 0b000010, "or">;
106 def XORrr : F3_1<2, 0b000011, "xor">;
107 def XORri : F3_2<2, 0b000011, "xor">;
109 // Section B.12 - Shift Instructions, p. 107
110 def SLLrr : F3_1<2, 0b100101, "sll">;
111 def SLLri : F3_2<2, 0b100101, "sll">;
112 def SRLrr : F3_1<2, 0b100110, "srl">;
113 def SRLri : F3_2<2, 0b100110, "srl">;
114 def SRArr : F3_1<2, 0b100111, "sra">;
115 def SRAri : F3_2<2, 0b100111, "sra">;
117 // Section B.13 - Add Instructions, p. 108
118 def ADDrr : F3_1<2, 0b000000, "add">;
119 def ADDri : F3_2<2, 0b000000, "add">;
121 // Section B.15 - Subtract Instructions, p. 110
122 def SUBrr : F3_1<2, 0b000100, "sub">;
123 def SUBCCrr : F3_1<2, 0b010100, "subcc">;
124 def SUBCCri : F3_2<2, 0b010100, "subcc">;
126 // Section B.18 - Multiply Instructions, p. 113
127 def UMULrr : F3_1<2, 0b001010, "umul">;
128 def SMULrr : F3_1<2, 0b001011, "smul">;
130 // Section B.19 - Divide Instructions, p. 115
131 def UDIVrr : F3_1<2, 0b001110, "udiv">;
132 def UDIVri : F3_2<2, 0b001110, "udiv">;
133 def SDIVrr : F3_1<2, 0b001111, "sdiv">;
134 def SDIVri : F3_2<2, 0b001111, "sdiv">;
135 def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
136 def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
137 def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
138 def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
140 // Section B.20 - SAVE and RESTORE, p. 117
141 def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
142 def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
143 def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
144 def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
146 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
148 // conditional branch class:
149 class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
151 let isTerminator = 1;
153 def BA : BranchV8<0b1000, "ba">;
154 def BN : BranchV8<0b0000, "bn">;
155 def BNE : BranchV8<0b1001, "bne">;
156 def BE : BranchV8<0b0001, "be">;
157 def BG : BranchV8<0b1010, "bg">;
158 def BLE : BranchV8<0b0010, "ble">;
159 def BGE : BranchV8<0b1011, "bge">;
160 def BL : BranchV8<0b0011, "bl">;
161 def BGU : BranchV8<0b1100, "bgu">;
162 def BLEU : BranchV8<0b0100, "bleu">;
163 def BCC : BranchV8<0b1101, "bcc">;
164 def BCS : BranchV8<0b0101, "bcs">;
166 // Section B.24 - Call and Link Instruction, p. 125
167 // This is the only Format 1 instruction
171 let Inst{29-0} = disp;
176 // Section B.25 - Jump and Link, p. 126
178 def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
180 // Section B.29 - Write State Register Instructions
181 def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
182 def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
184 // Convert between Floating-point Formats Instructions, p. 143
185 def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">;
186 def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">;
188 // Floating-point Move Instructions, p. 144
189 def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">;
190 def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">;
191 def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">;