1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 def LO10 : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
46 def HI22 : SDNodeXForm<imm, [{
47 // Transformation function: shift the immediate value down into the low bits.
48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
51 def SETHIimm : PatLeaf<(imm), [{
52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
56 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
57 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
60 def MEMrr : Operand<i32> {
61 let PrintMethod = "printMemOperand";
62 let NumMIOperands = 2;
63 let MIOperandInfo = (ops IntRegs, IntRegs);
65 def MEMri : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let NumMIOperands = 2;
68 let MIOperandInfo = (ops IntRegs, i32imm);
71 //===----------------------------------------------------------------------===//
73 //===----------------------------------------------------------------------===//
75 // Pseudo instructions.
76 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
77 let AsmString = asmstr;
78 dag OperandList = ops;
80 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
81 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
83 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
85 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
86 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
88 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
90 // Section A.3 - Synthetic Instructions, p. 85
91 // special cases of JMPL:
92 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
93 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
94 def RET : F3_2<2, 0b111000,
95 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
96 "ret $b, $c, $dst", []>;
97 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
98 def RETL: F3_2<2, 0b111000, (ops),
101 // CMP is a special case of SUBCC where destination is ignored, by setting it to
102 // %g0 (hardwired zero).
103 // FIXME: should keep track of the fact that it defs the integer condition codes
105 def CMPri: F3_2<2, 0b010100,
106 (ops IntRegs:$b, i32imm:$c),
109 // Section B.1 - Load Integer Instructions, p. 90
110 def LDSBri : F3_2<3, 0b001001,
111 (ops IntRegs:$dst, MEMri:$addr),
112 "ldsb [$addr], $dst",
113 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
114 def LDSHri : F3_2<3, 0b001010,
115 (ops IntRegs:$dst, MEMri:$addr),
116 "ldsh [$addr], $dst",
117 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
118 def LDUBri : F3_2<3, 0b000001,
119 (ops IntRegs:$dst, MEMri:$addr),
120 "ldub [$addr], $dst",
121 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
122 def LDUHri : F3_2<3, 0b000010,
123 (ops IntRegs:$dst, MEMri:$addr),
124 "lduh [$addr], $dst",
125 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
126 def LDri : F3_2<3, 0b000000,
127 (ops IntRegs:$dst, MEMri:$addr),
129 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
130 def LDDri : F3_2<3, 0b000011,
131 (ops IntRegs:$dst, MEMri:$addr),
132 "ldd [$addr], $dst", []>;
134 // Section B.2 - Load Floating-point Instructions, p. 92
135 def LDFrr : F3_1<3, 0b100000,
136 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
137 "ld [$b+$c], $dst", []>;
138 def LDFri : F3_2<3, 0b100000,
139 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
140 "ld [$b+$c], $dst", []>;
141 def LDDFrr : F3_1<3, 0b100011,
142 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
143 "ldd [$b+$c], $dst", []>;
144 def LDDFri : F3_2<3, 0b100011,
145 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
146 "ldd [$b+$c], $dst", []>;
147 def LDFSRrr: F3_1<3, 0b100001,
148 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
149 "ld [$b+$c], $dst", []>;
150 def LDFSRri: F3_2<3, 0b100001,
151 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
152 "ld [$b+$c], $dst", []>;
154 // Section B.4 - Store Integer Instructions, p. 95
155 def STBri : F3_2<3, 0b000101,
156 (ops MEMri:$addr, IntRegs:$src),
157 "stb $src, [$addr]", []>;
158 def STHri : F3_2<3, 0b000110,
159 (ops MEMri:$addr, IntRegs:$src),
160 "sth $src, [$addr]", []>;
161 def STri : F3_2<3, 0b000100,
162 (ops MEMri:$addr, IntRegs:$src),
163 "st $src, [$addr]", []>;
164 def STDri : F3_2<3, 0b000111,
165 (ops MEMri:$addr, IntRegs:$src),
166 "std $src, [$addr]", []>;
168 // Section B.5 - Store Floating-point Instructions, p. 97
169 def STFrr : F3_1<3, 0b100100,
170 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
171 "st $src, [$base+$offset]", []>;
172 def STFri : F3_2<3, 0b100100,
173 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
174 "st $src, [$base+$offset]", []>;
175 def STDFrr : F3_1<3, 0b100111,
176 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
177 "std $src, [$base+$offset]", []>;
178 def STDFri : F3_2<3, 0b100111,
179 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
180 "std $src, [$base+$offset]", []>;
181 def STFSRrr : F3_1<3, 0b100101,
182 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
183 "st $src, [$base+$offset]", []>;
184 def STFSRri : F3_2<3, 0b100101,
185 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
186 "st $src, [$base+$offset]", []>;
187 def STDFQrr : F3_1<3, 0b100110,
188 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
189 "std $src, [$base+$offset]", []>;
190 def STDFQri : F3_2<3, 0b100110,
191 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
192 "std $src, [$base+$offset]", []>;
194 // Section B.9 - SETHI Instruction, p. 104
195 def SETHIi: F2_1<0b100,
196 (ops IntRegs:$dst, i32imm:$src),
198 [(set IntRegs:$dst, SETHIimm:$src)]>;
200 // Section B.10 - NOP Instruction, p. 105
201 // (It's a special case of SETHI)
202 let rd = 0, imm22 = 0 in
203 def NOP : F2_1<0b100, (ops), "nop", []>;
205 // Section B.11 - Logical Instructions, p. 106
206 def ANDrr : F3_1<2, 0b000001,
207 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
209 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
210 def ANDri : F3_2<2, 0b000001,
211 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
213 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
214 def ANDCCrr : F3_1<2, 0b010001,
215 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
216 "andcc $b, $c, $dst", []>;
217 def ANDCCri : F3_2<2, 0b010001,
218 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
219 "andcc $b, $c, $dst", []>;
220 def ANDNrr : F3_1<2, 0b000101,
221 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
222 "andn $b, $c, $dst", []>;
223 def ANDNri : F3_2<2, 0b000101,
224 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
225 "andn $b, $c, $dst", []>;
226 def ANDNCCrr: F3_1<2, 0b010101,
227 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
228 "andncc $b, $c, $dst", []>;
229 def ANDNCCri: F3_2<2, 0b010101,
230 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
231 "andncc $b, $c, $dst", []>;
232 def ORrr : F3_1<2, 0b000010,
233 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
235 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
236 def ORri : F3_2<2, 0b000010,
237 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
239 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
240 def ORCCrr : F3_1<2, 0b010010,
241 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
242 "orcc $b, $c, $dst", []>;
243 def ORCCri : F3_2<2, 0b010010,
244 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
245 "orcc $b, $c, $dst", []>;
246 def ORNrr : F3_1<2, 0b000110,
247 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
248 "orn $b, $c, $dst", []>;
249 def ORNri : F3_2<2, 0b000110,
250 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
251 "orn $b, $c, $dst", []>;
252 def ORNCCrr : F3_1<2, 0b010110,
253 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
254 "orncc $b, $c, $dst", []>;
255 def ORNCCri : F3_2<2, 0b010110,
256 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
257 "orncc $b, $c, $dst", []>;
258 def XORrr : F3_1<2, 0b000011,
259 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
261 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
262 def XORri : F3_2<2, 0b000011,
263 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
265 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
266 def XORCCrr : F3_1<2, 0b010011,
267 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
268 "xorcc $b, $c, $dst", []>;
269 def XORCCri : F3_2<2, 0b010011,
270 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
271 "xorcc $b, $c, $dst", []>;
272 def XNORrr : F3_1<2, 0b000111,
273 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
274 "xnor $b, $c, $dst", []>;
275 def XNORri : F3_2<2, 0b000111,
276 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
277 "xnor $b, $c, $dst", []>;
278 def XNORCCrr: F3_1<2, 0b010111,
279 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
280 "xnorcc $b, $c, $dst", []>;
281 def XNORCCri: F3_2<2, 0b010111,
282 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
283 "xnorcc $b, $c, $dst", []>;
285 // Section B.12 - Shift Instructions, p. 107
286 def SLLrr : F3_1<2, 0b100101,
287 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
289 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
290 def SLLri : F3_2<2, 0b100101,
291 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
293 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
294 def SRLrr : F3_1<2, 0b100110,
295 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
297 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
298 def SRLri : F3_2<2, 0b100110,
299 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
301 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
302 def SRArr : F3_1<2, 0b100111,
303 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
305 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
306 def SRAri : F3_2<2, 0b100111,
307 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
309 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
311 // Section B.13 - Add Instructions, p. 108
312 def ADDrr : F3_1<2, 0b000000,
313 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
315 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
316 def ADDri : F3_2<2, 0b000000,
317 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
319 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
320 def ADDCCrr : F3_1<2, 0b010000,
321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
322 "addcc $b, $c, $dst", []>;
323 def ADDCCri : F3_2<2, 0b010000,
324 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
325 "addcc $b, $c, $dst", []>;
326 def ADDXrr : F3_1<2, 0b001000,
327 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
328 "addx $b, $c, $dst", []>;
329 def ADDXri : F3_2<2, 0b001000,
330 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
331 "addx $b, $c, $dst", []>;
332 def ADDXCCrr: F3_1<2, 0b011000,
333 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
334 "addxcc $b, $c, $dst", []>;
335 def ADDXCCri: F3_2<2, 0b011000,
336 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
337 "addxcc $b, $c, $dst", []>;
339 // Section B.15 - Subtract Instructions, p. 110
340 def SUBrr : F3_1<2, 0b000100,
341 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
343 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
344 def SUBri : F3_2<2, 0b000100,
345 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
347 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
348 def SUBCCrr : F3_1<2, 0b010100,
349 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
350 "subcc $b, $c, $dst", []>;
351 def SUBCCri : F3_2<2, 0b010100,
352 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
353 "subcc $b, $c, $dst", []>;
354 def SUBXrr : F3_1<2, 0b001100,
355 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
356 "subx $b, $c, $dst", []>;
357 def SUBXri : F3_2<2, 0b001100,
358 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
359 "subx $b, $c, $dst", []>;
360 def SUBXCCrr: F3_1<2, 0b011100,
361 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
362 "subxcc $b, $c, $dst", []>;
363 def SUBXCCri: F3_2<2, 0b011100,
364 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
365 "subxcc $b, $c, $dst", []>;
367 // Section B.18 - Multiply Instructions, p. 113
368 def UMULrr : F3_1<2, 0b001010,
369 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
370 "umul $b, $c, $dst", []>;
371 def UMULri : F3_2<2, 0b001010,
372 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
373 "umul $b, $c, $dst", []>;
374 def SMULrr : F3_1<2, 0b001011,
375 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
376 "smul $b, $c, $dst", []>;
377 def SMULri : F3_2<2, 0b001011,
378 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
379 "smul $b, $c, $dst", []>;
380 def UMULCCrr: F3_1<2, 0b011010,
381 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
382 "umulcc $b, $c, $dst", []>;
383 def UMULCCri: F3_2<2, 0b011010,
384 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
385 "umulcc $b, $c, $dst", []>;
386 def SMULCCrr: F3_1<2, 0b011011,
387 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
388 "smulcc $b, $c, $dst", []>;
389 def SMULCCri: F3_2<2, 0b011011,
390 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
391 "smulcc $b, $c, $dst", []>;
393 // Section B.19 - Divide Instructions, p. 115
394 def UDIVrr : F3_1<2, 0b001110,
395 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
396 "udiv $b, $c, $dst", []>;
397 def UDIVri : F3_2<2, 0b001110,
398 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
399 "udiv $b, $c, $dst", []>;
400 def SDIVrr : F3_1<2, 0b001111,
401 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
402 "sdiv $b, $c, $dst", []>;
403 def SDIVri : F3_2<2, 0b001111,
404 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
405 "sdiv $b, $c, $dst", []>;
406 def UDIVCCrr : F3_1<2, 0b011110,
407 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
408 "udivcc $b, $c, $dst", []>;
409 def UDIVCCri : F3_2<2, 0b011110,
410 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
411 "udivcc $b, $c, $dst", []>;
412 def SDIVCCrr : F3_1<2, 0b011111,
413 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
414 "sdivcc $b, $c, $dst", []>;
415 def SDIVCCri : F3_2<2, 0b011111,
416 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
417 "sdivcc $b, $c, $dst", []>;
419 // Section B.20 - SAVE and RESTORE, p. 117
420 def SAVErr : F3_1<2, 0b111100,
421 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
422 "save $b, $c, $dst", []>;
423 def SAVEri : F3_2<2, 0b111100,
424 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
425 "save $b, $c, $dst", []>;
426 def RESTORErr : F3_1<2, 0b111101,
427 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
428 "restore $b, $c, $dst", []>;
429 def RESTOREri : F3_2<2, 0b111101,
430 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
431 "restore $b, $c, $dst", []>;
433 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
435 // conditional branch class:
436 class BranchV8<bits<4> cc, dag ops, string asmstr>
437 : F2_2<cc, 0b010, ops, asmstr> {
439 let isTerminator = 1;
440 let hasDelaySlot = 1;
444 def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
445 def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
446 def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
447 def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
448 def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
449 def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
450 def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
451 def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
452 def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
453 def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
454 def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
455 def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
457 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
459 // floating-point conditional branch class:
460 class FPBranchV8<bits<4> cc, dag ops, string asmstr>
461 : F2_2<cc, 0b110, ops, asmstr> {
463 let isTerminator = 1;
464 let hasDelaySlot = 1;
467 def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
468 def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
469 def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
470 def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
471 def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
472 def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
473 def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
474 def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
475 def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
476 def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
477 def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
478 def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
479 def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
480 def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
481 def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
482 def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
486 // Section B.24 - Call and Link Instruction, p. 125
487 // This is the only Format 1 instruction
488 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
490 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
491 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
493 let OperandList = (ops IntRegs:$dst);
496 let Inst{29-0} = disp;
497 let AsmString = "call $dst";
500 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
501 // be an implicit def):
502 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
503 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
504 def JMPLrr : F3_1<2, 0b111000,
505 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
506 "jmpl $b+$c, $dst", []>;
509 // Section B.29 - Write State Register Instructions
510 def WRrr : F3_1<2, 0b110000,
511 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
512 "wr $b, $c, $dst", []>;
513 def WRri : F3_2<2, 0b110000,
514 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
515 "wr $b, $c, $dst", []>;
517 // Convert Integer to Floating-point Instructions, p. 141
518 def FITOS : F3_3<2, 0b110100, 0b011000100,
519 (ops FPRegs:$dst, FPRegs:$src),
521 def FITOD : F3_3<2, 0b110100, 0b011001000,
522 (ops DFPRegs:$dst, DFPRegs:$src),
525 // Convert Floating-point to Integer Instructions, p. 142
526 def FSTOI : F3_3<2, 0b110100, 0b011010001,
527 (ops FPRegs:$dst, FPRegs:$src),
529 def FDTOI : F3_3<2, 0b110100, 0b011010010,
530 (ops DFPRegs:$dst, DFPRegs:$src),
533 // Convert between Floating-point Formats Instructions, p. 143
534 def FSTOD : F3_3<2, 0b110100, 0b011001001,
535 (ops DFPRegs:$dst, FPRegs:$src),
537 def FDTOS : F3_3<2, 0b110100, 0b011000110,
538 (ops FPRegs:$dst, DFPRegs:$src),
541 // Floating-point Move Instructions, p. 144
542 def FMOVS : F3_3<2, 0b110100, 0b000000001,
543 (ops FPRegs:$dst, FPRegs:$src),
545 def FNEGS : F3_3<2, 0b110100, 0b000000101,
546 (ops FPRegs:$dst, FPRegs:$src),
548 def FABSS : F3_3<2, 0b110100, 0b000001001,
549 (ops FPRegs:$dst, FPRegs:$src),
552 // Floating-point Add and Subtract Instructions, p. 146
553 def FADDS : F3_3<2, 0b110100, 0b001000001,
554 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
555 "fadds $src1, $src2, $dst">;
556 def FADDD : F3_3<2, 0b110100, 0b001000010,
557 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
558 "faddd $src1, $src2, $dst">;
559 def FSUBS : F3_3<2, 0b110100, 0b001000101,
560 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
561 "fsubs $src1, $src2, $dst">;
562 def FSUBD : F3_3<2, 0b110100, 0b001000110,
563 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
564 "fsubd $src1, $src2, $dst">;
566 // Floating-point Multiply and Divide Instructions, p. 147
567 def FMULS : F3_3<2, 0b110100, 0b001001001,
568 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
569 "fmuls $src1, $src2, $dst">;
570 def FMULD : F3_3<2, 0b110100, 0b001001010,
571 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
572 "fmuld $src1, $src2, $dst">;
573 def FSMULD : F3_3<2, 0b110100, 0b001101001,
574 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
575 "fsmuld $src1, $src2, $dst">;
576 def FDIVS : F3_3<2, 0b110100, 0b001001101,
577 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
578 "fdivs $src1, $src2, $dst">;
579 def FDIVD : F3_3<2, 0b110100, 0b001001110,
580 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
581 "fdivd $src1, $src2, $dst">;
583 // Floating-point Compare Instructions, p. 148
584 // Note: the 2nd template arg is different for these guys.
585 // Note 2: the result of a FCMP is not available until the 2nd cycle
586 // after the instr is retired, but there is no interlock. This behavior
587 // is modelled with a forced noop after the instruction.
588 def FCMPS : F3_3<2, 0b110101, 0b001010001,
589 (ops FPRegs:$src1, FPRegs:$src2),
590 "fcmps $src1, $src2\n\tnop">;
591 def FCMPD : F3_3<2, 0b110101, 0b001010010,
592 (ops DFPRegs:$src1, DFPRegs:$src2),
593 "fcmpd $src1, $src2\n\tnop">;
594 def FCMPES : F3_3<2, 0b110101, 0b001010101,
595 (ops FPRegs:$src1, FPRegs:$src2),
596 "fcmpes $src1, $src2\n\tnop">;
597 def FCMPED : F3_3<2, 0b110101, 0b001010110,
598 (ops DFPRegs:$src1, DFPRegs:$src2),
599 "fcmped $src1, $src2\n\tnop">;
601 //===----------------------------------------------------------------------===//
602 // Non-Instruction Patterns
603 //===----------------------------------------------------------------------===//
606 def : Pat<(i32 simm13:$val),
607 (ORri G0, imm:$val)>;
608 // Arbitrary immediates.
609 def : Pat<(i32 imm:$val),
610 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;