1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
35 //===----------------------------------------------------------------------===//
37 // Pseudo instructions.
38 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
39 let AsmString = asmstr;
40 dag OperandList = ops;
42 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
43 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
45 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
47 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
48 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
50 def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
52 // Section A.3 - Synthetic Instructions, p. 85
53 // special cases of JMPL:
54 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
55 let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
56 def RET : F3_2<2, 0b111000,
57 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
59 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
60 def RETL: F3_2<2, 0b111000, (ops),
63 // CMP is a special case of SUBCC where destination is ignored, by setting it to
64 // %g0 (hardwired zero).
65 // FIXME: should keep track of the fact that it defs the integer condition codes
67 def CMPri: F3_2<2, 0b010100,
68 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
71 // Section B.1 - Load Integer Instructions, p. 90
72 def LDSB: F3_2<3, 0b001001,
73 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
74 "ldsb [$b+$c], $dst">;
75 def LDSH: F3_2<3, 0b001010,
76 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
77 "ldsh [$b+$c], $dst">;
78 def LDUB: F3_2<3, 0b000001,
79 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
80 "ldub [$b+$c], $dst">;
81 def LDUH: F3_2<3, 0b000010,
82 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
83 "lduh [$b+$c], $dst">;
84 def LD : F3_2<3, 0b000000,
85 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
87 def LDD : F3_2<3, 0b000011,
88 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
91 // Section B.2 - Load Floating-point Instructions, p. 92
92 def LDFrr : F3_1<3, 0b100000,
93 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
95 def LDFri : F3_2<3, 0b100000,
96 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
98 def LDDFrr : F3_1<3, 0b100011,
99 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
100 "ldd [$b+$c], $dst">;
101 def LDDFri : F3_2<3, 0b100011,
102 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
103 "ldd [$b+$c], $dst">;
104 def LDFSRrr: F3_1<3, 0b100001,
105 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
107 def LDFSRri: F3_2<3, 0b100001,
108 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
111 // Section B.4 - Store Integer Instructions, p. 95
112 def STB : F3_2<3, 0b000101,
113 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
114 "stb $src, [$base+$offset]">;
115 def STH : F3_2<3, 0b000110,
116 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
117 "sth $src, [$base+$offset]">;
118 def ST : F3_2<3, 0b000100,
119 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
120 "st $src, [$base+$offset]">;
121 def STD : F3_2<3, 0b000111,
122 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
123 "std $src, [$base+$offset]">;
125 // Section B.5 - Store Floating-point Instructions, p. 97
126 def STFrr : F3_1<3, 0b100100,
127 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
128 "st $src, [$base+$offset]">;
129 def STFri : F3_2<3, 0b100100,
130 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
131 "st $src, [$base+$offset]">;
132 def STDFrr : F3_1<3, 0b100111,
133 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
134 "std $src, [$base+$offset]">;
135 def STDFri : F3_2<3, 0b100111,
136 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
137 "std $src, [$base+$offset]">;
138 def STFSRrr : F3_1<3, 0b100101,
139 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
140 "st $src, [$base+$offset]">;
141 def STFSRri : F3_2<3, 0b100101,
142 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
143 "st $src, [$base+$offset]">;
144 def STDFQrr : F3_1<3, 0b100110,
145 (ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
146 "std $src, [$base+$offset]">;
147 def STDFQri : F3_2<3, 0b100110,
148 (ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
149 "std $src, [$base+$offset]">;
151 // Section B.9 - SETHI Instruction, p. 104
152 def SETHIi: F2_1<0b100,
153 (ops IntRegs:$dst, i32imm:$src),
156 // Section B.10 - NOP Instruction, p. 105
157 // (It's a special case of SETHI)
158 let rd = 0, imm22 = 0 in
159 def NOP : F2_1<0b100, (ops), "nop">;
161 // Section B.11 - Logical Instructions, p. 106
162 def ANDrr : F3_1<2, 0b000001,
163 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
165 def ANDri : F3_2<2, 0b000001,
166 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
168 def ANDCCrr : F3_1<2, 0b010001,
169 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
170 "andcc $b, $c, $dst">;
171 def ANDCCri : F3_2<2, 0b010001,
172 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
173 "andcc $b, $c, $dst">;
174 def ANDNrr : F3_1<2, 0b000101,
175 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
176 "andn $b, $c, $dst">;
177 def ANDNri : F3_2<2, 0b000101,
178 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
179 "andn $b, $c, $dst">;
180 def ANDNCCrr: F3_1<2, 0b010101,
181 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
182 "andncc $b, $c, $dst">;
183 def ANDNCCri: F3_2<2, 0b010101,
184 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
185 "andncc $b, $c, $dst">;
186 def ORrr : F3_1<2, 0b000010,
187 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
189 def ORri : F3_2<2, 0b000010,
190 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
192 def ORCCrr : F3_1<2, 0b010010,
193 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
194 "orcc $b, $c, $dst">;
195 def ORCCri : F3_2<2, 0b010010,
196 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
197 "orcc $b, $c, $dst">;
198 def ORNrr : F3_1<2, 0b000110,
199 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
201 def ORNri : F3_2<2, 0b000110,
202 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
204 def ORNCCrr : F3_1<2, 0b010110,
205 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
206 "orncc $b, $c, $dst">;
207 def ORNCCri : F3_2<2, 0b010110,
208 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
209 "orncc $b, $c, $dst">;
210 def XORrr : F3_1<2, 0b000011,
211 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
213 def XORri : F3_2<2, 0b000011,
214 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
216 def XORCCrr : F3_1<2, 0b010011,
217 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
218 "xorcc $b, $c, $dst">;
219 def XORCCri : F3_2<2, 0b010011,
220 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
221 "xorcc $b, $c, $dst">;
222 def XNORrr : F3_1<2, 0b000111,
223 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
224 "xnor $b, $c, $dst">;
225 def XNORri : F3_2<2, 0b000111,
226 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
227 "xnor $b, $c, $dst">;
228 def XNORCCrr: F3_1<2, 0b010111,
229 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
230 "xnorcc $b, $c, $dst">;
231 def XNORCCri: F3_2<2, 0b010111,
232 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
233 "xnorcc $b, $c, $dst">;
235 // Section B.12 - Shift Instructions, p. 107
236 def SLLrr : F3_1<2, 0b100101,
237 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
239 def SLLri : F3_2<2, 0b100101,
240 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
242 def SRLrr : F3_1<2, 0b100110,
243 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
245 def SRLri : F3_2<2, 0b100110,
246 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
248 def SRArr : F3_1<2, 0b100111,
249 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
251 def SRAri : F3_2<2, 0b100111,
252 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
255 // Section B.13 - Add Instructions, p. 108
256 def ADDrr : F3_1<2, 0b000000,
257 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
259 def ADDri : F3_2<2, 0b000000,
260 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
262 def ADDCCrr : F3_1<2, 0b010000,
263 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
264 "addcc $b, $c, $dst">;
265 def ADDCCri : F3_2<2, 0b010000,
266 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
267 "addcc $b, $c, $dst">;
268 def ADDXrr : F3_1<2, 0b001000,
269 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
270 "addx $b, $c, $dst">;
271 def ADDXri : F3_2<2, 0b001000,
272 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
273 "addx $b, $c, $dst">;
274 def ADDXCCrr: F3_1<2, 0b011000,
275 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
276 "addxcc $b, $c, $dst">;
277 def ADDXCCri: F3_2<2, 0b011000,
278 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
279 "addxcc $b, $c, $dst">;
281 // Section B.15 - Subtract Instructions, p. 110
282 def SUBrr : F3_1<2, 0b000100,
283 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
285 def SUBri : F3_2<2, 0b000100,
286 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
288 def SUBCCrr : F3_1<2, 0b010100,
289 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
290 "subcc $b, $c, $dst">;
291 def SUBCCri : F3_2<2, 0b010100,
292 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
293 "subcc $b, $c, $dst">;
294 def SUBXrr : F3_1<2, 0b001100,
295 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
296 "subx $b, $c, $dst">;
297 def SUBXri : F3_2<2, 0b001100,
298 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
299 "subx $b, $c, $dst">;
300 def SUBXCCrr: F3_1<2, 0b011100,
301 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
302 "subxcc $b, $c, $dst">;
303 def SUBXCCri: F3_2<2, 0b011100,
304 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
305 "subxcc $b, $c, $dst">;
307 // Section B.18 - Multiply Instructions, p. 113
308 def UMULrr : F3_1<2, 0b001010,
309 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
310 "umul $b, $c, $dst">;
311 def UMULri : F3_2<2, 0b001010,
312 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
313 "umul $b, $c, $dst">;
314 def SMULrr : F3_1<2, 0b001011,
315 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
316 "smul $b, $c, $dst">;
317 def SMULri : F3_2<2, 0b001011,
318 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
319 "smul $b, $c, $dst">;
320 def UMULCCrr: F3_1<2, 0b011010,
321 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
322 "umulcc $b, $c, $dst">;
323 def UMULCCri: F3_2<2, 0b011010,
324 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
325 "umulcc $b, $c, $dst">;
326 def SMULCCrr: F3_1<2, 0b011011,
327 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
328 "smulcc $b, $c, $dst">;
329 def SMULCCri: F3_2<2, 0b011011,
330 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
331 "smulcc $b, $c, $dst">;
333 // Section B.19 - Divide Instructions, p. 115
334 def UDIVrr : F3_1<2, 0b001110,
335 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
336 "udiv $b, $c, $dst">;
337 def UDIVri : F3_2<2, 0b001110,
338 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
339 "udiv $b, $c, $dst">;
340 def SDIVrr : F3_1<2, 0b001111,
341 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
342 "sdiv $b, $c, $dst">;
343 def SDIVri : F3_2<2, 0b001111,
344 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
345 "sdiv $b, $c, $dst">;
346 def UDIVCCrr : F3_1<2, 0b011110,
347 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
348 "udivcc $b, $c, $dst">;
349 def UDIVCCri : F3_2<2, 0b011110,
350 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
351 "udivcc $b, $c, $dst">;
352 def SDIVCCrr : F3_1<2, 0b011111,
353 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
354 "sdivcc $b, $c, $dst">;
355 def SDIVCCri : F3_2<2, 0b011111,
356 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
357 "sdivcc $b, $c, $dst">;
359 // Section B.20 - SAVE and RESTORE, p. 117
360 def SAVErr : F3_1<2, 0b111100,
361 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
362 "save $b, $c, $dst">;
363 def SAVEri : F3_2<2, 0b111100,
364 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
365 "save $b, $c, $dst">;
366 def RESTORErr : F3_1<2, 0b111101,
367 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
368 "restore $b, $c, $dst">;
369 def RESTOREri : F3_2<2, 0b111101,
370 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
371 "restore $b, $c, $dst">;
373 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
375 // conditional branch class:
376 class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
378 let isTerminator = 1;
379 let hasDelaySlot = 1;
383 def BA : BranchV8<0b1000, "ba">;
384 def BN : BranchV8<0b0000, "bn">;
385 def BNE : BranchV8<0b1001, "bne">;
386 def BE : BranchV8<0b0001, "be">;
387 def BG : BranchV8<0b1010, "bg">;
388 def BLE : BranchV8<0b0010, "ble">;
389 def BGE : BranchV8<0b1011, "bge">;
390 def BL : BranchV8<0b0011, "bl">;
391 def BGU : BranchV8<0b1100, "bgu">;
392 def BLEU : BranchV8<0b0100, "bleu">;
393 def BCC : BranchV8<0b1101, "bcc">;
394 def BCS : BranchV8<0b0101, "bcs">;
396 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
398 // floating-point conditional branch class:
399 class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
401 let isTerminator = 1;
402 let hasDelaySlot = 1;
405 def FBA : FPBranchV8<0b1000, "fba">;
406 def FBN : FPBranchV8<0b0000, "fbn">;
407 def FBU : FPBranchV8<0b0111, "fbu">;
408 def FBG : FPBranchV8<0b0110, "fbg">;
409 def FBUG : FPBranchV8<0b0101, "fbug">;
410 def FBL : FPBranchV8<0b0100, "fbl">;
411 def FBUL : FPBranchV8<0b0011, "fbul">;
412 def FBLG : FPBranchV8<0b0010, "fblg">;
413 def FBNE : FPBranchV8<0b0001, "fbne">;
414 def FBE : FPBranchV8<0b1001, "fbe">;
415 def FBUE : FPBranchV8<0b1010, "fbue">;
416 def FBGE : FPBranchV8<0b1011, "fbge">;
417 def FBUGE: FPBranchV8<0b1100, "fbuge">;
418 def FBLE : FPBranchV8<0b1101, "fble">;
419 def FBULE: FPBranchV8<0b1110, "fbule">;
420 def FBO : FPBranchV8<0b1111, "fbo">;
424 // Section B.24 - Call and Link Instruction, p. 125
425 // This is the only Format 1 instruction
426 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
428 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
429 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
433 let Inst{29-0} = disp;
437 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
438 // be an implicit def):
439 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
440 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
441 def JMPLrr : F3_1<2, 0b111000,
442 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
446 // Section B.29 - Write State Register Instructions
447 def WRrr : F3_1<2, 0b110000,
448 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
450 def WRri : F3_2<2, 0b110000,
451 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
454 // Convert Integer to Floating-point Instructions, p. 141
455 def FITOS : F3_3<2, 0b110100, 0b011000100,
456 (ops FPRegs:$dst, FPRegs:$src),
458 def FITOD : F3_3<2, 0b110100, 0b011001000,
459 (ops DFPRegs:$dst, DFPRegs:$src),
462 // Convert Floating-point to Integer Instructions, p. 142
463 def FSTOI : F3_3<2, 0b110100, 0b011010001,
464 (ops FPRegs:$dst, FPRegs:$src),
466 def FDTOI : F3_3<2, 0b110100, 0b011010010,
467 (ops DFPRegs:$dst, DFPRegs:$src),
470 // Convert between Floating-point Formats Instructions, p. 143
471 def FSTOD : F3_3<2, 0b110100, 0b011001001,
472 (ops DFPRegs:$dst, FPRegs:$src),
474 def FDTOS : F3_3<2, 0b110100, 0b011000110,
475 (ops FPRegs:$dst, DFPRegs:$src),
478 // Floating-point Move Instructions, p. 144
479 def FMOVS : F3_3<2, 0b110100, 0b000000001,
480 (ops FPRegs:$dst, FPRegs:$src),
482 def FNEGS : F3_3<2, 0b110100, 0b000000101,
483 (ops FPRegs:$dst, FPRegs:$src),
485 def FABSS : F3_3<2, 0b110100, 0b000001001,
486 (ops FPRegs:$dst, FPRegs:$src),
489 // Floating-point Add and Subtract Instructions, p. 146
490 def FADDS : F3_3<2, 0b110100, 0b001000001,
491 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
492 "fadds $src1, $src2, $dst">;
493 def FADDD : F3_3<2, 0b110100, 0b001000010,
494 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
495 "faddd $src1, $src2, $dst">;
496 def FSUBS : F3_3<2, 0b110100, 0b001000101,
497 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
498 "fsubs $src1, $src2, $dst">;
499 def FSUBD : F3_3<2, 0b110100, 0b001000110,
500 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
501 "fsubd $src1, $src2, $dst">;
503 // Floating-point Multiply and Divide Instructions, p. 147
504 def FMULS : F3_3<2, 0b110100, 0b001001001,
505 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
506 "fmuls $src1, $src2, $dst">;
507 def FMULD : F3_3<2, 0b110100, 0b001001010,
508 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
509 "fmuld $src1, $src2, $dst">;
510 def FSMULD : F3_3<2, 0b110100, 0b001101001,
511 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
512 "fsmuld $src1, $src2, $dst">;
513 def FDIVS : F3_3<2, 0b110100, 0b001001101,
514 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
515 "fdivs $src1, $src2, $dst">;
516 def FDIVD : F3_3<2, 0b110100, 0b001001110,
517 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
518 "fdivd $src1, $src2, $dst">;
520 // Floating-point Compare Instructions, p. 148
521 // Note: the 2nd template arg is different for these guys.
522 // Note 2: the result of a FCMP is not available until the 2nd cycle
523 // after the instr is retired, but there is no interlock. This behavior
524 // is modelled with a forced noop after the instruction.
525 def FCMPS : F3_3<2, 0b110101, 0b001010001,
526 (ops FPRegs:$src1, FPRegs:$src2),
527 "fcmps $src1, $src2\n nop">;
528 def FCMPD : F3_3<2, 0b110101, 0b001010010,
529 (ops DFPRegs:$src1, DFPRegs:$src2),
530 "fcmpd $src1, $src2\n nop">;
531 def FCMPES : F3_3<2, 0b110101, 0b001010101,
532 (ops FPRegs:$src1, FPRegs:$src2),
533 "fcmpes $src1, $src2\n nop">;
534 def FCMPED : F3_3<2, 0b110101, 0b001010110,
535 (ops DFPRegs:$src1, DFPRegs:$src2),
536 "fcmped $src1, $src2\n nop">;