1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Type.h"
20 #include "llvm/ADT/STLExtras.h"
24 SparcV8RegisterInfo::SparcV8RegisterInfo()
25 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26 V8::ADJCALLSTACKUP) {}
28 void SparcV8RegisterInfo::
29 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
30 unsigned SrcReg, int FI,
31 const TargetRegisterClass *RC) const {
32 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
33 if (RC == V8::IntRegsRegisterClass)
34 BuildMI(MBB, I, V8::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
35 else if (RC == V8::FPRegsRegisterClass)
36 BuildMI(MBB, I, V8::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
37 else if (RC == V8::DFPRegsRegisterClass)
38 BuildMI(MBB, I, V8::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
40 assert(0 && "Can't store this register to stack slot");
43 void SparcV8RegisterInfo::
44 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
45 unsigned DestReg, int FI,
46 const TargetRegisterClass *RC) const {
47 if (RC == V8::IntRegsRegisterClass)
48 BuildMI(MBB, I, V8::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
49 else if (RC == V8::FPRegsRegisterClass)
50 BuildMI(MBB, I, V8::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
51 else if (RC == V8::DFPRegsRegisterClass)
52 BuildMI(MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
54 assert(0 && "Can't load this register from stack slot");
57 void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator I,
59 unsigned DestReg, unsigned SrcReg,
60 const TargetRegisterClass *RC) const {
61 if (RC == V8::IntRegsRegisterClass)
62 BuildMI(MBB, I, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(SrcReg);
63 else if (RC == V8::FPRegsRegisterClass)
64 BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
65 else if (RC == V8::DFPRegsRegisterClass)
66 BuildMI(MBB, I, V8::FpMOVD, 1, DestReg).addReg(SrcReg);
68 assert (0 && "Can't copy this register");
71 MachineInstr *SparcV8RegisterInfo::foldMemoryOperand(MachineInstr* MI,
75 switch (MI->getOpcode()) {
77 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == V8::G0&&
78 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
79 if (OpNum == 0) // COPY -> STORE
80 return BuildMI(V8::STri, 3).addFrameIndex(FI).addImm(0)
81 .addReg(MI->getOperand(2).getReg());
83 return BuildMI(V8::LDri, 2, MI->getOperand(0).getReg())
84 .addFrameIndex(FI).addImm(0);
91 if (OpNum == 0) // COPY -> STORE
92 return BuildMI(isFloat ? V8::STFri : V8::STDFri, 3)
93 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
95 return BuildMI(isFloat ? V8::LDFri : V8::LDDFri, 2,
96 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
102 void SparcV8RegisterInfo::
103 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator I) const {
105 MachineInstr &MI = *I;
106 int Size = MI.getOperand(0).getImmedValue();
107 if (MI.getOpcode() == V8::ADJCALLSTACKDOWN)
110 BuildMI(MBB, I, V8::ADDri, 2, V8::O6).addReg(V8::O6).addSImm(Size);
115 SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
117 MachineInstr &MI = *II;
118 while (!MI.getOperand(i).isFrameIndex()) {
120 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
123 int FrameIndex = MI.getOperand(i).getFrameIndex();
125 // Addressable stack objects are accessed using neg. offsets from %fp
126 MachineFunction &MF = *MI.getParent()->getParent();
127 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
128 MI.getOperand(i+1).getImmedValue();
130 // Replace frame index with a frame pointer reference.
131 if (Offset >= -4096 && Offset <= 4095) {
132 // If the offset is small enough to fit in the immediate field, directly
134 MI.SetMachineOperandReg(i, V8::I6);
135 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
137 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
138 // scavenge a register here instead of reserving G1 all of the time.
139 unsigned OffHi = (unsigned)Offset >> 10U;
140 BuildMI(*MI.getParent(), II, V8::SETHIi, 1, V8::G1).addImm(OffHi);
142 BuildMI(*MI.getParent(), II, V8::ADDrr, 2,
143 V8::G1).addReg(V8::G1).addReg(V8::I6);
144 // Insert: G1+%lo(offset) into the user.
145 MI.SetMachineOperandReg(i, V8::I1);
146 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
147 Offset & ((1 << 10)-1));
151 void SparcV8RegisterInfo::
152 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
154 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
155 MachineBasicBlock &MBB = MF.front();
156 MachineFrameInfo *MFI = MF.getFrameInfo();
158 // Get the number of bytes to allocate from the FrameInfo
159 int NumBytes = (int) MFI->getStackSize();
161 // Emit the correct save instruction based on the number of bytes in
162 // the frame. Minimum stack frame size according to V8 ABI is:
163 // 16 words for register window spill
164 // 1 word for address of returned aggregate-value
165 // + 6 words for passing parameters on the stack
167 // 23 words * 4 bytes per word = 92 bytes
169 // Round up to next doubleword boundary -- a double-word boundary
170 // is required by the ABI.
171 NumBytes = (NumBytes + 7) & ~7;
172 NumBytes = -NumBytes;
174 if (NumBytes >= -4096) {
175 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
176 V8::O6).addImm(NumBytes).addReg(V8::O6);
178 MachineBasicBlock::iterator InsertPt = MBB.begin();
179 // Emit this the hard way. This clobbers G1 which we always know is
181 unsigned OffHi = (unsigned)NumBytes >> 10U;
182 BuildMI(MBB, InsertPt, V8::SETHIi, 1, V8::G1).addImm(OffHi);
184 BuildMI(MBB, InsertPt, V8::ORri, 2, V8::G1)
185 .addReg(V8::G1).addImm(NumBytes & ((1 << 10)-1));
186 BuildMI(MBB, InsertPt, V8::SAVErr, 2,
187 V8::O6).addReg(V8::O6).addReg(V8::G1);
191 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
192 MachineBasicBlock &MBB) const {
193 MachineBasicBlock::iterator MBBI = prior(MBB.end());
194 assert(MBBI->getOpcode() == V8::RETL &&
195 "Can only put epilog before 'retl' instruction!");
196 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
199 #include "SparcV8GenRegisterInfo.inc"