1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Type.h"
20 #include "llvm/ADT/STLExtras.h"
24 SparcV8RegisterInfo::SparcV8RegisterInfo()
25 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26 V8::ADJCALLSTACKUP) {}
28 static const TargetRegisterClass *getClass(unsigned SrcReg) {
29 if (SparcV8::IntRegsRegisterClass->contains(SrcReg))
30 return SparcV8::IntRegsRegisterClass;
31 else if (SparcV8::FPRegsRegisterClass->contains(SrcReg))
32 return SparcV8::FPRegsRegisterClass;
33 else if (SparcV8::DFPRegsRegisterClass->contains(SrcReg))
34 return SparcV8::DFPRegsRegisterClass;
36 std::cerr << "Error: register of unknown class found: " << SrcReg << "\n";
41 void SparcV8RegisterInfo::
42 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
43 unsigned SrcReg, int FrameIdx) const {
44 const TargetRegisterClass *RC = getClass(SrcReg);
46 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
47 if (RC == SparcV8::IntRegsRegisterClass)
48 BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
50 else if (RC == SparcV8::FPRegsRegisterClass)
51 BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
53 else if (RC == SparcV8::DFPRegsRegisterClass)
54 BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
57 assert (0 && "Can't store this register to stack slot");
60 void SparcV8RegisterInfo::
61 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
62 unsigned DestReg, int FrameIdx) const {
63 const TargetRegisterClass *RC = getClass(DestReg);
64 if (RC == SparcV8::IntRegsRegisterClass)
65 BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
66 else if (RC == SparcV8::FPRegsRegisterClass)
67 BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
69 else if (RC == SparcV8::DFPRegsRegisterClass)
70 BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
73 assert(0 && "Can't load this register from stack slot");
76 void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator I,
78 unsigned DestReg, unsigned SrcReg,
79 const TargetRegisterClass *RC) const {
80 if (RC == SparcV8::IntRegsRegisterClass)
81 BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
82 else if (RC == SparcV8::FPRegsRegisterClass)
83 BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
84 else if (RC == SparcV8::DFPRegsRegisterClass)
85 BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
87 assert (0 && "Can't copy this register");
90 void SparcV8RegisterInfo::
91 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I) const {
93 MachineInstr &MI = *I;
94 int size = MI.getOperand (0).getImmedValue ();
95 if (MI.getOpcode () == V8::ADJCALLSTACKDOWN)
97 BuildMI (MBB, I, V8::ADDri, 2, V8::SP).addReg (V8::SP).addSImm (size);
102 SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
104 MachineInstr &MI = *II;
105 while (!MI.getOperand(i).isFrameIndex()) {
107 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
110 int FrameIndex = MI.getOperand(i).getFrameIndex();
112 // Replace frame index with a frame pointer reference
113 MI.SetMachineOperandReg (i, V8::FP);
115 // Addressable stack objects are accessed using neg. offsets from %fp
116 MachineFunction &MF = *MI.getParent()->getParent();
117 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
118 MI.getOperand(i+1).getImmedValue();
120 MI.SetMachineOperandConst (i+1, MachineOperand::MO_SignExtendedImmed, Offset);
123 void SparcV8RegisterInfo::
124 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
126 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
127 MachineBasicBlock &MBB = MF.front();
128 MachineFrameInfo *MFI = MF.getFrameInfo();
130 // Get the number of bytes to allocate from the FrameInfo
131 int NumBytes = (int) MFI->getStackSize();
133 // Emit the correct save instruction based on the number of bytes in
134 // the frame. Minimum stack frame size according to V8 ABI is:
135 // 16 words for register window spill
136 // 1 word for address of returned aggregate-value
137 // + 6 words for passing parameters on the stack
139 // 23 words * 4 bytes per word = 92 bytes
141 // Round up to next doubleword boundary -- a double-word boundary
142 // is required by the ABI.
143 NumBytes = (NumBytes + 7) & ~7;
144 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
145 V8::SP).addImm(-NumBytes).addReg(V8::SP);
148 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
149 MachineBasicBlock &MBB) const {
150 MachineBasicBlock::iterator MBBI = prior(MBB.end());
151 assert(MBBI->getOpcode() == V8::RETL &&
152 "Can only put epilog before 'retl' instruction!");
153 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
156 #include "SparcV8GenRegisterInfo.inc"
158 const TargetRegisterClass*
159 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
160 switch (Ty->getTypeID()) {
161 case Type::FloatTyID: return &FPRegsInstance;
162 case Type::DoubleTyID: return &DFPRegsInstance;
164 case Type::ULongTyID: assert(0 && "Long values do not fit in registers!");
165 default: assert(0 && "Invalid type to getClass!");
167 case Type::SByteTyID:
168 case Type::UByteTyID:
169 case Type::ShortTyID:
170 case Type::UShortTyID:
173 case Type::PointerTyID: return &IntRegsInstance;