1 //===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "SparcV8TargetMachine.h"
15 #include "llvm/Assembly/PrintModulePass.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetMachineRegistry.h"
22 #include "llvm/Transforms/Scalar.h"
27 // Register the target.
28 RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
31 /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
33 SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
34 IntrinsicLowering *IL)
35 : TargetMachine("SparcV8", IL, false, 4, 4),
36 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) {
39 unsigned SparcV8TargetMachine::getJITMatchQuality() {
40 return 0; // No JIT yet.
43 unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
44 std::string TT = M.getTargetTriple();
45 if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "sparc-")
48 if (M.getEndianness() == Module::BigEndian &&
49 M.getPointerSize() == Module::Pointer32)
51 return 20; // BE/32 ==> Prefer sparcv8 on sparc
53 return 5; // BE/32 ==> Prefer ppc elsewhere
55 else if (M.getEndianness() != Module::AnyEndianness ||
56 M.getPointerSize() != Module::AnyPointerSize)
57 return 0; // Match for some other target
59 return getJITMatchQuality()/2;
62 /// addPassesToEmitAssembly - Add passes to the specified pass manager
63 /// to implement a static compiler for this target.
65 bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
67 // FIXME: Implement efficient support for garbage collection intrinsics.
68 PM.add(createLowerGCPass());
70 // Replace malloc and free instructions with library calls.
71 PM.add(createLowerAllocationsPass());
73 // FIXME: implement the switch instruction in the instruction selector.
74 PM.add(createLowerSwitchPass());
76 // FIXME: implement the invoke/unwind instructions!
77 PM.add(createLowerInvokePass());
79 PM.add(createLowerConstantExpressionsPass());
81 // Make sure that no unreachable blocks are instruction selected.
82 PM.add(createUnreachableBlockEliminationPass());
84 // FIXME: implement the select instruction in the instruction selector.
85 PM.add(createLowerSelectPass());
87 // Print LLVM code input to instruction selector:
89 PM.add(new PrintFunctionPass());
91 PM.add(createSparcV8SimpleInstructionSelector(*this));
93 // Print machine instructions as they were initially generated.
95 PM.add(createMachineFunctionPrinterPass(&std::cerr));
97 PM.add(createRegisterAllocator());
98 PM.add(createPrologEpilogCodeInserter());
100 // Print machine instructions after register allocation and prolog/epilog
102 if (PrintMachineCode)
103 PM.add(createMachineFunctionPrinterPass(&std::cerr));
105 PM.add(createSparcV8FPMoverPass(*this));
106 PM.add(createSparcV8DelaySlotFillerPass(*this));
108 // Print machine instructions after filling delay slots.
109 if (PrintMachineCode)
110 PM.add(createMachineFunctionPrinterPass(&std::cerr));
112 // Output assembly language.
113 PM.add(createSparcV8CodePrinterPass(Out, *this));
115 // Delete the MachineInstrs we generated, since they're no longer needed.
116 PM.add(createMachineCodeDeleter());
120 /// addPassesToJITCompile - Add passes to the specified pass manager to
121 /// implement a fast dynamic compiler for this target.
123 void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
124 // FIXME: Implement efficient support for garbage collection intrinsics.
125 PM.add(createLowerGCPass());
127 // Replace malloc and free instructions with library calls.
128 PM.add(createLowerAllocationsPass());
130 // FIXME: implement the switch instruction in the instruction selector.
131 PM.add(createLowerSwitchPass());
133 // FIXME: implement the invoke/unwind instructions!
134 PM.add(createLowerInvokePass());
136 PM.add(createLowerConstantExpressionsPass());
138 // Make sure that no unreachable blocks are instruction selected.
139 PM.add(createUnreachableBlockEliminationPass());
141 // FIXME: implement the select instruction in the instruction selector.
142 PM.add(createLowerSelectPass());
144 // Print LLVM code input to instruction selector:
145 if (PrintMachineCode)
146 PM.add(new PrintFunctionPass());
148 PM.add(createSparcV8SimpleInstructionSelector(TM));
150 // Print machine instructions as they were initially generated.
151 if (PrintMachineCode)
152 PM.add(createMachineFunctionPrinterPass(&std::cerr));
154 PM.add(createRegisterAllocator());
155 PM.add(createPrologEpilogCodeInserter());
157 // Print machine instructions after register allocation and prolog/epilog
159 if (PrintMachineCode)
160 PM.add(createMachineFunctionPrinterPass(&std::cerr));
162 PM.add(createSparcV8FPMoverPass(TM));
163 PM.add(createSparcV8DelaySlotFillerPass(TM));
165 // Print machine instructions after filling delay slots.
166 if (PrintMachineCode)
167 PM.add(createMachineFunctionPrinterPass(&std::cerr));