1 //===- InstrScheduling.cpp - Generic Instruction Scheduling support -------===//
3 // This file implements the llvm/CodeGen/InstrScheduling.h interface, along with
4 // generic support routines for instruction scheduling.
6 //===----------------------------------------------------------------------===//
8 #include "llvm/CodeGen/InstrScheduling.h"
9 #include "llvm/CodeGen/MachineInstr.h"
10 #include "llvm/CodeGen/MachineCodeForInstruction.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/BasicBlock.h"
15 #include "llvm/Instruction.h"
16 #include "SchedPriorities.h"
17 #include <ext/hash_set>
24 //************************* External Data Types *****************************/
26 cl::Enum<enum SchedDebugLevel_t> SchedDebugLevel("dsched", cl::NoFlags,
27 "enable instruction scheduling debugging information",
28 clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"),
29 clEnumValN(Sched_Disable, "off", "disable instruction scheduling"),
30 clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
31 clEnumValN(Sched_PrintSchedTrace, "t", "print trace of scheduling actions"),
32 clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"), 0);
35 //************************* Internal Data Types *****************************/
38 class SchedulingManager;
41 //----------------------------------------------------------------------
44 // Represents a group of instructions scheduled to be issued
46 //----------------------------------------------------------------------
48 class InstrGroup: public NonCopyable {
50 inline const SchedGraphNode* operator[](unsigned int slotNum) const {
51 assert(slotNum < group.size());
52 return group[slotNum];
56 friend class InstrSchedule;
58 inline void addInstr(const SchedGraphNode* node, unsigned int slotNum) {
59 assert(slotNum < group.size());
60 group[slotNum] = node;
63 /*ctor*/ InstrGroup(unsigned int nslots)
64 : group(nslots, NULL) {}
66 /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT
69 vector<const SchedGraphNode*> group;
73 //----------------------------------------------------------------------
74 // class ScheduleIterator:
76 // Iterates over the machine instructions in the for a single basic block.
77 // The schedule is represented by an InstrSchedule object.
78 //----------------------------------------------------------------------
80 template<class _NodeType>
81 class ScheduleIterator: public std::forward_iterator<_NodeType, ptrdiff_t> {
85 const InstrSchedule& S;
87 typedef ScheduleIterator<_NodeType> _Self;
89 /*ctor*/ inline ScheduleIterator(const InstrSchedule& _schedule,
92 : cycleNum(_cycleNum), slotNum(_slotNum), S(_schedule) {
96 /*ctor*/ inline ScheduleIterator(const _Self& x)
97 : cycleNum(x.cycleNum), slotNum(x.slotNum), S(x.S) {}
99 inline bool operator==(const _Self& x) const {
100 return (slotNum == x.slotNum && cycleNum== x.cycleNum && &S==&x.S);
103 inline bool operator!=(const _Self& x) const { return !operator==(x); }
105 inline _NodeType* operator*() const {
106 assert(cycleNum < S.groups.size());
107 return (*S.groups[cycleNum])[slotNum];
109 inline _NodeType* operator->() const { return operator*(); }
111 _Self& operator++(); // Preincrement
112 inline _Self operator++(int) { // Postincrement
113 _Self tmp(*this); ++*this; return tmp;
116 static _Self begin(const InstrSchedule& _schedule);
117 static _Self end( const InstrSchedule& _schedule);
120 inline _Self& operator=(const _Self& x); // DISABLE -- DO NOT IMPLEMENT
121 void skipToNextInstr();
125 //----------------------------------------------------------------------
126 // class InstrSchedule:
128 // Represents the schedule of machine instructions for a single basic block.
129 //----------------------------------------------------------------------
131 class InstrSchedule: public NonCopyable {
133 const unsigned int nslots;
134 unsigned int numInstr;
135 vector<InstrGroup*> groups; // indexed by cycle number
136 vector<cycles_t> startTime; // indexed by node id
139 typedef ScheduleIterator<SchedGraphNode> iterator;
140 typedef ScheduleIterator<const SchedGraphNode> const_iterator;
143 const_iterator begin() const;
145 const_iterator end() const;
147 public: // constructors and destructor
148 /*ctor*/ InstrSchedule (unsigned int _nslots,
149 unsigned int _numNodes);
150 /*dtor*/ ~InstrSchedule ();
152 public: // accessor functions to query chosen schedule
153 const SchedGraphNode* getInstr (unsigned int slotNum,
155 const InstrGroup* igroup = this->getIGroup(c);
156 return (igroup == NULL)? NULL : (*igroup)[slotNum];
159 inline InstrGroup* getIGroup (cycles_t c) {
160 if ((unsigned)c >= groups.size())
162 if (groups[c] == NULL)
163 groups[c] = new InstrGroup(nslots);
167 inline const InstrGroup* getIGroup (cycles_t c) const {
168 assert((unsigned)c < groups.size());
172 inline cycles_t getStartTime (unsigned int nodeId) const {
173 assert(nodeId < startTime.size());
174 return startTime[nodeId];
177 unsigned int getNumInstructions() const {
181 inline void scheduleInstr (const SchedGraphNode* node,
182 unsigned int slotNum,
184 InstrGroup* igroup = this->getIGroup(cycle);
185 assert((*igroup)[slotNum] == NULL && "Slot already filled?");
186 igroup->addInstr(node, slotNum);
187 assert(node->getNodeId() < startTime.size());
188 startTime[node->getNodeId()] = cycle;
193 friend class iterator;
194 friend class const_iterator;
195 /*ctor*/ InstrSchedule (); // Disable: DO NOT IMPLEMENT.
200 InstrSchedule::InstrSchedule(unsigned int _nslots, unsigned int _numNodes)
203 groups(2 * _numNodes / _nslots), // 2 x lower-bound for #cycles
204 startTime(_numNodes, (cycles_t) -1) // set all to -1
210 InstrSchedule::~InstrSchedule()
212 for (unsigned c=0, NC=groups.size(); c < NC; c++)
213 if (groups[c] != NULL)
214 delete groups[c]; // delete InstrGroup objects
218 template<class _NodeType>
221 ScheduleIterator<_NodeType>::skipToNextInstr()
223 while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
224 ++cycleNum; // skip cycles with no instructions
226 while (cycleNum < S.groups.size() &&
227 (*S.groups[cycleNum])[slotNum] == NULL)
230 if (slotNum == S.nslots)
234 while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
235 ++cycleNum; // skip cycles with no instructions
240 template<class _NodeType>
242 ScheduleIterator<_NodeType>&
243 ScheduleIterator<_NodeType>::operator++() // Preincrement
246 if (slotNum == S.nslots)
255 template<class _NodeType>
256 ScheduleIterator<_NodeType>
257 ScheduleIterator<_NodeType>::begin(const InstrSchedule& _schedule)
259 return _Self(_schedule, 0, 0);
262 template<class _NodeType>
263 ScheduleIterator<_NodeType>
264 ScheduleIterator<_NodeType>::end(const InstrSchedule& _schedule)
266 return _Self(_schedule, _schedule.groups.size(), 0);
269 InstrSchedule::iterator
270 InstrSchedule::begin()
272 return iterator::begin(*this);
275 InstrSchedule::const_iterator
276 InstrSchedule::begin() const
278 return const_iterator::begin(*this);
281 InstrSchedule::iterator
284 return iterator::end(*this);
287 InstrSchedule::const_iterator
288 InstrSchedule::end() const
290 return const_iterator::end( *this);
294 //----------------------------------------------------------------------
295 // class DelaySlotInfo:
297 // Record information about delay slots for a single branch instruction.
298 // Delay slots are simply indexed by slot number 1 ... numDelaySlots
299 //----------------------------------------------------------------------
301 class DelaySlotInfo: public NonCopyable {
303 const SchedGraphNode* brNode;
304 unsigned int ndelays;
305 vector<const SchedGraphNode*> delayNodeVec;
306 cycles_t delayedNodeCycle;
307 unsigned int delayedNodeSlotNum;
310 /*ctor*/ DelaySlotInfo (const SchedGraphNode* _brNode,
312 : brNode(_brNode), ndelays(_ndelays),
313 delayedNodeCycle(0), delayedNodeSlotNum(0) {}
315 inline unsigned getNumDelays () {
319 inline const vector<const SchedGraphNode*>& getDelayNodeVec() {
323 inline void addDelayNode (const SchedGraphNode* node) {
324 delayNodeVec.push_back(node);
325 assert(delayNodeVec.size() <= ndelays && "Too many delay slot instrs!");
328 inline void recordChosenSlot (cycles_t cycle, unsigned slotNum) {
329 delayedNodeCycle = cycle;
330 delayedNodeSlotNum = slotNum;
333 unsigned scheduleDelayedNode (SchedulingManager& S);
337 //----------------------------------------------------------------------
338 // class SchedulingManager:
340 // Represents the schedule of machine instructions for a single basic block.
341 //----------------------------------------------------------------------
343 class SchedulingManager: public NonCopyable {
344 public: // publicly accessible data members
345 const unsigned int nslots;
346 const MachineSchedInfo& schedInfo;
347 SchedPriorities& schedPrio;
348 InstrSchedule isched;
351 unsigned int totalInstrCount;
353 cycles_t nextEarliestIssueTime; // next cycle we can issue
354 vector<std::hash_set<const SchedGraphNode*> > choicesForSlot; // indexed by slot#
355 vector<const SchedGraphNode*> choiceVec; // indexed by node ptr
356 vector<int> numInClass; // indexed by sched class
357 vector<cycles_t> nextEarliestStartTime; // indexed by opCode
358 std::hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches;
359 // indexed by branch node ptr
362 SchedulingManager(const TargetMachine& _target, const SchedGraph* graph,
363 SchedPriorities& schedPrio);
364 ~SchedulingManager() {
365 for (std::hash_map<const SchedGraphNode*,
366 DelaySlotInfo*>::iterator I = delaySlotInfoForBranches.begin(),
367 E = delaySlotInfoForBranches.end(); I != E; ++I)
371 //----------------------------------------------------------------------
372 // Simplify access to the machine instruction info
373 //----------------------------------------------------------------------
375 inline const MachineInstrInfo& getInstrInfo () const {
376 return schedInfo.getInstrInfo();
379 //----------------------------------------------------------------------
380 // Interface for checking and updating the current time
381 //----------------------------------------------------------------------
383 inline cycles_t getTime () const {
387 inline cycles_t getEarliestIssueTime() const {
388 return nextEarliestIssueTime;
391 inline cycles_t getEarliestStartTimeForOp(MachineOpCode opCode) const {
392 assert(opCode < (int) nextEarliestStartTime.size());
393 return nextEarliestStartTime[opCode];
396 // Update current time to specified cycle
397 inline void updateTime (cycles_t c) {
399 schedPrio.updateTime(c);
402 //----------------------------------------------------------------------
403 // Functions to manage the choices for the current cycle including:
404 // -- a vector of choices by priority (choiceVec)
405 // -- vectors of the choices for each instruction slot (choicesForSlot[])
406 // -- number of choices in each sched class, used to check issue conflicts
407 // between choices for a single cycle
408 //----------------------------------------------------------------------
410 inline unsigned int getNumChoices () const {
411 return choiceVec.size();
414 inline unsigned getNumChoicesInClass (const InstrSchedClass& sc) const {
415 assert(sc < (int) numInClass.size() && "Invalid op code or sched class!");
416 return numInClass[sc];
419 inline const SchedGraphNode* getChoice(unsigned int i) const {
420 // assert(i < choiceVec.size()); don't check here.
424 inline std::hash_set<const SchedGraphNode*>& getChoicesForSlot(unsigned slotNum) {
425 assert(slotNum < nslots);
426 return choicesForSlot[slotNum];
429 inline void addChoice (const SchedGraphNode* node) {
430 // Append the instruction to the vector of choices for current cycle.
431 // Increment numInClass[c] for the sched class to which the instr belongs.
432 choiceVec.push_back(node);
433 const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
434 assert(sc < (int) numInClass.size());
438 inline void addChoiceToSlot (unsigned int slotNum,
439 const SchedGraphNode* node) {
440 // Add the instruction to the choice set for the specified slot
441 assert(slotNum < nslots);
442 choicesForSlot[slotNum].insert(node);
445 inline void resetChoices () {
447 for (unsigned int s=0; s < nslots; s++)
448 choicesForSlot[s].clear();
449 for (unsigned int c=0; c < numInClass.size(); c++)
453 //----------------------------------------------------------------------
454 // Code to query and manage the partial instruction schedule so far
455 //----------------------------------------------------------------------
457 inline unsigned int getNumScheduled () const {
458 return isched.getNumInstructions();
461 inline unsigned int getNumUnscheduled() const {
462 return totalInstrCount - isched.getNumInstructions();
465 inline bool isScheduled (const SchedGraphNode* node) const {
466 return (isched.getStartTime(node->getNodeId()) >= 0);
469 inline void scheduleInstr (const SchedGraphNode* node,
470 unsigned int slotNum,
473 assert(! isScheduled(node) && "Instruction already scheduled?");
475 // add the instruction to the schedule
476 isched.scheduleInstr(node, slotNum, cycle);
478 // update the earliest start times of all nodes that conflict with `node'
479 // and the next-earliest time anything can issue if `node' causes bubbles
480 updateEarliestStartTimes(node, cycle);
482 // remove the instruction from the choice sets for all slots
483 for (unsigned s=0; s < nslots; s++)
484 choicesForSlot[s].erase(node);
486 // and decrement the instr count for the sched class to which it belongs
487 const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
488 assert(sc < (int) numInClass.size());
492 //----------------------------------------------------------------------
493 // Create and retrieve delay slot info for delayed instructions
494 //----------------------------------------------------------------------
496 inline DelaySlotInfo* getDelaySlotInfoForInstr(const SchedGraphNode* bn,
497 bool createIfMissing=false)
499 std::hash_map<const SchedGraphNode*, DelaySlotInfo*>::const_iterator
500 I = delaySlotInfoForBranches.find(bn);
501 if (I != delaySlotInfoForBranches.end())
504 if (!createIfMissing) return 0;
506 DelaySlotInfo *dinfo =
507 new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpCode()));
508 return delaySlotInfoForBranches[bn] = dinfo;
512 SchedulingManager(); // DISABLED: DO NOT IMPLEMENT
513 void updateEarliestStartTimes(const SchedGraphNode* node, cycles_t schedTime);
518 SchedulingManager::SchedulingManager(const TargetMachine& target,
519 const SchedGraph* graph,
520 SchedPriorities& _schedPrio)
521 : nslots(target.getSchedInfo().getMaxNumIssueTotal()),
522 schedInfo(target.getSchedInfo()),
523 schedPrio(_schedPrio),
524 isched(nslots, graph->getNumNodes()),
525 totalInstrCount(graph->getNumNodes() - 2),
526 nextEarliestIssueTime(0),
527 choicesForSlot(nslots),
528 numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0
529 nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
530 (cycles_t) 0) // set all to 0
534 // Note that an upper bound on #choices for each slot is = nslots since
535 // we use this vector to hold a feasible set of instructions, and more
536 // would be infeasible. Reserve that much memory since it is probably small.
537 for (unsigned int i=0; i < nslots; i++)
538 choicesForSlot[i].resize(nslots);
543 SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
546 if (schedInfo.numBubblesAfter(node->getOpCode()) > 0)
547 { // Update next earliest time before which *nothing* can issue.
548 nextEarliestIssueTime = std::max(nextEarliestIssueTime,
549 curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode()));
552 const vector<MachineOpCode>*
553 conflictVec = schedInfo.getConflictList(node->getOpCode());
555 if (conflictVec != NULL)
556 for (unsigned i=0; i < conflictVec->size(); i++)
558 MachineOpCode toOp = (*conflictVec)[i];
559 cycles_t est = schedTime + schedInfo.getMinIssueGap(node->getOpCode(),
561 assert(toOp < (int) nextEarliestStartTime.size());
562 if (nextEarliestStartTime[toOp] < est)
563 nextEarliestStartTime[toOp] = est;
567 //************************* Internal Functions *****************************/
571 AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
573 // find the slot to start from, in the current cycle
574 unsigned int startSlot = 0;
575 cycles_t curTime = S.getTime();
577 assert(maxIssue > 0 && maxIssue <= S.nslots - startSlot);
579 // If only one instruction can be issued, do so.
581 for (unsigned s=startSlot; s < S.nslots; s++)
582 if (S.getChoicesForSlot(s).size() > 0)
583 {// found the one instruction
584 S.scheduleInstr(*S.getChoicesForSlot(s).begin(), s, curTime);
588 // Otherwise, choose from the choices for each slot
590 InstrGroup* igroup = S.isched.getIGroup(S.getTime());
591 assert(igroup != NULL && "Group creation failed?");
593 // Find a slot that has only a single choice, and take it.
594 // If all slots have 0 or multiple choices, pick the first slot with
595 // choices and use its last instruction (just to avoid shifting the vector).
597 for (numIssued = 0; numIssued < maxIssue; numIssued++)
600 for (unsigned s=startSlot; s < S.nslots; s++)
601 if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1)
603 chosenSlot = (int) s;
607 if (chosenSlot == -1)
608 for (unsigned s=startSlot; s < S.nslots; s++)
609 if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0)
611 chosenSlot = (int) s;
615 if (chosenSlot != -1)
616 { // Insert the chosen instr in the chosen slot and
617 // erase it from all slots.
618 const SchedGraphNode* node= *S.getChoicesForSlot(chosenSlot).begin();
619 S.scheduleInstr(node, chosenSlot, curTime);
623 assert(numIssued > 0 && "Should not happen when maxIssue > 0!");
628 // For now, just assume we are scheduling within a single basic block.
629 // Get the machine instruction vector for the basic block and clear it,
630 // then append instructions in scheduled order.
631 // Also, re-insert the dummy PHI instructions that were at the beginning
632 // of the basic block, since they are not part of the schedule.
635 RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
637 MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
638 const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
641 // Lets make sure we didn't lose any instructions, except possibly
642 // some NOPs from delay slots. Also, PHIs are not included in the schedule.
643 unsigned numInstr = 0;
644 for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
645 if (! mii.isNop((*I)->getOpCode()) &&
646 ! mii.isDummyPhiInstr((*I)->getOpCode()))
648 assert(S.isched.getNumInstructions() >= numInstr &&
649 "Lost some non-NOP instructions during scheduling!");
652 if (S.isched.getNumInstructions() == 0)
653 return; // empty basic block!
655 // First find the dummy instructions at the start of the basic block
656 MachineCodeForBasicBlock::iterator I = mvec.begin();
657 for ( ; I != mvec.end(); ++I)
658 if (! mii.isDummyPhiInstr((*I)->getOpCode()))
661 // Erase all except the dummy PHI instructions from mvec, and
662 // pre-allocate create space for the ones we will put back in.
663 mvec.erase(I, mvec.end());
665 InstrSchedule::const_iterator NIend = S.isched.end();
666 for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
667 mvec.push_back(const_cast<MachineInstr*>((*NI)->getMachineInstr()));
673 MarkSuccessorsReady(SchedulingManager& S, const SchedGraphNode* node)
675 // Check if any successors are now ready that were not already marked
676 // ready before, and that have not yet been scheduled.
678 for (sg_succ_const_iterator SI = succ_begin(node); SI !=succ_end(node); ++SI)
679 if (! (*SI)->isDummyNode()
680 && ! S.isScheduled(*SI)
681 && ! S.schedPrio.nodeIsReady(*SI))
682 {// successor not scheduled and not marked ready; check *its* preds.
684 bool succIsReady = true;
685 for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P)
686 if (! (*P)->isDummyNode()
687 && ! S.isScheduled(*P))
693 if (succIsReady) // add the successor to the ready list
694 S.schedPrio.insertReady(*SI);
699 // Choose up to `nslots' FEASIBLE instructions and assign each
700 // instruction to all possible slots that do not violate feasibility.
701 // FEASIBLE means it should be guaranteed that the set
702 // of chosen instructions can be issued in a single group.
705 // maxIssue : total number of feasible instructions
706 // S.choicesForSlot[i=0..nslots] : set of instructions feasible in slot i
709 FindSlotChoices(SchedulingManager& S,
710 DelaySlotInfo*& getDelaySlotInfo)
712 // initialize result vectors to empty
715 // find the slot to start from, in the current cycle
716 unsigned int startSlot = 0;
717 InstrGroup* igroup = S.isched.getIGroup(S.getTime());
718 for (int s = S.nslots - 1; s >= 0; s--)
719 if ((*igroup)[s] != NULL)
725 // Make sure we pick at most one instruction that would break the group.
726 // Also, if we do pick one, remember which it was.
727 unsigned int indexForBreakingNode = S.nslots;
728 unsigned int indexForDelayedInstr = S.nslots;
729 DelaySlotInfo* delaySlotInfo = NULL;
731 getDelaySlotInfo = NULL;
733 // Choose instructions in order of priority.
734 // Add choices to the choice vector in the SchedulingManager class as
735 // we choose them so that subsequent choices will be correctly tested
736 // for feasibility, w.r.t. higher priority choices for the same cycle.
738 while (S.getNumChoices() < S.nslots - startSlot)
740 const SchedGraphNode* nextNode=S.schedPrio.getNextHighest(S,S.getTime());
741 if (nextNode == NULL)
742 break; // no more instructions for this cycle
744 if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0)
746 delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
747 if (delaySlotInfo != NULL)
749 if (indexForBreakingNode < S.nslots)
750 // cannot issue a delayed instr in the same cycle as one
751 // that breaks the issue group or as another delayed instr
754 indexForDelayedInstr = S.getNumChoices();
757 else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode()))
759 if (indexForBreakingNode < S.nslots)
760 // have a breaking instruction already so throw this one away
763 indexForBreakingNode = S.getNumChoices();
766 if (nextNode != NULL)
768 S.addChoice(nextNode);
770 if (S.schedInfo.isSingleIssue(nextNode->getOpCode()))
772 assert(S.getNumChoices() == 1 &&
773 "Prioritizer returned invalid instr for this cycle!");
778 if (indexForDelayedInstr < S.nslots)
779 break; // leave the rest for delay slots
782 assert(S.getNumChoices() <= S.nslots);
783 assert(! (indexForDelayedInstr < S.nslots &&
784 indexForBreakingNode < S.nslots) && "Cannot have both in a cycle");
786 // Assign each chosen instruction to all possible slots for that instr.
787 // But if only one instruction was chosen, put it only in the first
788 // feasible slot; no more analysis will be needed.
790 if (indexForDelayedInstr >= S.nslots &&
791 indexForBreakingNode >= S.nslots)
792 { // No instructions that break the issue group or that have delay slots.
793 // This is the common case, so handle it separately for efficiency.
795 if (S.getNumChoices() == 1)
797 MachineOpCode opCode = S.getChoice(0)->getOpCode();
799 for (s=startSlot; s < S.nslots; s++)
800 if (S.schedInfo.instrCanUseSlot(opCode, s))
802 assert(s < S.nslots && "No feasible slot for this opCode?");
803 S.addChoiceToSlot(s, S.getChoice(0));
807 for (unsigned i=0; i < S.getNumChoices(); i++)
809 MachineOpCode opCode = S.getChoice(i)->getOpCode();
810 for (unsigned int s=startSlot; s < S.nslots; s++)
811 if (S.schedInfo.instrCanUseSlot(opCode, s))
812 S.addChoiceToSlot(s, S.getChoice(i));
816 else if (indexForDelayedInstr < S.nslots)
818 // There is an instruction that needs delay slots.
819 // Try to assign that instruction to a higher slot than any other
820 // instructions in the group, so that its delay slots can go
824 assert(indexForDelayedInstr == S.getNumChoices() - 1 &&
825 "Instruction with delay slots should be last choice!");
826 assert(delaySlotInfo != NULL && "No delay slot info for instr?");
828 const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
829 MachineOpCode delayOpCode = delayedNode->getOpCode();
830 unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
832 unsigned delayedNodeSlot = S.nslots;
835 // Find the last possible slot for the delayed instruction that leaves
836 // at least `d' slots vacant after it (d = #delay slots)
837 for (int s = S.nslots-ndelays-1; s >= (int) startSlot; s--)
838 if (S.schedInfo.instrCanUseSlot(delayOpCode, s))
844 highestSlotUsed = -1;
845 for (unsigned i=0; i < S.getNumChoices() - 1; i++)
847 // Try to assign every other instruction to a lower numbered
848 // slot than delayedNodeSlot.
849 MachineOpCode opCode =S.getChoice(i)->getOpCode();
850 bool noSlotFound = true;
852 for (s=startSlot; s < delayedNodeSlot; s++)
853 if (S.schedInfo.instrCanUseSlot(opCode, s))
855 S.addChoiceToSlot(s, S.getChoice(i));
859 // No slot before `delayedNodeSlot' was found for this opCode
860 // Use a later slot, and allow some delay slots to fall in
863 for ( ; s < S.nslots; s++)
864 if (S.schedInfo.instrCanUseSlot(opCode, s))
866 S.addChoiceToSlot(s, S.getChoice(i));
870 assert(s < S.nslots && "No feasible slot for instruction?");
872 highestSlotUsed = std::max(highestSlotUsed, (int) s);
875 assert(highestSlotUsed <= (int) S.nslots-1 && "Invalid slot used?");
877 // We will put the delayed node in the first slot after the
878 // highest slot used. But we just mark that for now, and
879 // schedule it separately because we want to schedule the delay
880 // slots for the node at the same time.
881 cycles_t dcycle = S.getTime();
882 unsigned int dslot = highestSlotUsed + 1;
883 if (dslot == S.nslots)
888 delaySlotInfo->recordChosenSlot(dcycle, dslot);
889 getDelaySlotInfo = delaySlotInfo;
892 { // There is an instruction that breaks the issue group.
893 // For such an instruction, assign to the last possible slot in
894 // the current group, and then don't assign any other instructions
896 assert(indexForBreakingNode < S.nslots);
897 const SchedGraphNode* breakingNode=S.getChoice(indexForBreakingNode);
898 unsigned breakingSlot = INT_MAX;
899 unsigned int nslotsToUse = S.nslots;
901 // Find the last possible slot for this instruction.
902 for (int s = S.nslots-1; s >= (int) startSlot; s--)
903 if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s))
908 assert(breakingSlot < S.nslots &&
909 "No feasible slot for `breakingNode'?");
911 // Higher priority instructions than the one that breaks the group:
912 // These can be assigned to all slots, but will be assigned only
913 // to earlier slots if possible.
915 i < S.getNumChoices() && i < indexForBreakingNode; i++)
917 MachineOpCode opCode =S.getChoice(i)->getOpCode();
919 // If a higher priority instruction cannot be assigned to
920 // any earlier slots, don't schedule the breaking instruction.
922 bool foundLowerSlot = false;
923 nslotsToUse = S.nslots; // May be modified in the loop
924 for (unsigned int s=startSlot; s < nslotsToUse; s++)
925 if (S.schedInfo.instrCanUseSlot(opCode, s))
927 if (breakingSlot < S.nslots && s < breakingSlot)
929 foundLowerSlot = true;
930 nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND!
933 S.addChoiceToSlot(s, S.getChoice(i));
937 breakingSlot = INT_MAX; // disable breaking instr
940 // Assign the breaking instruction (if any) to a single slot
941 // Otherwise, just ignore the instruction. It will simply be
942 // scheduled in a later cycle.
943 if (breakingSlot < S.nslots)
945 S.addChoiceToSlot(breakingSlot, breakingNode);
946 nslotsToUse = breakingSlot;
949 nslotsToUse = S.nslots;
951 // For lower priority instructions than the one that breaks the
952 // group, only assign them to slots lower than the breaking slot.
953 // Otherwise, just ignore the instruction.
954 for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++)
956 MachineOpCode opCode = S.getChoice(i)->getOpCode();
957 for (unsigned int s=startSlot; s < nslotsToUse; s++)
958 if (S.schedInfo.instrCanUseSlot(opCode, s))
959 S.addChoiceToSlot(s, S.getChoice(i));
961 } // endif (no delay slots and no breaking slots)
963 return S.getNumChoices();
968 ChooseOneGroup(SchedulingManager& S)
970 assert(S.schedPrio.getNumReady() > 0
971 && "Don't get here without ready instructions.");
973 cycles_t firstCycle = S.getTime();
974 DelaySlotInfo* getDelaySlotInfo = NULL;
976 // Choose up to `nslots' feasible instructions and their possible slots.
977 unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
979 while (numIssued == 0)
981 S.updateTime(S.getTime()+1);
982 numIssued = FindSlotChoices(S, getDelaySlotInfo);
985 AssignInstructionsToSlots(S, numIssued);
987 if (getDelaySlotInfo != NULL)
988 numIssued += getDelaySlotInfo->scheduleDelayedNode(S);
990 // Print trace of scheduled instructions before newly ready ones
991 if (SchedDebugLevel >= Sched_PrintSchedTrace)
993 for (cycles_t c = firstCycle; c <= S.getTime(); c++)
995 cerr << " Cycle " << (long)c << " : Scheduled instructions:\n";
996 const InstrGroup* igroup = S.isched.getIGroup(c);
997 for (unsigned int s=0; s < S.nslots; s++)
1000 if ((*igroup)[s] != NULL)
1001 cerr << * ((*igroup)[s])->getMachineInstr() << "\n";
1013 ForwardListSchedule(SchedulingManager& S)
1016 const SchedGraphNode* node;
1018 S.schedPrio.initialize();
1020 while ((N = S.schedPrio.getNumReady()) > 0)
1022 cycles_t nextCycle = S.getTime();
1024 // Choose one group of instructions for a cycle, plus any delay slot
1025 // instructions (which may overflow into successive cycles).
1026 // This will advance S.getTime() to the last cycle in which
1027 // instructions are actually issued.
1029 unsigned numIssued = ChooseOneGroup(S);
1030 assert(numIssued > 0 && "Deadlock in list scheduling algorithm?");
1032 // Notify the priority manager of scheduled instructions and mark
1033 // any successors that may now be ready
1035 for (cycles_t c = nextCycle; c <= S.getTime(); c++)
1037 const InstrGroup* igroup = S.isched.getIGroup(c);
1038 for (unsigned int s=0; s < S.nslots; s++)
1039 if ((node = (*igroup)[s]) != NULL)
1041 S.schedPrio.issuedReadyNodeAt(S.getTime(), node);
1042 MarkSuccessorsReady(S, node);
1046 // Move to the next the next earliest cycle for which
1047 // an instruction can be issued, or the next earliest in which
1048 // one will be ready, or to the next cycle, whichever is latest.
1050 S.updateTime(std::max(S.getTime() + 1,
1051 std::max(S.getEarliestIssueTime(),
1052 S.schedPrio.getEarliestReadyTime())));
1057 //---------------------------------------------------------------------
1058 // Code for filling delay slots for delayed terminator instructions
1059 // (e.g., BRANCH and RETURN). Delay slots for non-terminator
1060 // instructions (e.g., CALL) are not handled here because they almost
1061 // always can be filled with instructions from the call sequence code
1062 // before a call. That's preferable because we incur many tradeoffs here
1063 // when we cannot find single-cycle instructions that can be reordered.
1064 //----------------------------------------------------------------------
1067 NodeCanFillDelaySlot(const SchedulingManager& S,
1068 const SchedGraphNode* node,
1069 const SchedGraphNode* brNode,
1070 bool nodeIsPredecessor)
1072 assert(! node->isDummyNode());
1074 // don't put a branch in the delay slot of another branch
1075 if (S.getInstrInfo().isBranch(node->getOpCode()))
1078 // don't put a single-issue instruction in the delay slot of a branch
1079 if (S.schedInfo.isSingleIssue(node->getOpCode()))
1082 // don't put a load-use dependence in the delay slot of a branch
1083 const MachineInstrInfo& mii = S.getInstrInfo();
1085 for (SchedGraphNode::const_iterator EI = node->beginInEdges();
1086 EI != node->endInEdges(); ++EI)
1087 if (! (*EI)->getSrc()->isDummyNode()
1088 && mii.isLoad((*EI)->getSrc()->getOpCode())
1089 && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
1092 // for now, don't put an instruction that does not have operand
1093 // interlocks in the delay slot of a branch
1094 if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
1097 // Finally, if the instruction preceeds the branch, we make sure the
1098 // instruction can be reordered relative to the branch. We simply check
1099 // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
1101 if (nodeIsPredecessor)
1103 bool onlyCDEdgeToBranch = true;
1104 for (SchedGraphNode::const_iterator OEI = node->beginOutEdges();
1105 OEI != node->endOutEdges(); ++OEI)
1106 if (! (*OEI)->getSink()->isDummyNode()
1107 && ((*OEI)->getSink() != brNode
1108 || (*OEI)->getDepType() != SchedGraphEdge::CtrlDep))
1110 onlyCDEdgeToBranch = false;
1114 if (!onlyCDEdgeToBranch)
1123 MarkNodeForDelaySlot(SchedulingManager& S,
1125 SchedGraphNode* node,
1126 const SchedGraphNode* brNode,
1127 bool nodeIsPredecessor)
1129 if (nodeIsPredecessor)
1130 { // If node is in the same basic block (i.e., preceeds brNode),
1131 // remove it and all its incident edges from the graph. Make sure we
1132 // add dummy edges for pred/succ nodes that become entry/exit nodes.
1133 graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
1136 { // If the node was from a target block, add the node to the graph
1137 // and add a CD edge from brNode to node.
1138 assert(0 && "NOT IMPLEMENTED YET");
1141 DelaySlotInfo* dinfo = S.getDelaySlotInfoForInstr(brNode, /*create*/ true);
1142 dinfo->addDelayNode(node);
1147 FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
1148 SchedGraphNode* brNode,
1149 vector<SchedGraphNode*>& sdelayNodeVec)
1151 const MachineInstrInfo& mii = S.getInstrInfo();
1153 mii.getNumDelaySlots(brNode->getOpCode());
1158 sdelayNodeVec.reserve(ndelays);
1160 // Use a separate vector to hold the feasible multi-cycle nodes.
1161 // These will be used if not enough single-cycle nodes are found.
1163 vector<SchedGraphNode*> mdelayNodeVec;
1165 for (sg_pred_iterator P = pred_begin(brNode);
1166 P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
1167 if (! (*P)->isDummyNode() &&
1168 ! mii.isNop((*P)->getOpCode()) &&
1169 NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
1171 if (mii.maxLatency((*P)->getOpCode()) > 1)
1172 mdelayNodeVec.push_back(*P);
1174 sdelayNodeVec.push_back(*P);
1177 // If not enough single-cycle instructions were found, select the
1178 // lowest-latency multi-cycle instructions and use them.
1179 // Note that this is the most efficient code when only 1 (or even 2)
1180 // values need to be selected.
1182 while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0)
1185 mii.maxLatency(mdelayNodeVec[0]->getOpCode());
1186 unsigned minIndex = 0;
1187 for (unsigned i=1; i < mdelayNodeVec.size(); i++)
1190 mii.maxLatency(mdelayNodeVec[i]->getOpCode());
1197 sdelayNodeVec.push_back(mdelayNodeVec[minIndex]);
1198 if (sdelayNodeVec.size() < ndelays) // avoid the last erase!
1199 mdelayNodeVec.erase(mdelayNodeVec.begin() + minIndex);
1204 // Remove the NOPs currently in delay slots from the graph.
1205 // Mark instructions specified in sdelayNodeVec to replace them.
1206 // If not enough useful instructions were found, mark the NOPs to be used
1207 // for filling delay slots, otherwise, otherwise just discard them.
1210 ReplaceNopsWithUsefulInstr(SchedulingManager& S,
1211 SchedGraphNode* node,
1212 vector<SchedGraphNode*> sdelayNodeVec,
1215 vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
1216 const MachineInstrInfo& mii = S.getInstrInfo();
1217 const MachineInstr* brInstr = node->getMachineInstr();
1218 unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
1219 assert(ndelays > 0 && "Unnecessary call to replace NOPs");
1221 // Remove the NOPs currently in delay slots from the graph.
1222 // If not enough useful instructions were found, use the NOPs to
1223 // fill delay slots, otherwise, just discard them.
1225 unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
1226 MachineCodeForBasicBlock& bbMvec = node->getBB()->getMachineInstrVec();
1227 assert(bbMvec[firstDelaySlotIdx - 1] == brInstr &&
1228 "Incorrect instr. index in basic block for brInstr");
1230 // First find all useful instructions already in the delay slots
1231 // and USE THEM. We'll throw away the unused alternatives below
1233 for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
1234 if (! mii.isNop(bbMvec[i]->getOpCode()))
1235 sdelayNodeVec.insert(sdelayNodeVec.begin(),
1236 graph->getGraphNodeForInstr(bbMvec[i]));
1238 // Then find the NOPs and keep only as many as are needed.
1239 // Put the rest in nopNodeVec to be deleted.
1240 for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
1241 if (mii.isNop(bbMvec[i]->getOpCode()))
1242 if (sdelayNodeVec.size() < ndelays)
1243 sdelayNodeVec.push_back(graph->getGraphNodeForInstr(bbMvec[i]));
1245 nopNodeVec.push_back(graph->getGraphNodeForInstr(bbMvec[i]));
1247 assert(sdelayNodeVec.size() >= ndelays);
1249 // If some delay slots were already filled, throw away that many new choices
1250 if (sdelayNodeVec.size() > ndelays)
1251 sdelayNodeVec.resize(ndelays);
1253 // Mark the nodes chosen for delay slots. This removes them from the graph.
1254 for (unsigned i=0; i < sdelayNodeVec.size(); i++)
1255 MarkNodeForDelaySlot(S, graph, sdelayNodeVec[i], node, true);
1257 // And remove the unused NOPs from the graph.
1258 for (unsigned i=0; i < nopNodeVec.size(); i++)
1259 graph->eraseIncidentEdges(nopNodeVec[i], /*addDummyEdges*/ true);
1263 // For all delayed instructions, choose instructions to put in the delay
1264 // slots and pull those out of the graph. Mark them for the delay slots
1265 // in the DelaySlotInfo object for that graph node. If no useful work
1266 // is found for a delay slot, use the NOP that is currently in that slot.
1268 // We try to fill the delay slots with useful work for all instructions
1269 // EXCEPT CALLS AND RETURNS.
1270 // For CALLs and RETURNs, it is nearly always possible to use one of the
1271 // call sequence instrs and putting anything else in the delay slot could be
1272 // suboptimal. Also, it complicates generating the calling sequence code in
1276 ChooseInstructionsForDelaySlots(SchedulingManager& S,
1277 const BasicBlock *bb,
1280 const MachineInstrInfo& mii = S.getInstrInfo();
1281 const Instruction *termInstr = (Instruction*)bb->getTerminator();
1282 MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);
1283 vector<SchedGraphNode*> delayNodeVec;
1284 const MachineInstr* brInstr = NULL;
1286 if (termInstr->getOpcode() != Instruction::Ret)
1288 // To find instructions that need delay slots without searching the full
1289 // machine code, we assume that the only delayed instructions are CALLs
1290 // or instructions generated for the terminator inst.
1291 // Find the first branch instr in the sequence of machine instrs for term
1294 while (first < termMvec.size() &&
1295 ! mii.isBranch(termMvec[first]->getOpCode()))
1299 assert(first < termMvec.size() &&
1300 "No branch instructions for BR? Ok, but weird! Delete assertion.");
1302 brInstr = (first < termMvec.size())? termMvec[first] : NULL;
1304 // Compute a vector of the nodes chosen for delay slots and then
1305 // mark delay slots to replace NOPs with these useful instructions.
1307 if (brInstr != NULL)
1309 SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr);
1310 FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec);
1311 ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph);
1315 // Also mark delay slots for other delayed instructions to hold NOPs.
1316 // Simply passing in an empty delayNodeVec will have this effect.
1318 delayNodeVec.clear();
1319 const MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
1320 for (unsigned i=0; i < bbMvec.size(); i++)
1321 if (bbMvec[i] != brInstr &&
1322 mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
1324 SchedGraphNode* node = graph->getGraphNodeForInstr(bbMvec[i]);
1325 ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
1331 // Schedule the delayed branch and its delay slots
1334 DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
1336 assert(delayedNodeSlotNum < S.nslots && "Illegal slot for branch");
1337 assert(S.isched.getInstr(delayedNodeSlotNum, delayedNodeCycle) == NULL
1338 && "Slot for branch should be empty");
1340 unsigned int nextSlot = delayedNodeSlotNum;
1341 cycles_t nextTime = delayedNodeCycle;
1343 S.scheduleInstr(brNode, nextSlot, nextTime);
1345 for (unsigned d=0; d < ndelays; d++)
1348 if (nextSlot == S.nslots)
1354 // Find the first feasible instruction for this delay slot
1355 // Note that we only check for issue restrictions here.
1356 // We do *not* check for flow dependences but rely on pipeline
1357 // interlocks to resolve them. Machines without interlocks
1358 // will require this code to be modified.
1359 for (unsigned i=0; i < delayNodeVec.size(); i++)
1361 const SchedGraphNode* dnode = delayNodeVec[i];
1362 if ( ! S.isScheduled(dnode)
1363 && S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
1364 && instrIsFeasible(S, dnode->getOpCode()))
1366 assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpCode())
1367 && "Instructions without interlocks not yet supported "
1368 "when filling branch delay slots");
1369 S.scheduleInstr(dnode, nextSlot, nextTime);
1375 // Update current time if delay slots overflowed into later cycles.
1376 // Do this here because we know exactly which cycle is the last cycle
1377 // that contains delay slots. The next loop doesn't compute that.
1378 if (nextTime > S.getTime())
1379 S.updateTime(nextTime);
1381 // Now put any remaining instructions in the unfilled delay slots.
1382 // This could lead to suboptimal performance but needed for correctness.
1383 nextSlot = delayedNodeSlotNum;
1384 nextTime = delayedNodeCycle;
1385 for (unsigned i=0; i < delayNodeVec.size(); i++)
1386 if (! S.isScheduled(delayNodeVec[i]))
1388 do { // find the next empty slot
1390 if (nextSlot == S.nslots)
1395 } while (S.isched.getInstr(nextSlot, nextTime) != NULL);
1397 S.scheduleInstr(delayNodeVec[i], nextSlot, nextTime);
1405 // Check if the instruction would conflict with instructions already
1406 // chosen for the current cycle
1409 ConflictsWithChoices(const SchedulingManager& S,
1410 MachineOpCode opCode)
1412 // Check if the instruction must issue by itself, and some feasible
1413 // choices have already been made for this cycle
1414 if (S.getNumChoices() > 0 && S.schedInfo.isSingleIssue(opCode))
1417 // For each class that opCode belongs to, check if there are too many
1418 // instructions of that class.
1420 const InstrSchedClass sc = S.schedInfo.getSchedClass(opCode);
1421 return (S.getNumChoicesInClass(sc) == S.schedInfo.getMaxIssueForClass(sc));
1425 //************************* External Functions *****************************/
1428 //---------------------------------------------------------------------------
1429 // Function: ViolatesMinimumGap
1432 // Check minimum gap requirements relative to instructions scheduled in
1434 // Note that we do not need to consider `nextEarliestIssueTime' here because
1435 // that is also captured in the earliest start times for each opcode.
1436 //---------------------------------------------------------------------------
1439 ViolatesMinimumGap(const SchedulingManager& S,
1440 MachineOpCode opCode,
1441 const cycles_t inCycle)
1443 return (inCycle < S.getEarliestStartTimeForOp(opCode));
1447 //---------------------------------------------------------------------------
1448 // Function: instrIsFeasible
1451 // Check if any issue restrictions would prevent the instruction from
1452 // being issued in the current cycle
1453 //---------------------------------------------------------------------------
1456 instrIsFeasible(const SchedulingManager& S,
1457 MachineOpCode opCode)
1459 // skip the instruction if it cannot be issued due to issue restrictions
1460 // caused by previously issued instructions
1461 if (ViolatesMinimumGap(S, opCode, S.getTime()))
1464 // skip the instruction if it cannot be issued due to issue restrictions
1465 // caused by previously chosen instructions for the current cycle
1466 if (ConflictsWithChoices(S, opCode))
1472 //---------------------------------------------------------------------------
1473 // Function: ScheduleInstructionsWithSSA
1476 // Entry point for instruction scheduling on SSA form.
1477 // Schedules the machine instructions generated by instruction selection.
1478 // Assumes that register allocation has not been done, i.e., operands
1479 // are still in SSA form.
1480 //---------------------------------------------------------------------------
1483 class InstructionSchedulingWithSSA : public FunctionPass {
1484 const TargetMachine ⌖
1486 inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
1488 // getAnalysisUsage - We use LiveVarInfo...
1489 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1490 AU.addRequired(FunctionLiveVarInfo::ID);
1493 bool runOnFunction(Function *F);
1495 } // end anonymous namespace
1499 InstructionSchedulingWithSSA::runOnFunction(Function *M)
1501 if (SchedDebugLevel == Sched_Disable)
1504 SchedGraphSet graphSet(M, target);
1506 if (SchedDebugLevel >= Sched_PrintSchedGraphs)
1508 cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
1512 for (SchedGraphSet::const_iterator GI=graphSet.begin(), GE=graphSet.end();
1515 SchedGraph* graph = (*GI);
1516 const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
1517 assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
1518 const BasicBlock* bb = bbvec[0];
1520 if (SchedDebugLevel >= Sched_PrintSchedTrace)
1521 cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
1524 SchedPriorities schedPrio(M, graph,getAnalysis<FunctionLiveVarInfo>());
1525 SchedulingManager S(target, graph, schedPrio);
1527 ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
1529 ForwardListSchedule(S); // computes schedule in S
1531 RecordSchedule(bb, S); // records schedule in BB
1534 if (SchedDebugLevel >= Sched_PrintMachineCode)
1536 cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
1537 MachineCodeForMethod::get(M).dump();
1544 Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) {
1545 return new InstructionSchedulingWithSSA(tgt);