2 //***************************************************************************
4 // InstrSelectionSupport.h
7 // Target-independent instruction selection code.
8 // See SparcInstrSelection.cpp for usage.
11 // 10/10/01 - Vikram Adve - Created
12 //**************************************************************************/
14 #include "llvm/CodeGen/InstrSelectionSupport.h"
15 #include "llvm/CodeGen/InstrSelection.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineCodeForInstruction.h"
18 #include "llvm/CodeGen/MachineCodeForMethod.h"
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/MachineRegInfo.h"
22 #include "llvm/ConstantVals.h"
23 #include "llvm/Method.h"
24 #include "llvm/BasicBlock.h"
25 #include "llvm/Type.h"
26 #include "llvm/iMemory.h"
29 //*************************** Local Functions ******************************/
32 static TmpInstruction*
33 InsertCodeToLoadConstant(Method* method,
36 vector<MachineInstr*>& loadConstVec,
37 TargetMachine& target)
39 vector<TmpInstruction*> tempVec;
41 // Create a tmp virtual register to hold the constant.
42 TmpInstruction* tmpReg = new TmpInstruction(opValue);
43 MachineCodeForInstruction &MCFI = MachineCodeForInstruction::get(vmInstr);
46 target.getInstrInfo().CreateCodeToLoadConst(method, opValue, tmpReg,
47 loadConstVec, tempVec);
49 // Register the new tmp values created for this m/c instruction sequence
50 for (unsigned i=0; i < tempVec.size(); i++)
51 MCFI.addTemp(tempVec[i]);
53 // Record the mapping from the tmp VM instruction to machine instruction.
54 // Do this for all machine instructions that were not mapped to any
55 // other temp values created by
56 // tmpReg->addMachineInstruction(loadConstVec.back());
62 //---------------------------------------------------------------------------
63 // Function GetConstantValueAsSignedInt
65 // Convenience function to get the value of an integer constant, for an
66 // appropriate integer or non-integer type that can be held in an integer.
67 // The type of the argument must be the following:
68 // Signed or unsigned integer
72 // isValidConstant is set to true if a valid constant was found.
73 //---------------------------------------------------------------------------
76 GetConstantValueAsSignedInt(const Value *V,
77 bool &isValidConstant)
79 if (!isa<Constant>(V))
81 isValidConstant = false;
85 isValidConstant = true;
87 if (V->getType() == Type::BoolTy)
88 return (int64_t) cast<ConstantBool>(V)->getValue();
90 if (V->getType()->isIntegral())
92 if (V->getType()->isSigned())
93 return cast<ConstantSInt>(V)->getValue();
95 assert(V->getType()->isUnsigned());
96 uint64_t Val = cast<ConstantUInt>(V)->getValue();
97 if (Val < INT64_MAX) // then safe to cast to signed
101 isValidConstant = false;
106 //---------------------------------------------------------------------------
107 // Function: FoldGetElemChain
110 // Fold a chain of GetElementPtr instructions containing only
111 // structure offsets into an equivalent (Pointer, IndexVector) pair.
112 // Returns the pointer Value, and stores the resulting IndexVector
113 // in argument chainIdxVec.
114 //---------------------------------------------------------------------------
117 FoldGetElemChain(const InstructionNode* getElemInstrNode,
118 vector<Value*>& chainIdxVec)
120 MemAccessInst* getElemInst = (MemAccessInst*)
121 getElemInstrNode->getInstruction();
123 // Initialize return values from the incoming instruction
124 Value* ptrVal = NULL;
125 assert(chainIdxVec.size() == 0);
127 // Now chase the chain of getElementInstr instructions, if any.
128 // Check for any array indices and stop there.
130 const InstrTreeNode* ptrChild = getElemInstrNode;
131 while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
132 ptrChild->getOpLabel() == GetElemPtrIdx)
134 // Child is a GetElemPtr instruction
135 getElemInst = (MemAccessInst*)
136 ((InstructionNode*) ptrChild)->getInstruction();
137 const vector<Value*>& idxVec = getElemInst->copyIndices();
138 bool allStructureOffsets = true;
140 // If it is a struct* access, the first offset must be array index [0],
141 // and all other offsets must be structure (not array) offsets
142 if (!isa<ConstantUInt>(idxVec.front()) ||
143 cast<ConstantUInt>(idxVec.front())->getValue() != 0)
144 allStructureOffsets = false;
146 if (allStructureOffsets)
147 for (unsigned int i=1; i < idxVec.size(); i++)
148 if (idxVec[i]->getType() == Type::UIntTy)
150 allStructureOffsets = false;
154 if (allStructureOffsets)
155 { // Get pointer value out of ptrChild and *prepend* its index vector
156 ptrVal = getElemInst->getPointerOperand();
157 chainIdxVec.insert(chainIdxVec.begin(),
158 idxVec.begin()+1, idxVec.end());
159 ((InstructionNode*) ptrChild)->markFoldedIntoParent();
160 // mark so no code is generated
162 else // cannot fold this getElementPtr instr. or any further ones
165 ptrChild = ptrChild->leftChild();
172 //------------------------------------------------------------------------
173 // Function Set2OperandsFromInstr
174 // Function Set3OperandsFromInstr
176 // For the common case of 2- and 3-operand arithmetic/logical instructions,
177 // set the m/c instr. operands directly from the VM instruction's operands.
178 // Check whether the first or second operand is 0 and can use a dedicated "0"
180 // Check whether the second operand should use an immediate field or register.
181 // (First and third operands are never immediates for such instructions.)
184 // canDiscardResult: Specifies that the result operand can be discarded
185 // by using the dedicated "0"
187 // op1position, op2position and resultPosition: Specify in which position
188 // in the machine instruction the 3 operands (arg1, arg2
189 // and result) should go.
191 // RETURN VALUE: unsigned int flags, where
192 // flags & 0x01 => operand 1 is constant and needs a register
193 // flags & 0x02 => operand 2 is constant and needs a register
194 //------------------------------------------------------------------------
197 Set2OperandsFromInstr(MachineInstr* minstr,
198 InstructionNode* vmInstrNode,
199 const TargetMachine& target,
200 bool canDiscardResult,
204 Set3OperandsFromInstr(minstr, vmInstrNode, target,
205 canDiscardResult, op1Position,
206 /*op2Position*/ -1, resultPosition);
211 Set3OperandsFromInstr(MachineInstr* minstr,
212 InstructionNode* vmInstrNode,
213 const TargetMachine& target,
214 bool canDiscardResult,
219 assert(op1Position >= 0);
220 assert(resultPosition >= 0);
223 minstr->SetMachineOperandVal(op1Position, MachineOperand::MO_VirtualRegister,
224 vmInstrNode->leftChild()->getValue());
226 // operand 2 (if any)
227 if (op2Position >= 0)
228 minstr->SetMachineOperandVal(op2Position, MachineOperand::MO_VirtualRegister,
229 vmInstrNode->rightChild()->getValue());
231 // result operand: if it can be discarded, use a dead register if one exists
232 if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
233 minstr->SetMachineOperandReg(resultPosition,
234 target.getRegInfo().getZeroRegNum());
236 minstr->SetMachineOperandVal(resultPosition,
237 MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
241 MachineOperand::MachineOperandType
242 ChooseRegOrImmed(Value* val,
243 MachineOpCode opCode,
244 const TargetMachine& target,
246 unsigned int& getMachineRegNum,
247 int64_t& getImmedValue)
249 MachineOperand::MachineOperandType opType =
250 MachineOperand::MO_VirtualRegister;
251 getMachineRegNum = 0;
254 // Check for the common case first: argument is not constant
256 Constant *CPV = dyn_cast<Constant>(val);
257 if (!CPV) return opType;
259 if (ConstantBool *CPB = dyn_cast<ConstantBool>(CPV))
261 if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
263 getMachineRegNum = target.getRegInfo().getZeroRegNum();
264 return MachineOperand::MO_MachineRegister;
268 return MachineOperand::MO_SignExtendedImmed;
271 // Otherwise it needs to be an integer or a NULL pointer
272 if (! CPV->getType()->isIntegral() &&
273 ! (CPV->getType()->isPointerType() &&
277 // Now get the constant value and check if it fits in the IMMED field.
278 // Take advantage of the fact that the max unsigned value will rarely
279 // fit into any IMMED field and ignore that case (i.e., cast smaller
280 // unsigned constants to signed).
283 if (CPV->getType()->isPointerType())
287 else if (CPV->getType()->isSigned())
289 intValue = cast<ConstantSInt>(CPV)->getValue();
293 uint64_t V = cast<ConstantUInt>(CPV)->getValue();
294 if (V >= INT64_MAX) return opType;
295 intValue = (int64_t)V;
298 if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
300 opType = MachineOperand::MO_MachineRegister;
301 getMachineRegNum = target.getRegInfo().getZeroRegNum();
303 else if (canUseImmed &&
304 target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
306 opType = MachineOperand::MO_SignExtendedImmed;
307 getImmedValue = intValue;
314 //---------------------------------------------------------------------------
315 // Function: FixConstantOperandsForInstr
318 // Special handling for constant operands of a machine instruction
319 // -- if the constant is 0, use the hardwired 0 register, if any;
320 // -- if the constant fits in the IMMEDIATE field, use that field;
321 // -- else create instructions to put the constant into a register, either
322 // directly or by loading explicitly from the constant pool.
324 // In the first 2 cases, the operand of `minstr' is modified in place.
325 // Returns a vector of machine instructions generated for operands that
326 // fall under case 3; these must be inserted before `minstr'.
327 //---------------------------------------------------------------------------
329 vector<MachineInstr*>
330 FixConstantOperandsForInstr(Instruction* vmInstr,
331 MachineInstr* minstr,
332 TargetMachine& target)
334 vector<MachineInstr*> loadConstVec;
336 const MachineInstrDescriptor& instrDesc =
337 target.getInstrInfo().getDescriptor(minstr->getOpCode());
339 Method* method = vmInstr->getParent()->getParent();
341 for (unsigned op=0; op < minstr->getNumOperands(); op++)
343 const MachineOperand& mop = minstr->getOperand(op);
345 // skip the result position (for efficiency below) and any other
346 // positions already marked as not a virtual register
347 if (instrDesc.resultPos == (int) op ||
348 mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
349 mop.getVRegValue() == NULL)
354 Value* opValue = mop.getVRegValue();
355 bool constantThatMustBeLoaded = false;
357 if (Constant *opConst = dyn_cast<Constant>(opValue))
359 unsigned int machineRegNum;
361 MachineOperand::MachineOperandType opType =
362 ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
363 (target.getInstrInfo().getImmedConstantPos(minstr->getOpCode()) == (int) op),
364 machineRegNum, immedValue);
366 if (opType == MachineOperand::MO_MachineRegister)
367 minstr->SetMachineOperandReg(op, machineRegNum);
368 else if (opType == MachineOperand::MO_VirtualRegister)
369 constantThatMustBeLoaded = true; // load is generated below
371 minstr->SetMachineOperandConst(op, opType, immedValue);
374 if (constantThatMustBeLoaded || isa<GlobalValue>(opValue))
375 { // opValue is a constant that must be explicitly loaded into a reg.
376 TmpInstruction* tmpReg = InsertCodeToLoadConstant(method, opValue, vmInstr,
377 loadConstVec, target);
378 minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
384 // Also, check for implicit operands used (not those defined) by the
385 // machine instruction. These include:
386 // -- arguments to a Call
387 // -- return value of a Return
388 // Any such operand that is a constant value needs to be fixed also.
389 // The current instructions with implicit refs (viz., Call and Return)
390 // have no immediate fields, so the constant always needs to be loaded
393 for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
394 if (isa<Constant>(minstr->getImplicitRef(i)) ||
395 isa<GlobalValue>(minstr->getImplicitRef(i)))
397 Value* oldVal = minstr->getImplicitRef(i);
398 TmpInstruction* tmpReg =
399 InsertCodeToLoadConstant(method, oldVal, vmInstr, loadConstVec, target);
400 minstr->setImplicitRef(i, tmpReg);